1: /* 2: * Copyright (c) 1987 Regents of the University of California. 3: * All rights reserved. The Berkeley software License Agreement 4: * specifies the terms and conditions for redistribution. 5: * 6: * @(#)mch_backup.s 1.2 (2.11BSD GTE) 12/26/92 7: */ 8: 9: #include "DEFS.h" 10: 11: SPACE(GLOBAL, ssr, 3*2) / contents of MM registers SSR0-2 12: / after trap 13: 14: /* 15: * unwind(ar0::r0, mod::r1) 16: * caddr_t ar0; 17: * u_char mod; 18: * 19: * Unwind a register modification from a partially completed aborted 20: * instruction. Ar0 is the address of the user's register r0 as saved in 21: * the stack (_regloc contains the relative indexes of the the user's 22: * registers from ar0). Mod contains a register modification recorded as: 23: * 24: * 7 3 2 0 25: * +------------------------+ 26: * | displacement | reg | 27: * +------------------------+ 28: * 29: * where "reg" is the index of the modified register and displacement is 30: * the 2's complement displacement of the modification. 31: */ 32: unwind: 33: mov r1,-(sp) / grab displacement 34: asr (sp) / tmp = mod >> 3 { signed shift } 35: asr (sp) 36: asr (sp) 37: bic $!7,r1 / mod = _regloc[mod&7] * sizeof(int) 38: movb _regloc(r1),r1 39: asl r1 40: add r0,r1 / ar0[mod] -= tmp 41: sub (sp)+,(r1) 42: rts pc 43: 44: /* 45: * backup(ar0) 46: * caddr_t ar0; 47: * 48: * Back up user CPU state after aborted instruction. Called from trap when 49: * attempting an automatic stack grow to restore the user's state prior to 50: * a stack fault. Returns zero if successful. 51: */ 52: #ifndef KERN_NONSEP 53: /* 54: * Backup routine for use with machines with SSR1 and SSR2 (saved in ssr+2 55: * and ssr+4 by trap). SSR1 records any auto-increments and/or decrements 56: * that were already performed for the aborted instruction. SSR2 holds 57: * the adddress of the instruction which faulted. 58: */ 59: ENTRY(backup) 60: mov 2(sp),r0 / r0 = ar0 61: movb ssr+2,r1 / undo first register modification from 62: jsr pc,unwind / saved SSR1 63: movb ssr+3,r1 / and second ... 64: jsr pc,unwind 65: movb _regloc+7,r1 / ar0[_regloc[PC] * sizeof(int)] 66: asl r1 / = saved SSR2 67: add r0,r1 68: mov ssr+4,(r1) 69: clr r0 / and return success 70: rts pc 71: 72: #else KERN_NONSEP 73: /* 74: * 11/40 version of backup, for use with no SSR1 and SSR2. Actually SSR1 75: * usually exists for all processors except the '34 and '40 but always 76: * reads as zero on those without separate I&D ... 77: */ 78: 79: .bss 80: bflg: .=.+1 81: jflg: .=.+1 82: fflg: .=.+1 83: .text 84: 85: ENTRY(backup) 86: mov 2(sp),ssr+2 / pass ar0 to the real backup routine 87: mov r2,-(sp) / backup needs an extra register 88: jsr pc,backup 89: mov r2,ssr+2 / save computed register modification 90: mov (sp)+,r2 / mask and restore r2 91: movb jflg,r0 / if backup failed, return failure 92: bne 1f 93: mov 2(sp),r0 / r0 = ar0 94: movb ssr+2,r1 / undo register modifications 95: jsr pc,unwind 96: movb ssr+3,r1 97: jsr pc,unwind 98: movb _regloc+7,r1 / ar0[_regloc[PC] * sizeof(int)] = 99: asl r1 / computed fault pc 100: add r0,r1 101: mov ssr+4,(r1) 102: clr r0 / and indicate success 103: 2: 104: rts pc 105: 106: /* 107: * Hard part: simulate the ssr2 register missing on 11/40 and similar 108: * processors. 109: */ 110: backup: 111: clr r2 / backup register ssr1 112: mov $1,bflg / clrs jflg 113: clrb fflg 114: mov ssr+4,r0 115: jsr pc,fetch 116: mov r0,r1 117: ash $-11.,r0 118: bic $!36,r0 119: jmp *0f(r0) 120: 0: t00; t01; t02; t03; t04; t05; t06; t07 121: t10; t11; t12; t13; t14; t15; t16; t17 122: 123: t00: 124: clrb bflg 125: 126: t10: 127: mov r1,r0 128: swab r0 129: bic $!16,r0 130: jmp *0f(r0) 131: 0: u0; u1; u2; u3; u4; u5; u6; u7 132: 133: u6: / single op, m[tf]pi, sxt, illegal 134: bit $400,r1 135: beq u5 / all but m[tf], sxt 136: bit $200,r1 137: beq 1f / mfpi 138: bit $100,r1 139: bne u5 / sxt 140: 141: / Simulate mtpi with double (sp)+,dd. 142: bic $4000,r1 / turn instr into (sp)+ 143: br t01 144: 145: / Simulate mfpi with double ss,-(sp). 146: 1: 147: ash $6,r1 148: bis $46,r1 / -(sp) 149: br t01 150: 151: u4: / jsr 152: mov r1,r0 153: jsr pc,setreg / assume no fault 154: bis $173000,r2 / -2 from sp 155: rts pc 156: 157: t07: / EIS 158: clrb bflg 159: 160: u0: / jmp, swab 161: u5: / single op 162: f5: / movei, movfi 163: ff1: / ldfps 164: ff2: / stfps 165: ff3: / stst 166: mov r1,r0 167: br setreg 168: 169: t01: / mov 170: t02: / cmp 171: t03: / bit 172: t04: / bic 173: t05: / bis 174: t06: / add 175: t16: / sub 176: clrb bflg 177: 178: t11: / movb 179: t12: / cmpb 180: t13: / bitb 181: t14: / bicb 182: t15: / bisb 183: mov r1,r0 184: ash $-6,r0 185: jsr pc,setreg 186: swab r2 187: mov r1,r0 188: jsr pc,setreg 189: 190: / If delta(dest) is zero, no need to fetch source. 191: bit $370,r2 192: beq 1f 193: 194: / If mode(source) is R, no fault is possible. 195: bit $7000,r1 196: beq 1f 197: 198: / If reg(source) is reg(dest), too bad. 199: mov r2,-(sp) 200: bic $174370,(sp) 201: cmpb 1(sp),(sp)+ 202: beq u7 203: 204: / Start source cycle. Pick up value of reg. 205: mov r1,r0 206: ash $-6,r0 207: bic $!7,r0 208: movb _regloc(r0),r0 209: asl r0 210: add ssr+2,r0 211: mov (r0),r0 212: 213: / If reg has been incremented, must decrement it before fetch. 214: bit $174000,r2 215: ble 2f 216: dec r0 217: bit $10000,r2 218: beq 2f 219: dec r0 220: 2: 221: 222: / If mode is 6,7 fetch and add X(R) to R. 223: bit $4000,r1 224: beq 2f 225: bit $2000,r1 226: beq 2f 227: mov r0,-(sp) 228: mov ssr+4,r0 229: add $2,r0 230: jsr pc,fetch 231: add (sp)+,r0 232: 2: 233: 234: / Fetch operand. If mode is 3, 5, or 7, fetch *. 235: jsr pc,fetch 236: bit $1000,r1 237: beq 1f 238: bit $6000,r1 239: bne fetch 240: 1: 241: rts pc 242: 243: t17: / floating point instructions 244: 245: clrb bflg 246: mov r1,r0 247: swab r0 248: bic $!16,r0 249: jmp *0f(r0) 250: 0: f0; f1; f2; f3; f4; f5; f6; f7 251: 252: f0: 253: mov r1,r0 254: ash $-5,r0 255: bic $!16,r0 256: jmp *0f(r0) 257: 0: ff0; ff1; ff2; ff3; ff4; ff5; ff6; ff7 258: 259: f1: / mulf, modf 260: f2: / addf, movf 261: f3: / subf, cmpf 262: f4: / movf, divf 263: ff4: / clrf 264: ff5: / tstf 265: ff6: / absf 266: ff7: / negf 267: inc fflg 268: mov r1,r0 269: br setreg 270: 271: f6: 272: bit $400,r1 273: beq f1 / movfo 274: br f5 / movie 275: 276: f7: 277: bit $400,r1 278: beq f5 / movif 279: br f1 / movof 280: 281: ff0: / cfcc, setf, setd, seti, setl 282: 283: u1: / br 284: u2: / br 285: u3: / br 286: u7: / illegal 287: incb jflg 288: rts pc 289: 290: setreg: 291: mov r0,-(sp) 292: bic $!7,r0 293: bis r0,r2 294: mov (sp)+,r0 295: ash $-3,r0 296: bic $!7,r0 297: movb 0f(r0),r0 298: tstb bflg 299: beq 1f 300: bit $2,r2 301: beq 2f 302: bit $4,r2 303: beq 2f 304: 1: 305: cmp r0,$20 306: beq 2f 307: cmp r0,$-20 308: beq 2f 309: asl r0 310: 2: 311: 312: tstb fflg 313: beq 3f 314: asl r0 315: stfps r1 316: bit $200,r1 317: beq 3f 318: asl r0 319: 3: 320: 321: bisb r0,r2 322: rts pc 323: 324: 0: .byte 0,0,10,20,-10,-20,0,0 325: 326: fetch: 327: bic $1,r0 328: mov nofault,-(sp) 329: mov $1f,nofault 330: mfpi (r0) 331: mov (sp)+,r0 332: mov (sp)+,nofault 333: rts pc 334: 335: 1: 336: mov (sp)+,nofault 337: clrb r2 / clear out dest on fault 338: mov $-1,r0 339: rts pc 340: #endif KERN_NONSEP
Defined functions
Defined variables
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Last modified: 1992-12-27
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