2.11BSD#431 - /usr/src/sys/pdpuba/hpreg.h

   1: /*
   2:  * Copyright (c) 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)hpreg.h	2.0 (2.11BSD) 1995/07/20
   7:  */
   8: 
   9: /*
  10:  * Definitions for SMD-type disk drives and drivers.
  11:  */
  12: 
  13: #define XP_CC   0x1 /* drivedata[0] bit indicating presence of current
  14: 			 * cylinder 'hpcc' register.  Only set for RP04,5,6,7.
  15: 			*/
  16: #define XP_NOSEARCH 0x2 /* drivedata[0] bit indicating lack of search cmd */
  17: 
  18: /*
  19:  *	Controller registers and bits
  20:  */
  21: struct hpdevice
  22: {
  23:     union   {
  24:         int w;
  25:         char    c[2];
  26:     }   hpcs1;      /* control and status 1 register */
  27:     short   hpwc;       /* word count register */
  28:     caddr_t hpba;       /* UNIBUS address register */
  29:     short   hpda;       /* desired address register */
  30:     union   {
  31:         int w;
  32:         char    c[2];
  33:     }   hpcs2;      /* control and status 2 register */
  34:     short   hpds;       /* drive status register */
  35:     short   hper1;      /* error register 1 */
  36:     short   hpas;       /* attention summary register */
  37:     short   hpla;       /* look ahead register */
  38:     short   hpdb;       /* data buffer register */
  39:     short   hpmr;       /* maintenance register (1) */
  40:     short   hpdt;       /* drive type register */
  41:     short   hpsn;       /* serial number register */
  42:     short   hpof;       /* offset register */
  43:     short   hpdc;       /* desired cylinder address register */
  44:     short   hpcc;       /* HP: current cylinder register */
  45: #define rmhr    hpcc        /* RM: holding register */
  46:     short   hper2;      /* HP: error register 2 */
  47: #define rmmr2   hper2       /* RM: maintenance register 2 */
  48:     short   hper3;      /* HP: error register 3 */
  49: #define rmer2   hper3       /* RM: error register 2 */
  50:     short   hpec1;      /* burst error bit position */
  51:     short   hpec2;      /* burst error bit pattern */
  52:     short   hpbae;      /* bus address extension register (RH70 only) */
  53:     short   hpcs3;      /* control and status 3 register (RH70 only) */
  54: };
  55: 
  56: /* Other bits of hpcs1 */
  57: #define HP_SC       0100000     /* special condition */
  58: #define HP_TRE      0040000     /* transfer error */
  59: #define HP_MCPE     0020000     /* MASSBUS control bus read parity error */
  60: /* bit 12 is unused */
  61: #define HP_DVA      0004000     /* drive available */
  62: /* bits 9 and 8 are the extended address bits */
  63: #define HP_RDY      0000200     /* controller ready */
  64: #define HP_IE       0000100     /* interrupt enable */
  65: /* bits 5-1 are the command */
  66: #define HP_GO       0000001
  67: #define HP_BITS     \
  68: "\10\20SC\17TRE\16MCPE\14DVA\10RDY\7IE\1GO"
  69: 
  70: /* commands */
  71: #define HP_NOP      000
  72: #define HP_UNLOAD   002     /* offline drive */
  73: #define HP_SEEK     004     /* seek */
  74: #define HP_RECAL    006     /* recalibrate */
  75: #define HP_DCLR     010     /* drive clear */
  76: #define HP_RELEASE  012     /* release */
  77: #define HP_OFFSET   014     /* offset */
  78: #define HP_RTC      016     /* return to center-line */
  79: #define HP_PRESET   020     /* read-in preset */
  80: #define HP_PACK     022     /* pack acknowledge */
  81: #define HP_SEARCH   030     /* search */
  82: #define HP_WCDATA   050     /* write check data */
  83: #define HP_WCHDR    052     /* write check header and data */
  84: #define HP_WCOM     060     /* write */
  85: #define HP_WHDR     062     /* write header and data */
  86: #define HP_RCOM     070     /* read data */
  87: #define HP_RHDR     072     /* read header and data */
  88: /* The following two are optionally enabled on some non-DEC controllers */
  89: #define HP_BOOT     074     /* boot */
  90: #define HP_FORMAT   076     /* format */
  91: 
  92: /* hpcs2 */
  93: #define HPCS2_DLT   0100000     /* data late */
  94: #define HPCS2_WCE   0040000     /* write check error */
  95: #define HPCS2_UPE   0020000     /* UNIBUS parity error */
  96: #define HPCS2_NED   0010000     /* nonexistent drive */
  97: #define HPCS2_NEM   0004000     /* nonexistent memory */
  98: #define HPCS2_PGE   0002000     /* programming error */
  99: #define HPCS2_MXF   0001000     /* missed transfer */
 100: #define HPCS2_MDPE  0000400     /* MASSBUS data read parity error */
 101: #define HPCS2_OR    0000200     /* output ready */
 102: #define HPCS2_IR    0000100     /* input ready */
 103: #define HPCS2_CLR   0000040     /* controller clear */
 104: #define HPCS2_PAT   0000020     /* parity test */
 105: #define HPCS2_BAI   0000010     /* address increment inhibit */
 106: /* bits 2-0 are drive select */
 107: 
 108: #define HPCS2_BITS \
 109: "\10\20DLT\17WCE\16UPE\15NED\14NEM\13PGE\12MXF\11MDPE\
 110: \10OR\7IR\6CLR\5PAT\4BAI"
 111: 
 112: /* hpds */
 113: #define HPDS_ATA    0100000     /* attention active */
 114: #define HPDS_ERR    0040000     /* composite drive error */
 115: #define HPDS_PIP    0020000     /* positioning in progress */
 116: #define HPDS_MOL    0010000     /* medium on line */
 117: #define HPDS_WRL    0004000     /* write locked */
 118: #define HPDS_LST    0002000     /* last sector transferred */
 119: #define HPDS_DAE    0001000     /* dual access enabled (programmable) */
 120: #define HPDS_DPR    0000400     /* drive present */
 121: #define HPDS_DRY    0000200     /* drive ready */
 122: #define HPDS_VV     0000100     /* volume valid */
 123: /* bits 5-3, 1 are spare */
 124: #define HPDS_ILV    0000004     /* interleaved */
 125: #define HPDS_OM     0000001     /* offset mode */
 126: 
 127: #define HPDS_DREADY (HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV)
 128: 
 129: #define HPDS_BITS \
 130: "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12DAE\11DPR\10DRY\7VV\3ILV\1OM"
 131: 
 132: /* hper1 */
 133: #define HPER1_DCK   0100000     /* data check */
 134: #define HPER1_UNS   0040000     /* drive unsafe */
 135: #define HPER1_OPI   0020000     /* operation incomplete */
 136: #define HPER1_DTE   0010000     /* drive timing error */
 137: #define HPER1_WLE   0004000     /* write lock error */
 138: #define HPER1_IAE   0002000     /* invalid address error */
 139: #define HPER1_AOE   0001000     /* address overflow error */
 140: #define HPER1_HCRC  0000400     /* header crc error */
 141: #define HPER1_HCE   0000200     /* header compare error */
 142: #define HPER1_ECH   0000100     /* ecc hard error */
 143: #define HPER1_WCF   0000040     /* write clock fail (0) */
 144: #define HPER1_FER   0000020     /* format error */
 145: #define HPER1_PAR   0000010     /* parity error */
 146: #define HPER1_RMR   0000004     /* register modification refused */
 147: #define HPER1_ILR   0000002     /* illegal register */
 148: #define HPER1_ILF   0000001     /* illegal function */
 149: 
 150: #define HPER1_BITS \
 151: "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\
 152: \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF"
 153: 
 154: /* hpdt */
 155: #define HPDT_NBA    0100000     /* not block addressed; always 0 */
 156: #define HPDT_TAPE   0040000     /* tape drive; always 0 */
 157: #define HPDT_MH     0020000     /* moving head; always 1 */
 158: /* bit 12 is unused */
 159: #define HPDT_DRR    0004000     /* drive request required  */
 160: /* bits 10-9 are unused */
 161: /* bits 8-0 are drive type; the correct values are hard to determine */
 162: #define HPDT_RM02   0000025     /* rm02, possibly rm03? */
 163: #define HPDT_RM80   0000026     /* rm80 */
 164: #define HPDT_RM05   0000027     /* rm05 */
 165: #define HPDT_RM03   0000024     /* rm03 */
 166: #define HPDT_RP04   0000020     /* rp04 */
 167: #define HPDT_RP05   0000021     /* rp05 */
 168: #define HPDT_RP06   0000022     /* rp06 */
 169: #define HPDT_RP07   0000042     /* rp07 */
 170: 
 171: /* hpof */
 172: #define HPOF_FMT22  0010000     /* 16 bit format */
 173: #define HPOF_ECI    0004000     /* ecc inhibit */
 174: #define HPOF_HCI    0002000     /* header compare inhibit */
 175: 
 176: /* THE SC21 ACTUALLY JUST IMPLEMENTS ADVANCE/RETARD... */
 177: #define HPOF_P400   0020        /*  +400 uinches */
 178: #define HPOF_M400   0220        /*  -400 uinches */
 179: #define HPOF_P800   0040        /*  +800 uinches */
 180: #define HPOF_M800   0240        /*  -800 uinches */
 181: #define HPOF_P1200  0060        /* +1200 uinches */
 182: #define HPOF_M1200  0260        /* -1200 uinches */
 183: 
 184: #define HPOF_BITS   \
 185: "\10\15FMT22\14ECI\13HCI\10OD"
 186: 
 187: /*
 188:  * rmhr
 189:  *
 190:  * Emulex (i.e non DEC) controllers implement the ability to query for
 191:  * the drive geometry by placing these codes into the 'holding register'.
 192: */
 193: #define HPHR_MAXCYL 0x8017      /* max cylinder */
 194: #define HPHR_MAXTRAK    0x8018      /* max track/cylinder */
 195: #define HPHR_MAXSECT    0x8019      /* max sector/track */
 196: 
 197: /* rmer2: These are the bits for an RM error register 2 */
 198: #define RMER2_BSE   0100000     /* bad sector error */
 199: #define RMER2_SKI   0040000     /* seek incomplete */
 200: #define RMER2_DPE   0020000     /* drive plug error */
 201: #define RMER2_IVC   0010000     /* invalid command */
 202: #define RMER2_LSC   0004000     /* loss of system clock */
 203: #define RMER2_LBC   0002000     /* loss of bit clock */
 204: /* bits 9-8 are unused */
 205: #define RMER2_DVC   0000200     /* device check */
 206: /* bits 6-4 are unused */
 207: #define RMER2_MDPE  0000010     /* MASSBUS data read parity error */
 208: /* bits 2-0 are unused */
 209: 
 210: #define RMER2_BITS \
 211: "\10\20BSE\17SKI\16DPE\15IVC\14LSC\13LBC\10DVC\4MDPE"
 212: 
 213: /* hpcs3 */
 214: #define HPCS3_APE   0100000     /* address parity error */
 215: #define HPCS3_DPE   0060000     /* data parity error */
 216: #define HPCS3_WCE   0017000     /* write check error */
 217: #define HPCS3_DW    0002000     /* double word */
 218: /* bits 9-8 are unused */
 219: #define HPCS3_IE    0000100     /* interrupt enable */
 220: /* bits 5-4 are unused */
 221: /* bits 3-0 are inverted parity check */
 222: 
 223: #define HPCS3_BITS  \
 224: "\10\20APE\17DPE\15WCE\13DW\7IE"
 225: 
 226: /*
 227:  * Systems Industries kludge: use value in
 228:  * the serial # register to figure out real drive type.
 229:  */
 230: #define SIMB_MB 0xff00      /* model byte value */
 231: #define SIMB_S6 0x2000      /* switch s6 */
 232: #define SIMB_LU 0x0007      /* logical unit (should = drive #) */
 233: 
 234: #define SI9775D 0x0700      /* 9775 direct */
 235: #define SI9775M 0x0e00      /* 9775 mapped */
 236: #define SI9730D 0x0b00      /* 9730 or 9784 direct */
 237: #define SI9730M 0x0d00      /* 9730 or 9784 mapped */
 238: #define SI9766  0x0300      /* 9766 */
 239: #define SI9762  0x0100      /* 9762 */
 240: #define SICAPD  0x0500      /* Capricorn direct */
 241: #define SICAPN  0x0400      /* Capricorn mapped */
 242: #define SI9751D 0x0f00      /* Eagle direct */
 243: 
 244: #define SIRM03  0x8000      /* RM03 indication */
 245: #define SIRM05  0x0000      /* RM05 pseudo-indication */

Defined struct's

Defined macros

Usage of this include