2.9BSD - /usr/include/sys/cpu.h

   1: #if PDP11 == 44
   2: 
   3: #define PDP1144_CMER    ((physadr) 0177744)
   4: #define PDP1144_CCR ((physadr) 0177746)
   5: #define PDP1144_CMR ((physadr) 0177750)
   6: #define PDP1144_CHR ((physadr) 0177752)
   7: #define PDP1144_CDR ((physadr) 0177754)
   8: 
   9: /* bits in cache memory error register */
  10: #define CME_CMPE    0100000     /* cache memory parity error */
  11: /* bits 14-8 are unused */
  12: #define CME_PEHI    0000200     /* parity error high byte */
  13: #define CME_PELO    0000100     /* parity error low byte */
  14: #define CME_TPE     0000040     /* tag parity error */
  15: /* bits 4-0 are unused */
  16: #define CME_BITS    \
  17: "\10\20CMPE\10PEHI\7PELO\6TPE"
  18: 
  19: /* bits in cache control register */
  20: /* bits 15-14 are unused */
  21: #define CCR_VSIU    0020000     /* valid store in use (read only) */
  22: #define CCR_VCIP    0010000     /* valid clear in progress (read only) */
  23: /* bit 11 is unused */
  24: #define CCR_WWPT    0002000     /* write wrong parity tag */
  25: #define CCR_UCB     0001000     /* unconditional cache bypass */
  26: #define CCR_FC      0000400     /* flush cache (write only) */
  27: #define CCR_PEA     0000200     /* parity error abort */
  28: #define CCR_WWPD    0000100     /* write wrong parity data */
  29: /* bits 5-4 are unused */
  30: #define CCR_FMHI    0000010     /* force miss high */
  31: #define CCR_FMLO    0000004     /* force miss low */
  32: /* bit 1 is unused */
  33: #define CCR_DCPI    0000001     /* disable cache parity interrupt */
  34: #define CCR_BITS    \
  35: "\10\16VSIU\15VCIP\13WWPT\12UCB\11FC\10PEA\7WWPD\4FMHI\3FMLO\1DCPI"
  36: 
  37: /* bits in cache maintenance register */
  38: #define CMR_CMP1    0100000     /* compare 1 (write only) */
  39: #define CMR_CMP2    0040000     /* compare 2 (write only) */
  40: #define CMR_CMP3    0020000     /* compare 3 (write only) */
  41: #define CMR_V       0010000     /* valid (write only) */
  42: #define CMR_HPB     0004000     /* high parity bit (write only) */
  43: #define CMR_LPB     0002000     /* low parity bit (write only) */
  44: #define CMR_TPB     0001000     /* tag parity bit */
  45: #define CMR_HIT     0000400     /* hit */
  46: /* bits 7-5 are unused */
  47: #define CMR_ESA     0000020     /* enable stop action */
  48: #define CMR_AM      0000010     /* address matched */
  49: #define CMR_EHA     0000004     /* enable halt action */
  50: #define CMR_HODO    0000002     /* hit on destination only */
  51: #define CMR_TDAR    0000001     /* tag data from address match register */
  52: #define CMR_BITS    \
  53: "\10\20CMP1\17CMP2\16CMP3\15V\14HPB\13LPB\12TPB\11H\5ESA\4AM\3EHA\2HODO\1TDAR"
  54: 
  55: #endif	PDP11 == 44
  56: 
  57: #if PDP11 == 60
  58: 
  59: #define PDP1160_MSR ((physadr) 0177744)
  60: #define PDP1160_CCR ((physadr) 0177746)
  61: #define PDP1160_HMR ((physadr) 0177752)
  62: 
  63: /* bits in memory system register */
  64: #define MSR_CPUAB   0100000     /* cpu abort
  65: /* bits 14-8 are unused */
  66: #define MSR_PEHI    0000200     /* high byte parity error */
  67: #define MSR_PELO    0000100     /* low byte parity error */
  68: #define MSR_TPE     0000040     /* tag parity error */
  69: /* bits 4-0 are unused */
  70: #define MSR_BITS    \
  71: "\10\20CPUAB\10PEHI\7PELO\6TPE"
  72: 
  73: /* bits in cache control register */
  74: /* bits 15-8 are unused */
  75: #define CCR_CPEA    0000200     /* cache parity error abort */
  76: #define CCR_WWP     0000100     /* write wrong parity */
  77: /* bits 5-4 are unused */
  78: #define CCR_FM1     0000010     /* force miss 1 */
  79: #define CCR_FM2     0000004     /* force miss 2 */
  80: /* bit 1 is unused */
  81: #define CCR_DT      0000001     /* disable traps */
  82: #define CCR_BITS    \
  83: "\10\10CPEA\7WWP\4FM1\3FM2\1DT"
  84: 
  85: #endif	PDP11 == 60
  86: 
  87: #if PDP11 == 70
  88: 
  89: #define PDP1170_LEAR    ((physadr) 0177740)
  90: #define PDP1170_HEAR    ((physadr) 0177742)
  91: #define PDP1170_MSER    ((physadr) 0177744)
  92: #define PDP1170_CCR ((physadr) 0177746)
  93: #define PDP1170_CMR ((physadr) 0177750)
  94: #define PDP1170_HMR ((physadr) 0177752)
  95: #define PDP1170_LSR ((physadr) 0177760)
  96: #define PDP1170_USR ((physadr) 0177762)
  97: #define PDP1170_SID ((physadr) 0177764)
  98: #define PDP1170_CPUER   ((physadr) 0177766)
  99: #define PDP1170_MBR ((physadr) 0177770)
 100: 
 101: /* bits in memory system error register */
 102: #define MSER_CPUAB  0100000     /* cpu abort */
 103: #define MSER_CPUABAE    0040000     /* cpu abort after error */
 104: #define MSER_UPE    0020000     /* UNIBUS parity error */
 105: #define MSER_UMPE   0010000     /* UNIBUS multiple parity error */
 106: #define MSER_CPUER  0004000     /* cpu error */
 107: #define MSER_UE     0002000     /* UNIBUS error */
 108: #define MSER_CPUUA  0001000     /* cpu UNIBUS abort */
 109: #define MSER_EM     0000400     /* error in maintenance */
 110: #define MSER_DMG1   0000200     /* data memory group 1 */
 111: #define MSER_DMG0   0000100     /* data memory group 0 */
 112: #define MSER_AMG1   0000040     /* address memory group 1 */
 113: #define MSER_AMG0   0000020     /* address memory group 0 */
 114: #define MSER_MMOW   0000010     /* main memory odd word */
 115: #define MSER_MMEW   0000004     /* main memory even word */
 116: #define MSER_MMAPE  0000002     /* main memory address parity error */
 117: #define MSER_MMT    0000001     /* main memory timeout */
 118: #define MSER_BITS   \
 119: "\10\20CPUAB\17CPUABAE\16UPE\15UMPE\14CPUER\13UE\12CPUUA\11EM\10DMG1\
 120: \7DMG0\6AMG1\5AMG0\4MMOW\3MMER\2MMAPE\1MMT"
 121: 
 122: /* bits in cache control register */
 123: /* bits 15-6 are unused */
 124: #define CCR_FRG1    0000040     /* force replacement group 1 */
 125: #define CCR_FRG0    0000020     /* force replacement group 0 */
 126: #define CCR_FMG1    0000010     /* force miss group 1 */
 127: #define CCR_FMG0    0000004     /* force miss group 0 */
 128: #define CCR_DUT     0000002     /* disable UNIBUS traps */
 129: #define CCR_DT      0000001     /* disable traps */
 130: #define CCR_BITS    \
 131: "\10\6FRG1\5FRG0\4FMG1\3FMG0\2DUT\1DT"
 132: 
 133: /* bits in cpu error register */
 134: /* bits 15-8 are unused */
 135: #define CPUER_ILH   0000200     /* illegal halt */
 136: #define CPUER_OAE   0000100     /* odd address error */
 137: #define CPUER_NXM   0000040     /* nonexistent memory */
 138: #define CPUER_UTIMO 0000020     /* UNIBUS timeout */
 139: #define CPUER_YZSL  0000010     /* yellow zone stack limit */
 140: #define CPUER_RZSL  0000004     /* red zone stack limit */
 141: #define CPUER_BITS  \
 142: "\10\10ILH\7OAE\6NXM\5UIMO\4YZSL\3RZSL"
 143: 
 144: #endif	PDP11 == 70

Defined macros