2.9BSD - /usr/include/sys/hpreg.h

   1: /*
   2:  *	Definitions for SMD-type disk drives and drivers.
   3:  *	This file is used for RM02/03/05, RP04/05/06,
   4:  *	and Diva controllers.
   5:  */
   6: 
   7: #if NXP > 0
   8: /*
   9:  *	Structures used in the xp driver
  10:  *	to describe drives, controllers, and topology
  11:  */
  12: struct xp_controller {
  13:     struct  buf *xp_actf;       /* pointer to next active xputab */
  14:     struct  buf *xp_actl;       /* pointer to last active xputab */
  15:     struct  hpdevice *xp_addr;  /* csr address */
  16:     char    xp_flags;       /* controller-type flags */
  17:     char    xp_active;      /* nonzero if doing a transfer */
  18: };
  19: 
  20: struct xp_drive {
  21:     struct  xp_controller *xp_ctlr; /* controller to which slave attached */
  22:     char    xp_type;        /* drive type */
  23:     char    xp_unit;        /* slave number */
  24:     struct  size *xp_sizes;     /* pointer to sizes array */
  25:     char    xp_nsect;
  26:     char    xp_ntrack;
  27:     int xp_nspc;        /* sectors/cylinder */
  28:     int xp_cc;          /* current cylinder, for RM's */
  29: #ifdef  BADSECT
  30:     int xp_ncyl;        /* cylinders per pack */
  31: #endif
  32: };
  33: 
  34: /*
  35:  * bits in xp_flags:
  36:  */
  37: #define XP_NOCC     1       /* has no current cylinder register */
  38: #define XP_RH70     2       /* uses 22-bit addressing */
  39: #define XP_NOSEARCH 4       /* won't do search commands */
  40: 
  41: /*
  42:  * Defines for disk drive type registers
  43:  */
  44: #define RP  022     /* RP04/5/6 */
  45: #define RM03    024     /* RM03 */
  46: #define RM02    025     /* RM02 */
  47: #define RM05    027     /* RM05 */
  48: /*
  49:  * These two drive types are dummies because the actual numbers conflict
  50:  * with DEC controllers.  The RM5X actually reads as 25; the Diva Comp VI
  51:  * reads as 22.  Xp_drive must be patched at boot time or initialized.
  52:  */
  53: #define RM5X    076     /* Ampex 815 cyl. RM05 with Emulex Controller */
  54: #define DV  077     /* Diva Comp VI Controller */
  55: 
  56: #define HP_SECT     22
  57: #define HP_TRAC     19
  58: #define RP06_CYL    815
  59: #define RP04_CYL    411
  60: #define RM_SECT     32
  61: #define RM_TRAC     5
  62: #define RM_CYL      823
  63: #define RM5_SECT    32
  64: #define RM5_TRAC    19
  65: #define RM5_CYL     823
  66: #define RM5X_CYL    815
  67: #define DV_SECT     33
  68: #define DV_TRAC     19
  69: #define DV_CYL      815
  70: 
  71: /*
  72:  *	SI Eagle
  73:  */
  74: #define SI_SECT     48
  75: #define SI_TRAC     20
  76: #define SI_CYL      842
  77: #define SI_SN_MSK   017400      /* SI serial number mask */
  78: #define SI_SN_DT    07400       /* SI serial number drive type */
  79: 
  80: #ifdef  BADSECT
  81: #define NCYL(x)     (x)
  82: #else
  83: #define NCYL(x)     /* not used */
  84: #endif	BADSECT
  85: 
  86: /*
  87:  *  Macros to inititialize xp_drive entries.  These can be used as examples,
  88:  *  or as the actual initializers in ioconf.c.  The arguments are the number
  89:  *  of the controller to which the drive is attached, and the physical
  90:  *  drive unit number.  Used only if XP_PROBE is not defined.
  91:  */
  92: #define RM02_INIT(c,u)  \
  93:     { &xp_controller[c], RM02, u, &rm_sizes, \
  94:     RM_SECT, RM_TRAC, RM_SECT*RM_TRAC, 0, NCYL(RM_CYL)  }
  95: #define RM03_INIT(c,u)  \
  96:     { &xp_controller[c], RM03, u, &rm_sizes, \
  97:     RM_SECT, RM_TRAC, RM_SECT*RM_TRAC, 0, NCYL(RM_CYL)  }
  98: #define RM05_INIT(c,u)  \
  99:     { &xp_controller[c], RM05, u, &rm5_sizes, \
 100:     RM5_SECT, RM5_TRAC, RM5_SECT*RM5_TRAC, 0, NCYL(RM5_CYL)  }
 101: #define RM05X_INIT(c,u) \
 102:     { &xp_controller[c], RM05X, u, &rm5_sizes, \
 103:     RM5_SECT, RM5_TRAC, RM5_SECT*RM5_TRAC, 0, NCYL(RM5X_CYL)  }
 104: #define RP06_INIT(c,u)  \
 105:     { &xp_controller[c], RP, u, &hp_sizes, \
 106:     HP_SECT, HP_TRAC, HP_SECT*HP_TRAC, 0, NCYL(RP06_CYL)  }
 107: #define RP05_INIT(c,u)  RP06_INIT(c,u)
 108: #define RP04_INIT(c,u)  \
 109:     { &xp_controller[c], RP, u, &hp_sizes, \
 110:     HP_SECT, HP_TRAC, HP_SECT*HP_TRAC, 0, NCYL(RP04_CYL)  }
 111: #define SI_INIT(c,u)    \
 112:     { &xp_controller[c], RM05, u, &si_sizes, \
 113:     SI_SECT, SI_TRAC, SI_SECT*SI_TRAC, 0, NCYL(SI_CYL)  }
 114: #define DV_INIT(c,u)    \
 115:     { &xp_controller[c], DV, u, &dv_sizes, \
 116:     DV_SECT, DV_TRAC, DV_SECT*DV_TRAC, 0, NCYL(DV_CYL)  }
 117: #endif	NXP
 118: 
 119: /*
 120:  *	Controller registers and bits
 121:  */
 122: struct hpdevice
 123: {
 124:     union   {
 125:         int w;
 126:         char    c[2];
 127:     }   hpcs1;      /* control and status 1 register */
 128:     short   hpwc;       /* word count register */
 129:     caddr_t hpba;       /* UNIBUS address register */
 130:     short   hpda;       /* desired address register */
 131:     union   {
 132:         int w;
 133:         char    c[2];
 134:     }   hpcs2;      /* control and status 2 register */
 135:     short   hpds;       /* drive status register */
 136:     short   hper1;      /* error register 1 */
 137:     short   hpas;       /* attention summary register */
 138:     short   hpla;       /* look ahead register */
 139:     short   hpdb;       /* data buffer register */
 140:     short   hpmr;       /* maintenance register (1) */
 141:     short   hpdt;       /* drive type register */
 142:     short   hpsn;       /* serial number register */
 143:     short   hpof;       /* offset register */
 144:     short   hpdc;       /* desired cylinder address register */
 145:     short   hpcc;       /* HP: current cylinder register */
 146: #define rmhr    hpcc;       /* RM: holding register */
 147:     short   hper2;      /* HP: error register 2 */
 148: #define rmmr2   hper2       /* RM: maintenance register 2 */
 149:     short   hper3;      /* HP: error register 3 */
 150: #define rmer2   hper3       /* RM: error register 2 */
 151:     short   hpec1;      /* burst error bit position */
 152:     short   hpec2;      /* burst error bit pattern */
 153:     short   hpbae;      /* bus address extension register (RH70 only) */
 154:     short   hpcs3;      /* control and status 3 register (RH70 only) */
 155: };
 156: 
 157: /* Other bits of hpcs1 */
 158: #define HP_SC       0100000     /* special condition */
 159: #define HP_TRE      0040000     /* transfer error */
 160: #define HP_MCPE     0020000     /* MASSBUS control bus read parity error */
 161: /* bit 12 is unused */
 162: #define HP_DVA      0004000     /* drive available */
 163: /* bits 9 and 8 are the extended address bits */
 164: #define HP_RDY      0000200     /* controller ready */
 165: #define HP_IE       0000100     /* interrupt enable */
 166: /* bits 5-1 are the command */
 167: #define HP_GO       0000001
 168: #define HP_BITS     \
 169: "\10\20SC\17TRE\16MCPE\14DVA\10RDY\7IE\1GO"
 170: 
 171: /* commands */
 172: #define HP_NOP      000
 173: #define HP_SEEK     004     /* seek */
 174: #define HP_RECAL    006     /* recalibrate */
 175: #define HP_DCLR     010     /* drive clear */
 176: #define HP_RELEASE  012     /* release */
 177: #define HP_OFFSET   014     /* offset */
 178: #define HP_RTC      016     /* return to center-line */
 179: #define HP_PRESET   020     /* read-in preset */
 180: #define HP_PACK     022     /* pack acknowledge */
 181: #define HP_SEARCH   030     /* search */
 182: #define HP_WCDATA   050     /* write check data */
 183: #define HP_WCHDR    052     /* write check header and data */
 184: #define HP_WCOM     060     /* write */
 185: #define HP_WHDR     062     /* write header and data */
 186: #define HP_RCOM     070     /* read data */
 187: #define HP_RHDR     072     /* read header and data */
 188: /* The following two are optionally enabled on some non-DEC controllers */
 189: #define HP_BOOT     074     /* boot */
 190: #define HP_FORMAT   076     /* format */
 191: 
 192: /* hpcs2 */
 193: #define HPCS2_DLT   0100000     /* data late */
 194: #define HPCS2_WCE   0040000     /* write check error */
 195: #define HPCS2_UPE   0020000     /* UNIBUS parity error */
 196: #define HPCS2_NED   0010000     /* nonexistent drive */
 197: #define HPCS2_NEM   0004000     /* nonexistent memory */
 198: #define HPCS2_PGE   0002000     /* programming error */
 199: #define HPCS2_MXF   0001000     /* missed transfer */
 200: #define HPCS2_MDPE  0000400     /* MASSBUS data read parity error */
 201: #define HPCS2_OR    0000200     /* output ready */
 202: #define HPCS2_IR    0000100     /* input ready */
 203: #define HPCS2_CLR   0000040     /* controller clear */
 204: #define HPCS2_PAT   0000020     /* parity test */
 205: #define HPCS2_BAI   0000010     /* address increment inhibit */
 206: /* bits 2-0 are drive select */
 207: 
 208: #define HPCS2_BITS \
 209: "\10\20DLT\17WCE\16UPE\15NED\14NEM\13PGE\12MXF\11MDPE\
 210: \10OR\7IR\6CLR\5PAT\4BAI"
 211: 
 212: /* hpds */
 213: #define HPDS_ATA    0100000     /* attention active */
 214: #define HPDS_ERR    0040000     /* composite drive error */
 215: #define HPDS_PIP    0020000     /* positioning in progress */
 216: #define HPDS_MOL    0010000     /* medium on line */
 217: #define HPDS_WRL    0004000     /* write locked */
 218: #define HPDS_LST    0002000     /* last sector transferred */
 219: #define HPDS_DAE    0001000     /* dual access enabled (programmable) */
 220: #define HPDS_DPR    0000400     /* drive present */
 221: #define HPDS_DRY    0000200     /* drive ready */
 222: #define HPDS_VV     0000100     /* volume valid */
 223: /* bits 5-1 are spare */
 224: #define HPDS_OM     0000001     /* offset mode */
 225: 
 226: #define HPDS_DREADY (HPDS_DPR|HPDS_DRY|HPDS_MOL|HPDS_VV)
 227: 
 228: #define HPDS_BITS \
 229: "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12DAE\11DPR\10DRY\7VV\1OM"
 230: 
 231: /* hper1 */
 232: #define HPER1_DCK   0100000     /* data check */
 233: #define HPER1_UNS   0040000     /* drive unsafe */
 234: #define HPER1_OPI   0020000     /* operation incomplete */
 235: #define HPER1_DTE   0010000     /* drive timing error */
 236: #define HPER1_WLE   0004000     /* write lock error */
 237: #define HPER1_IAE   0002000     /* invalid address error */
 238: #define HPER1_AOE   0001000     /* address overflow error */
 239: #define HPER1_HCRC  0000400     /* header crc error */
 240: #define HPER1_HCE   0000200     /* header compare error */
 241: #define HPER1_ECH   0000100     /* ecc hard error */
 242: #define HPER1_WCF   0000040     /* write clock fail (0) */
 243: #define HPER1_FER   0000020     /* format error */
 244: #define HPER1_PAR   0000010     /* parity error */
 245: #define HPER1_RMR   0000004     /* register modification refused */
 246: #define HPER1_ILR   0000002     /* illegal register */
 247: #define HPER1_ILF   0000001     /* illegal function */
 248: 
 249: #define HPER1_BITS \
 250: "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\
 251: \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF"
 252: 
 253: /* hpdt */
 254: #define HPDT_NBA    0100000     /* not block addressed; always 0 */
 255: #define HPDT_TAPE   0040000     /* tape drive; always 0 */
 256: #define HPDT_MH     0020000     /* moving head; always 1 */
 257: /* bit 12 is unused */
 258: #define HPDT_DRR    0004000     /* drive request required  */
 259: /* bits 10-9 are unused */
 260: /* bits 8-0 are drive type; the correct values are hard to determine */
 261: #define HPDT_RM05SP 0000047     /* single ported rm05 */
 262: #define HPDT_RM05DP 0000027     /* dual ported rm05 */
 263: #define HPDT_RM02   0000025     /* rm02, possibly rm03? */
 264: #define HPDT_RM03   0000024     /* rm03 */
 265: #define HPDT_RP06   0000022     /* rp06 */
 266: 
 267: /* hpof */
 268: #define HPOF_FMT22  0010000     /* 16 bit format */
 269: #define HPOF_ECI    0004000     /* ecc inhibit */
 270: #define HPOF_HCI    0002000     /* header compare inhibit */
 271: 
 272: /* THE SC21 ACTUALLY JUST IMPLEMENTS ADVANCE/RETARD... */
 273: #define HPOF_P400   0020        /*  +400 uinches */
 274: #define HPOF_M400   0220        /*  -400 uinches */
 275: #define HPOF_P800   0040        /*  +800 uinches */
 276: #define HPOF_M800   0240        /*  -800 uinches */
 277: #define HPOF_P1200  0060        /* +1200 uinches */
 278: #define HPOF_M1200  0260        /* -1200 uinches */
 279: 
 280: #define HPOF_BITS   \
 281: "\10\15FMT22\14ECI\13HCI\10OD"
 282: 
 283: /* rmer2: These are the bits for an RM error register 2 */
 284: #define RMER2_BSE   0100000     /* bad sector error */
 285: #define RMER2_SKI   0040000     /* seek incomplete */
 286: #define RMER2_DPE   0020000     /* drive plug error */
 287: #define RMER2_IVC   0010000     /* invalid command */
 288: #define RMER2_LSC   0004000     /* loss of system clock */
 289: #define RMER2_LBC   0002000     /* loss of bit clock */
 290: /* bits 9-8 are unused */
 291: #define RMER2_DVC   0000200     /* device check */
 292: /* bits 6-4 are unused */
 293: #define RMER2_MDPE  0000010     /* MASSBUS data read parity error */
 294: /* bits 2-0 are unused */
 295: 
 296: #define RMER2_BITS \
 297: "\10\20BSE\17SKI\16DPE\15IVC\14LSC\13LBC\10DVC\4MDPE"
 298: 
 299: /* hpcs3 */
 300: #define HPCS3_APE   0100000     /* address parity error */
 301: #define HPCS3_DPE   0060000     /* data parity error */
 302: #define HPCS3_WCE   0017000     /* write check error */
 303: #define HPCS3_DW    0002000     /* double word */
 304: /* bits 9-8 are unused */
 305: #define HPCS3_IE    0000100     /* interrupt enable */
 306: /* bits 5-4 are unused */
 307: /* bits 3-0 are inverted parity check */
 308: 
 309: #define HPCS3_BITS  \
 310: "\10\20APE\17DPE\15WCE\13DW\7IE"

Defined struct's

Defined macros

Usage of this include