1: struct hsdevice
2: {
3: short hscs1; /* Control and Status register 1 */
4: short hswc; /* Word count register */
5: caddr_t hsba; /* UNIBUS address register */
6: short hsda; /* Desired address register */
7: short hscs2; /* Control and Status register 2 */
8: short hsds; /* Drive Status */
9: short hser; /* Error register */
10: short hsas; /* Attention summary */
11: short hsla; /* Look ahead register used */
12: short hsdb; /* Data buffer register */
13: short hsmr; /* Maintenance register */
14: short hsdt; /* Drive type register */
15: short hsbae; /* Bus extension (11/70) */
16: };
17:
18: /* bits in hscs1 */
19: #define HS_SC 0100000 /* special condition */
20: #define HS_TRE 0040000 /* transfer error */
21: #define HS_MCPE 0020000 /* MASSBUS control bus parity error */
22: /* bit 12 is unused */
23: #define HS_DVA 0004000 /* drive available */
24: #define HS_PSEL 0002000 /* port select */
25: /* bits 9-8 are the UNIBUS extension bits */
26: #define HS_RDY 0000200 /* ready */
27: #define HS_IE 0000100 /* interrupt enable */
28: /* bits 5-1 are the function */
29: #define HS_GO 0000001 /* go */
30: #define HS_BITS \
31: "\10\20SC\17TRE\16MCPE\14DVA\13PSEL\10RDY\7IE\1GO"
32:
33: /* commands */
34: #define HS_NOOP 0000000 /* no operation */
35: #define HS_DCLR 0000010 /* drive clear */
36: #define HS_SEARCH 0000030 /* search */
37: #define HS_WCHK 0000050 /* write check */
38: #define HS_WCOM 0000060 /* write */
39: #define HS_RCOM 0000070 /* read */
40:
41: /* bits in hscs2 */
42: #define HSCS2_DLT 0100000 /* data late */
43: #define HSCS2_WCE 0040000 /* write check error */
44: #define HSCS2_PE 0020000 /* parity error */
45: #define HSCS2_NED 0010000 /* nonexistent drive */
46: #define HSCS2_NEM 0004000 /* nonexistent memory */
47: #define HSCS2_PGE 0002000 /* program error */
48: #define HSCS2_MXF 0001000 /* missed transfer */
49: #define HSCS2_MDPE 0000400 /* MASSBUS data bus parity error */
50: #define HSCS2_OR 0000200 /* output ready */
51: #define HSCS2_IR 0000100 /* input ready */
52: #define HSCS2_CLR 0000040 /* controller clear */
53: #define HSCS2_PAT 0000020 /* parity test */
54: #define HSCS2_BAI 0000010 /* UNIBUS address increment inhibit */
55: /* bits 2-0 are unit select */
56: #define HSCS2_BITS \
57: "\10\20DLT\17WCE\16PE\15NED\14NEM\13PGE\12MXF\11MDPE\10OR\7IR\6CLR\5PAT\4BAI"
58:
59: /* bits in hsds */
60: #define HSDS_ATA 0100000 /* attention active */
61: #define HSDS_ERR 0040000 /* error summary */
62: #define HSDS_PIP 0020000 /* positioning in progress */
63: #define HSDS_MOL 0010000 /* medium on line */
64: #define HSDS_WRL 0004000 /* write locked */
65: #define HSDS_LBT 0002000 /* last block transferred */
66: /* bit 9 is unused */
67: #define HSDS_DPR 0000400 /* drive present */
68: #define HSDS_DRY 0000200 /* drive ready */
69: /* bits 6-0 are unused */
70: #define HSDS_BITS \
71: "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LBT\11DPR\10DRY"
72:
73: /* bits in hser */
74: #define HSER_DCK 0100000 /* data check */
75: #define HSER_UNS 0040000 /* unsafe */
76: #define HSER_OPI 0020000 /* operation incomplete */
77: #define HSER_DTE 0010000 /* drive timing error */
78: #define HSER_WLE 0004000 /* write lock error */
79: #define HSER_IAE 0002000 /* invalid address error */
80: #define HSER_AO 0001000 /* address overflow */
81: /* bits 8-4 are unused */
82: #define HSER_PAR 0000010 /* bus parity error */
83: #define HSER_RMR 0000004 /* register modify refused */
84: #define HSER_ILR 0000002 /* illegal register */
85: #define HSER_ILF 0000001 /* illegal function */
86: #define HSER_BITS \
87: "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AO\4PAR\3RMR\2ILR\1ILF"
88:
89: /* bits in hsdt */
90: /* bits 15-9 always read as 0 */
91: #define HSDT_HS03 0000000 /* RS03 */
92: #define HSDT_HS03SI 0000001 /* RS03 with sector interleave */
93: #define HSDT_HS04 0000002 /* RS04 */
94: #define HSDT_HS04SI 0000003 /* RS04 with sector interleave */
Defined struct's
Defined macros
HS_GO
defined in line
29; used 3 times
HS_IE
defined in line
27; used 2 times
HS_SC
defined in line
19;
never used
Usage of this include