1: struct htdevice
2: {
3: short htcs1; /* control and status 1 register */
4: short htwc; /* word count register */
5: caddr_t htba; /* bus address register */
6: short htfc; /* frame counter */
7: short htcs2; /* control and status 2 register */
8: short htfs; /* formatter status register */
9: short hter; /* error register */
10: short htas; /* attention summary register */
11: short htcc; /* check character register */
12: short htdb; /* data buffer register */
13: short htmr; /* maintenance register */
14: short htdt; /* drive type register */
15: short htsn; /* serial number register */
16: short httc; /* tape control register */
17: short htbae; /* bus address extension register (RH70 only) */
18: short htcs3; /* control and status 3 register (RH70 only) */
19: };
20:
21: /* htcs1 */
22: #define HT_SC 0100000 /* special condition */
23: #define HT_TRE 0040000 /* transfer error */
24: #define HT_MCPE 0020000 /* MASSBUS control bus read parity error */
25: /* bit 12 is unused */
26: #define HT_DVA 0004000 /* drive available */
27: /* bit 10 is unused */
28: /* bits 9-8 are UNIBUS extension bits */
29: #define HT_RDY 0000200 /* ready */
30: #define HT_IE 0000100 /* interrupt enable */
31: #define HT_GO 0000001 /* go bit */
32: /* bits 5-1 are the command */
33: #define HTCS1_BITS \
34: "\10\20SC\17TRE\16MCPE\14DVA\12A17\11A16\10RDY\7IE\1GO"
35:
36: /* commands */
37: #define HT_SENSE 0000000 /* no operations (sense) */
38: #define HT_REWOFFL 0000002 /* rewind offline */
39: #define HT_REW 0000006 /* rewind */
40: #define HT_DCLR 0000010 /* drive clear */
41: #define HT_RIP 0000020 /* read in preset */
42: #define HT_ERASE 0000024 /* erase */
43: #define HT_WEOF 0000026 /* write tape mark */
44: #define HT_SFORW 0000030 /* space forward */
45: #define HT_SREV 0000032 /* space reverse */
46: #define HT_WCHFWD 0000050 /* write check forward */
47: #define HT_WCHREV 0000056 /* write check reverse */
48: #define HT_WCOM 0000060 /* write forward */
49: #define HT_RCOM 0000070 /* read forward */
50: #define HT_RREV 0000076 /* read reverse */
51:
52: /* htcs2 */
53: #define HTCS2_DLT 0100000 /* data late */
54: /*
55: * The 1981-1982 DEC peripherals handbook says bit 14 is unused.
56: * The 1980 one says it's WCE. Take your choice.
57: */
58: #define HTCS2_WCE 0040000 /* write check error */
59: #define HTCS2_UPE 0020000 /* UNIBUS parity error */
60: #define HTCS2_NEF 0010000 /* nonexistent formatter */
61: #define HTCS2_NEM 0004000 /* nonexistent memory */
62: #define HTCS2_PRE 0002000 /* program error */
63: #define HTCS2_MXF 0001000 /* missed transfer */
64: #define HTCS2_MDPE 0000400 /* MASSBUS data read parity error */
65: #define HTCS2_OR 0000200 /* output ready */
66: #define HTCS2_IR 0000100 /* input ready */
67: #define HTCS2_CLR 0000040 /* controller clear */
68: #define HTCS2_PAT 0000020 /* parity test */
69: #define HTCS2_MAII 0000010 /* memory address increment inhibit */
70: /* bits 2-0 select the formatter */
71: #define HTCS2_BITS \
72: "\10\20DLT\16UPE\16NEF\14NEM\13PRE\12MXF\11MDPE\10OR\7IR\6CLR\5PAT\4MAII"
73: #define HTCS2_ERR \
74: (HTCS2_MDPE|HTCS2_MXF|HTCS2_PRE|HTCS2_NEM|HTCS2_NEF|HTCS2_UPE|HTCS2_WCE)
75:
76: /* htfs */
77: #define HTFS_ATA 0100000 /* attention active */
78: #define HTFS_ERR 0040000 /* composite error */
79: #define HTFS_PIP 0020000 /* positioning in progress */
80: #define HTFS_MOL 0010000 /* medium on line */
81: #define HTFS_WRL 0004000 /* write lock */
82: #define HTFS_EOT 0002000 /* end of tape */
83: /* bit 9 is unused */
84: #define HTFS_DPR 0000400 /* drive present (always 1) */
85: #define HTFS_DRY 0000200 /* drive ready */
86: #define HTFS_SSC 0000100 /* slave status change */
87: #define HTFS_PES 0000040 /* phase-encoded status */
88: #define HTFS_SDWN 0000020 /* slowing down */
89: #define HTFS_IDB 0000010 /* identification burst */
90: #define HTFS_TM 0000004 /* tape mark */
91: #define HTFS_BOT 0000002 /* beginning of tape */
92: #define HTFS_SLA 0000001 /* slave attention */
93:
94: #define HTFS_BITS \
95: "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13EOT\11DPR\10DRY\
96: \7SSC\6PES\5SDWN\4IDB\3TM\2BOT\1SLA"
97:
98: /* hter */
99: #define HTER_CORCRC 0100000 /* correctible data/crc error */
100: #define HTER_UNS 0040000 /* unsafe */
101: #define HTER_OPI 0020000 /* operation incomplete */
102: #define HTER_CTE 0010000 /* controller timing error */
103: #define HTER_NEF 0004000 /* non-executable function */
104: #define HTER_CSITM 0002000 /* correctable skew/illegal tape mark */
105: #define HTER_FCE 0001000 /* frame count error */
106: #define HTER_NSG 0000400 /* non-standard gap */
107: #define HTER_PEFLRC 0000200 /* pe format error/lrc error */
108: #define HTER_INCVPE 0000100 /* incorrectable data/vertical parity error */
109: #define HTER_DPAR 0000040 /* MASSBUS data write parity error */
110: #define HTER_FMT 0000020 /* format select error */
111: #define HTER_CPAR 0000010 /* MASSBUS control bus write parity error */
112: #define HTER_RMR 0000004 /* register modification refused */
113: #define HTER_ILR 0000002 /* illegal register */
114: #define HTER_ILF 0000001 /* illegal function */
115:
116: #define HTER_BITS \
117: "\10\20CORCRC\17UNS\16OPI\15CTE\14NEF\13CSITM\12FCE\11NSG\10PEFLRC\
118: \7INCVPE\6DPAR\5FMT\4CPAR\3RMR\2ILR\1ILF"
119: #define HTER_HARD \
120: (HTER_UNS|HTER_OPI|HTER_NEF|HTER_DPAR|HTER_FMT|HTER_CPAR| \
121: HTER_RMR|HTER_ILR|HTER_ILF)
122:
123: /* htcc */
124: /* bits 15-9 are unused */
125: #define HTCC_DTPAR 0000400 /* dead track parity/crc parity */
126: /* bits 7-0 contain dead track/crc information */
127: #define HTCC_BITS \
128: "\10\11DTPAR"
129:
130: /* htmr */
131: /* bits 15-8 contain lrc/maintenance data */
132: #define HTMR_MDPB 0000400 /* maintenance data parity bit */
133: #define HTMR_TSC 0000200 /* tape speed clock */
134: #define HTMR_MC 0000100 /* maintenance clock */
135: /* bits 4-1 contain the maintenance operation code */
136: #define HTMR_MM 0000001 /* maintenance mode */
137: #define HTMR_BITS \
138: "\10\10MDPB\7TSC\6MC\1MM"
139:
140: /* htdt */
141: #define HTDT_NSA 0100000 /* not sector addressed; always 1 */
142: #define HTDT_TAP 0040000 /* tape; always 1 */
143: #define HTDT_MOH 0020000 /* moving head; always 0 */
144: #define HTDT_7CH 0010000 /* 7 channel; always 0 */
145: #define HTDT_DRQ 0004000 /* drive request required; always 0 */
146: #define HTDT_SPR 0002000 /* slave present */
147: /* bit 9 is unused */
148: /* bits 8-0 are formatter/transport type */
149: #define HTDT_BITS \
150: "\10\20NSA\17TAP\16MOH\15SCH\14DRQ\13SPR"
151:
152: /* httc */
153: #define HTTC_ACCL 0100000 /* transport is not up to speed */
154: #define HTTC_FCS 0040000 /* frame count status */
155: #define HTTC_SAC 0020000 /* slave address change */
156: #define HTTC_EAODTE 0010000 /* enable abort on data xfer errors */
157: /* bit 11 is unused */
158: /* bits 10-8 are density select */
159: #define HTTC_800BPI 0001400 /* in bits 10-8, dens=800 */
160: #define HTTC_1600BPI 0002000 /* in bits 10-8, dens=1600 */
161: /* bits 7-4 are format select */
162: #define HTTC_PDP11 0000300 /* in bits 7-4, pdp11 normal format */
163: #define HTTC_EVEN 0000010 /* select even parity */
164: /* bits 2-0 are slave select */
165:
166: #define HTTC_BITS \
167: "\10\20ACCL\17FCS\16SAC\15EAODTE\4EVEN"
168:
169: /* htcs3 */
170: #define HTCS3_APE 0100000 /* address parity error */
171: /* bits 14-11 are unused */
172: #define HTCS3_DW 0002000 /* double word */
173: /* bits 9-7 are unused */
174: #define HTCS3_IE 0000100 /* interrupt enable */
175: /* bits 5-4 are unused */
176: /* bits 3-0 are inverted parity check */
177: #define HTCS3_BITS \
178: "\10\20APE\13DW\7IE"
179:
180: #define b_repcnt b_bcount
181: #define b_command b_resid
Defined struct's
Defined macros
HT_GO
defined in line
31; used 8 times
HT_IE
defined in line
30; used 7 times
HT_SC
defined in line
22; used 1 times
Usage of this include