1: /* 2: * Copyright (c) 1982, 1986 Regents of the University of California. 3: * All rights reserved. The Berkeley software License Agreement 4: * specifies the terms and conditions for redistribution. 5: * 6: * @(#)cpudata.c 7.1 (Berkeley) 6/5/86 7: */ 8: 9: #include "pte.h" 10: 11: #include "param.h" 12: 13: #include "cpu.h" 14: #include "nexus.h" 15: #include "ioa.h" 16: #include "../vaxuba/ubareg.h" 17: 18: /* 19: * Initialization of per-cpu data structures. 20: */ 21: 22: /* 23: * These are the (fixed) addresses of the (last 8k bytes of) 24: * unibus memory for each of the possible unibus adapters. Note that the 25: * unibus memory addresses are actually indexed by the unibus adapter type code. 26: */ 27: #if VAX8600 28: caddr_t umaddr8600a[4] = { 29: (caddr_t) UMEMA8600(0), (caddr_t) UMEMA8600(1), 30: (caddr_t) UMEMA8600(2), (caddr_t) UMEMA8600(3), 31: }; 32: caddr_t umaddr8600b[4] = { 33: (caddr_t) UMEMB8600(0), (caddr_t) UMEMB8600(1), 34: (caddr_t) UMEMB8600(2), (caddr_t) UMEMB8600(3), 35: }; 36: #endif 37: #if VAX780 38: caddr_t umaddr780[4] = { 39: (caddr_t) UMEM780(0), (caddr_t) UMEM780(1), 40: (caddr_t) UMEM780(2), (caddr_t) UMEM780(3) 41: }; 42: #endif 43: #if VAX750 44: caddr_t umaddr750[2] = { 45: (caddr_t) UMEM750(0), (caddr_t) UMEM750(1), 46: }; 47: #endif 48: #if VAX730 49: caddr_t umaddr730[1] = { 50: (caddr_t) UMEM730 51: }; 52: #endif 53: #if VAX630 54: caddr_t umaddr630[1] = { 55: (caddr_t) UMEM630 56: }; 57: #endif 58: 59: /* 60: * Information to patch around the stupidity of configuration 61: * registers not returning types on some of the processors. 62: */ 63: #if VAX750 64: short nexty750[NNEX750] = { 65: NEX_MEM16, NEX_MEM16, NEX_MEM16, NEX_MEM16, 66: NEX_MBA, NEX_MBA, NEX_MBA, NEX_MBA, 67: NEX_UBA0, NEX_UBA1, NEX_ANY, NEX_ANY, 68: NEX_ANY, NEX_ANY, NEX_ANY, NEX_ANY 69: }; 70: #endif 71: #if VAX730 72: short nexty730[NNEX730] = { 73: NEX_MEM16, NEX_ANY, NEX_ANY, NEX_ANY, 74: NEX_ANY, NEX_ANY, NEX_ANY, NEX_ANY, 75: }; 76: #endif 77: 78: #if VAX8600 79: struct nexusconnect sbi8600[] = { 80: { NNEX8600, NEXA8600, umaddr8600a, NBDP8600, 1, 0 }, 81: { NNEX8600, NEXB8600, umaddr8600b, NBDP8600, 1, 0 }, 82: }; 83: struct iobus io8600[] = { 84: { IO_ABUS, IOA8600(0), IOAMAPSIZ, (caddr_t)&sbi8600[0] }, 85: { IO_ABUS, IOA8600(1), IOAMAPSIZ, (caddr_t)&sbi8600[1] }, 86: }; 87: #endif 88: #if VAX630 89: short nexty630[NNEX630] = { 90: NEX_UBA0, 91: }; 92: #endif 93: 94: #if VAX780 95: struct nexusconnect sbi780 = { 96: NNEX780, NEX780, umaddr780, NBDP780, 1, 0, 97: }; 98: struct iobus io780[] = { IO_SBI780, 0, 0, (caddr_t)&sbi780 }; 99: #endif 100: 101: #if VAX750 102: struct nexusconnect cmi750 = { 103: NNEX750, NEX750, umaddr750, NBDP750, 0, nexty750, 104: }; 105: struct iobus io750[] = { IO_CMI750, 0, 0, (caddr_t)&cmi750 }; 106: #endif 107: 108: #if VAX730 109: struct nexusconnect xxx730 = { 110: NNEX730, NEX730, umaddr730, NBDP730, 0, nexty730, 111: }; 112: struct iobus io730[] = { IO_XXX730, 0, 0, (caddr_t)&xxx730 }; 113: #endif 114: #if VAX630 115: struct nexusconnect xxx630 = { 116: NNEX630, NEX630, umaddr630, NBDP630, 0, nexty630, 117: }; 118: struct iobus io630[] = { IO_QBUS, 0, 0, (caddr_t)&xxx630 }; 119: #endif 120: 121: 122: struct percpu percpu[] = { 123: #if VAX8600 124: { VAX_8600, 6, 2, io8600 }, 125: #endif 126: #if VAX780 127: { VAX_780, 2, 1, io780 }, 128: #endif 129: #if VAX750 130: { VAX_750, 1, 1, io750 }, 131: #endif 132: #if VAX730 133: { VAX_730, 1, 1, io730 }, 134: #endif 135: #if VAX630 136: { VAX_630, 2, 1, io630 }, 137: #endif 138: 0, 139: };