4.3BSD - /usr/src/sys/vax/mem.h

   1: /*
   2:  * Copyright (c) 1982, 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)mem.h	7.1 (Berkeley) 6/5/86
   7:  */
   8: 
   9: /*
  10:  * Memory controller registers
  11:  *
  12:  * The way in which the data is stored in these registers varies
  13:  * per controller and cpu, so we define macros here to mask that.
  14:  */
  15: struct  mcr {
  16:     int mc_reg[6];
  17: };
  18: 
  19: /*
  20:  * Compute maximum possible number of memory controllers,
  21:  * for sizing of the mcraddr array.
  22:  */
  23: #if VAX780
  24: #define MAXNMCR     4
  25: #else
  26: #define MAXNMCR     1
  27: #endif
  28: 
  29: /*
  30:  * For each controller type we define 5 macros:
  31:  *	M???_INH(mcr)		inhibits further crd interrupts from mcr
  32:  *	M???_ENA(mcr)		enables another crd interrupt from mcr
  33:  *	M???_ERR(mcr)		tells whether an error is waiting
  34:  *	M???_SYN(mcr)		gives the syndrome bits of the error
  35:  *	M???_ADDR(mcr)		gives the address of the error
  36:  */
  37: 
  38: #if VAX8600
  39: /*
  40:  * 8600 register bit definitions
  41:  */
  42: #define M8600_ICRD  0x400       /* inhibit crd interrupts */
  43: #define M8600_TB_ERR    0xf00       /* translation buffer error mask */
  44: /*
  45:  * MDECC register
  46:  */
  47: #define M8600_ADDR_PE   0x080000    /* address parity error */
  48: #define M8600_DBL_ERR   0x100000    /* data double bit error */
  49: #define M8600_SNG_ERR   0x200000    /* data single bit error */
  50: #define M8600_BDT_ERR   0x400000    /* bad data error */
  51: 
  52: /*
  53:  * ESPA register is used to address scratch pad registers in the Ebox.
  54:  * To access a register in the scratch pad, write the ESPA with the address
  55:  * and then read the ESPD register.
  56:  *
  57:  * NOTE:  In assmebly code, the the mfpr instruction that reads the ESPD
  58:  *	  register must immedately follow the mtpr instruction that setup
  59:  *	  the ESPA register -- per the VENUS processor register spec.
  60:  *
  61:  * The scratchpad registers that are supplied for a single bit ECC
  62:  * error are:
  63:  */
  64: #define SPAD_MSTAT1 0x25        /* scratch pad mstat1 register	*/
  65: #define SPAD_MSTAT2 0x26        /* scratch pad mstat2 register	*/
  66: #define SPAD_MDECC  0x27        /* scratch pad mdecc register	*/
  67: #define SPAD_MEAR   0x2a        /* scratch pad mear register	*/
  68: 
  69: #define M8600_MEMERR(mdecc) ((mdecc) & 0x780000)
  70: #define M8600_HRDERR(mdecc) ((mdecc) & 0x580000)
  71: #define M8600_ENA (mtpr(MERG, (mfpr(MERG) & ~M8600_ICRD)))
  72: #define M8600_INH (mtpr(EHSR, 0), mtpr(MERG, (mfpr(MERG) | M8600_ICRD)))
  73: #define M8600_SYN(mdecc) (((mdecc) >> 9) & 0x3f)
  74: #define M8600_ADDR(mear) ((mear) & 0x3ffffffc)
  75: #define M8600_ARRAY(mear) (((mear) >> 22) & 0x0f)
  76: 
  77: #define M8600_MDECC_BITS "\20\27BAD_DT_ERR\26SNG_BIT_ERR\25DBL_BIT_ERR\
  78: \24ADDR_PE"
  79: #define M8600_MSTAT1_BITS "\20\30CPR_PE_A\27CPR_PE_B\26ABUS_DT_PE\
  80: \25ABUS_CTL_MSK_PE\24ABUS_ADR_PE\23ABUS_C/A_CYCLE\22ABUS_ADP_1\21ABUS_ADP_0\
  81: \20TB_MISS\17BLK_HIT\16C0_TAG_MISS\15CHE_MISS\14TB_VAL_ERR\13TB_PTE_B_PE\
  82: \12TB_PTE_A_PE\11TB_TAG_PE\10WR_DT_PE_B3\7WR_DT_PE_B2\6WR_DT_PE_B1\
  83: \5WR_DT_PE_B0\4CHE_RD_DT_PE\3CHE_SEL\2ANY_REFL\1CP_BW_CHE_DT_PE"
  84: #define M8600_MSTAT2_BITS "\20\20CP_BYT_WR\17ABUS_BD_DT_CODE\10MULT_ERR\
  85: \7CHE_TAG_PE\6CHE_TAG_W_PE\5CHE_WRTN_BIT\4NXM\3CP-IO_BUF_ERR\2MBOX_LOCK"
  86: #endif VAX8600
  87: 
  88: #if VAX780
  89: #define M780_ICRD   0x40000000  /* inhibit crd interrupts, in [2] */
  90: #define M780_HIER   0x20000000  /* high error rate, in reg[2] */
  91: #define M780_ERLOG  0x10000000  /* error log request, in reg[2] */
  92: /* on a 780, memory crd's occur only when bit 15 is set in the SBIER */
  93: /* register; bit 14 there is an error bit which we also clear */
  94: /* these bits are in the back of the ``red book'' (or in the VMS code) */
  95: 
  96: #define M780C_INH(mcr)  \
  97:     (((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0))
  98: #define M780C_ENA(mcr)  \
  99:     (((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14))
 100: #define M780C_ERR(mcr)  \
 101:     ((mcr)->mc_reg[2] & (M780_ERLOG))
 102: 
 103: #define M780C_SYN(mcr)  ((mcr)->mc_reg[2] & 0xff)
 104: #define M780C_ADDR(mcr) (((mcr)->mc_reg[2] >> 8) & 0xfffff)
 105: 
 106: #define M780EL_INH(mcr) \
 107:     (((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0))
 108: #define M780EL_ENA(mcr) \
 109:     (((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14))
 110: #define M780EL_ERR(mcr) \
 111:     ((mcr)->mc_reg[2] & (M780_ERLOG))
 112: 
 113: #define M780EL_SYN(mcr) ((mcr)->mc_reg[2] & 0x7f)
 114: #define M780EL_ADDR(mcr)    (((mcr)->mc_reg[2] >> 11) & 0x1ffff)
 115: 
 116: #define M780EU_INH(mcr) \
 117:     (((mcr)->mc_reg[3] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0))
 118: #define M780EU_ENA(mcr) \
 119:     (((mcr)->mc_reg[3] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14))
 120: #define M780EU_ERR(mcr) \
 121:     ((mcr)->mc_reg[3] & (M780_ERLOG))
 122: 
 123: #define M780EU_SYN(mcr) ((mcr)->mc_reg[3] & 0x7f)
 124: #define M780EU_ADDR(mcr)    (((mcr)->mc_reg[3] >> 11) & 0x1ffff)
 125: #endif
 126: 
 127: #if VAX750
 128: #define M750_ICRD   0x10000000  /* inhibit crd interrupts, in [1] */
 129: #define M750_UNCORR 0xc0000000  /* uncorrectable error, in [0] */
 130: #define M750_CORERR 0x20000000  /* correctable error, in [0] */
 131: 
 132: #define M750_INH(mcr)   ((mcr)->mc_reg[1] = 0)
 133: #define M750_ENA(mcr)   ((mcr)->mc_reg[0] = (M750_UNCORR|M750_CORERR), \
 134:                 (mcr)->mc_reg[1] = M750_ICRD)
 135: #define M750_ERR(mcr)   ((mcr)->mc_reg[0] & (M750_UNCORR|M750_CORERR))
 136: 
 137: #define M750_SYN(mcr)   ((mcr)->mc_reg[0] & 0x7f)
 138: #define M750_ADDR(mcr)  (((mcr)->mc_reg[0] >> 9) & 0x7fff)
 139: #endif
 140: 
 141: #if VAX730
 142: #define M730_UNCORR 0x80000000  /* rds, uncorrectable error, in [1] */
 143: #define M730_CRD    0x40000000  /* crd, in [1] */
 144: #define M730_FTBPE  0x20000000  /* force tbuf parity error, in [1] */
 145: #define M730_ENACRD 0x10000000  /* enable crd interrupt, in [1] */
 146: #define M730_MME    0x08000000  /* mem-man enable (ala ipr), in [1] */
 147: #define M730_DM     0x04000000  /* diagnostic mode, in [1] */
 148: #define M730_DISECC 0x02000000  /* disable ecc, in [1] */
 149: 
 150: #define M730_INH(mcr)   ((mcr)->mc_reg[1] = M730_MME)
 151: #define M730_ENA(mcr)   ((mcr)->mc_reg[1] = (M730_MME|M730_ENACRD))
 152: #define M730_ERR(mcr)   ((mcr)->mc_reg[1] & (M730_UNCORR|M730_CRD))
 153: #define M730_SYN(mcr)   ((mcr)->mc_reg[0] & 0x7f)
 154: #define M730_ADDR(mcr)  (((mcr)->mc_reg[0] >> 8) & 0x7fff)
 155: #endif
 156: 
 157: /* controller types */
 158: #define M780C   1
 159: #define M780EL  2
 160: #define M780EU  3
 161: #define M750    4
 162: #define M730    5
 163: 
 164: #define MEMINTVL    (60*10)     /* 10 minutes */
 165: 
 166: #ifdef  KERNEL
 167: int nmcr;
 168: struct  mcr *mcraddr[MAXNMCR];
 169: int mcrtype[MAXNMCR];
 170: #endif

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