if_accreg.h

Macros

ACC_ERR           X
ACC_GO            X
ACC_IE            X
ACC_INBITS        X
ACC_NXM           X
ACC_OUTBITS       X
ACC_RDY           X
ACC_RESET         X
IN_EOM            X
IN_HRDY           X
IN_IBF            X
IN_IMPBSY         X
IN_MRDY           X
IN_RMR            X
IN_WEN            X
OUT_BBACK         X
OUT_ENLB          X
OUT_TMR           X
iba               X
icsr              X
iwc               X
oba               X
ocsr              X
owc               X

struct's

accdevice         X
accdma            X

   1: /*
   2:  * Copyright (c) 1982, 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)if_accreg.h	7.1 (Berkeley) 6/5/86
   7:  */
   8: 
   9: /*
  10:  * ACC LH/DH-11 interface
  11:  */
  12: 
  13: struct accdma {
  14:     short   csr;    /* control and status */
  15:     short   db; /* data buffer */
  16:     u_short ba; /* buss address */
  17:     short   wc; /* word count */
  18: };
  19: 
  20: struct accdevice {
  21:     struct  accdma input;
  22:     struct  accdma output;
  23: };
  24: 
  25: #define icsr    input.csr
  26: #define iba input.ba
  27: #define iwc input.wc
  28: #define ocsr    output.csr
  29: #define oba output.ba
  30: #define owc output.wc
  31: 
  32: /*
  33:  * Bits Common to both input and out CSR's
  34:  */
  35: #define ACC_ERR     0x8000      /* error present */
  36: #define ACC_NXM     0x4000      /* non-existant memory */
  37: #define ACC_RDY     0x0080      /* ready */
  38: #define ACC_IE      0x0040      /* interrupt enable */
  39: #define ACC_RESET   0x0002      /* reset interface */
  40: #define ACC_GO      0x0001      /* start operation */
  41: 
  42: /*
  43:  * Input Control Status Register
  44:  */
  45: #define IN_EOM      0x2000      /* end-of-message recieved */
  46: #define IN_HRDY     0x0800      /* host ready */
  47: #define IN_IMPBSY   0x0400      /* IMP not ready */
  48: #define IN_RMR      0x0200      /* receive master ready error */
  49: #define IN_IBF      0x0100      /* input data buffer full */
  50: #define IN_WEN      0x0008      /* write enable */
  51: #define IN_MRDY     0x0004      /* master ready */
  52: 
  53: #define ACC_INBITS \
  54: "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\
  55: \4WEN\3MRDY\2RESET\1GO"
  56: 
  57: /*
  58:  * Output Control Status Register
  59:  */
  60: #define OUT_TMR     0x0200      /* transmit master ready error */
  61: #define OUT_BBACK   0x0008      /* bus back */
  62: #define OUT_ENLB    0x0004      /* enable last bit */
  63: 
  64: #define ACC_OUTBITS \
  65: "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO"