if_cssreg.h

Macros

CSS_ATTN          X
CSS_CLR           X
CSS_CYCLE         X
CSS_ERR           X
CSS_GO            X
CSS_IE            X
CSS_INBITS        X
CSS_MAINT         X
CSS_NXM           X
CSS_OUTBITS       X
CSS_RDY           X
CSS_XA            X
IN_EOM            X
IN_HRDY           X
IN_IMPNR          X
IN_RLE            X
IN_WEN            X
OUT_ENLB          X
OUT_TXEC          X
css_iba           X
css_icsr          X
css_iwc           X
css_oba           X
css_ocsr          X
css_owc           X

struct's

cssdevice         X
cssdma            X

   1: /*
   2:  * Copyright (c) 1982, 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)if_cssreg.h	7.1 (Berkeley) 6/5/86
   7:  */
   8: 
   9: /*
  10:  * DEC/CSS IMP11-A ARPAnet interface
  11:  */
  12: 
  13: struct cssdma {
  14:     short   wc;     /* word count */
  15:     u_short ba;     /* bus address (low 16 bits) */
  16:     short   csr;        /* status register */
  17:     short   db;     /* data buffer*/
  18: };
  19: 
  20: struct cssdevice {
  21:     struct  cssdma  css_output; /* transmit DR11-B */
  22:     struct  cssdma  css_hole;   /* unclever gap */
  23:     struct  cssdma  css_input;  /* receive DR11-B */
  24: };
  25: 
  26: #define css_icsr        css_input.csr
  27: #define css_iba         css_input.ba
  28: #define css_iwc         css_input.wc
  29: #define css_ocsr        css_output.csr
  30: #define css_oba         css_output.ba
  31: #define css_owc         css_output.wc
  32: 
  33: /*
  34:  * Bits Common to both input and out CSR's
  35:  */
  36: #define CSS_ERR         0x8000          /* error present */
  37: #define CSS_NXM         0x4000          /* non-existant memory */
  38: #define CSS_ATTN    0x2000      /* attention */
  39: #define CSS_MAINT   0x1000      /* maintenance mode */
  40: #define CSS_CYCLE   0x0100      /* force bus cycle */
  41: #define CSS_RDY         0x0080          /* ready */
  42: #define CSS_IE          0x0040          /* interrupt enable */
  43: #define CSS_XA      0x0030      /* extended address bits */
  44: #define CSS_CLR     0x0020      /* clear status (reset) */
  45: #define CSS_GO          0x0001          /* start operation */
  46: 
  47: /*
  48:  * Input Control Status Register
  49:  */
  50: #define IN_EOM          0x0800          /* end-of-message recieved */
  51: #define IN_IMPNR    0x0400          /* IMP not ready */
  52: #define IN_RLE          0x0200          /* ready line error */
  53: #define IN_WEN          0x0008          /* write enable */
  54: #define IN_HRDY         0x0004          /* host ready */
  55: 
  56: #define CSS_INBITS \
  57: "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO"
  58: 
  59: 
  60: /*
  61:  * Output Control Status Register
  62:  */
  63: #define OUT_TXEC    0x0008          /* tx error clear */
  64: #define OUT_ENLB    0x0004          /* enable last bit */
  65: 
  66: #define CSS_OUTBITS \
  67: "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO"