if_enreg.h

Macros

EN_BITS           X
EN_GO             X
EN_IEN            X
EN_IERROR         X
EN_OERROR         X
EN_OPDONE         X
EN_PROMISCUOUS    X
spl_enet          X

struct's

endevice          X

   1: /*
   2:  * Copyright (c) 1982, 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)if_enreg.h	7.1 (Berkeley) 6/5/86
   7:  */
   8: 
   9: /*
  10:  * Xerox experimental ethernet registers.
  11:  *
  12:  * N.B.: status register and device address are read/write,
  13:  * device address is read-only, rest are WRITE ONLY!
  14:  */
  15: struct endevice {
  16:     short   en_owc;     /* output word count (10 bits) */
  17:     short   en_oba;     /* output buffer address */
  18:     short   en_ostat;   /* output control and status */
  19:     short   en_odelay;  /* output start delay, 25usec units  */
  20:     short   en_iwc;     /* input word count */
  21:     short   en_iba;     /* input buffer address */
  22:     short   en_istat;   /* input csr */
  23:     short   en_addr;    /* ~device address (low 8 bits) */
  24: };
  25: 
  26: /*
  27:  * Control and status bits.
  28:  */
  29: #define EN_IERROR   0x8000      /* CRC error, buf ovflo or overrun */
  30: #define EN_OERROR   0x8000      /* collision or output underrun */
  31: #define EN_OPDONE   0x0080      /* previous operation completed */
  32: #define EN_IEN      0x0040      /* enable interrupt when DONE */
  33: #define EN_PROMISCUOUS  0x0002      /* promiscuous, input any packet */
  34: #define EN_GO       0x0001      /* start op bit */
  35: 
  36: #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO"
  37: 
  38: #define spl_enet()  spl5()