rlink_cext-I: connected to rlink_cext_fifo_rx rlink_cext-I: connected to rlink_cext_fifo_tx 543.3 ns 40: START ++ rreg (000,00017) a=fffe() d=ff02 s=00! OK -- rreg (010,00007) a=fffd() d=0201 s=00! OK -- rreg (020,00007) a=fffc() d=0700 s=00! OK -- rreg (030,00007) a=fffb() d=0000 s=00 OK -- rreg (040,00007) a=fffa() d=0000 s=00 OK -- rreg (050,00027) a=ffe8() d=0000 s=00 OK ++ rreg (060,00017) a=4ff8(i0.losize ) d=167777 s=00000000! OK -- rreg (070,00007) a=0040( ) d=000000 s=00000010 OK -- rreg (100,00007) a=0048( ) d=000020 s=00000000 OK -- rreg (110,00007) a=0050( ) d=000000 s=00000000 OK -- rreg (120,00007) a=0054( ) d=000000 s=00000000 OK -- rreg (130,00007) a=0058( ) d=000000 s=00000010 OK -- rreg (140,00007) a=005c( ) d=000000 s=00000010 OK -- rreg (150,00007) a=4000( ) d=000070 s=00000000 OK -- rreg (160,00007) a=4800( ) d=000014 s=00000000 OK -- rreg (170,00007) a=0060( ) d=000001 s=00000000 OK -- rreg (200,00007) a=4500( ) d=000000 s=00000000 OK -- rreg (210,00007) a=4fb3( ) d=000200 s=00000000 OK -- rreg (220,00007) a=4ab0( ) d=000000 s=00000000 OK -- rreg (230,00027) a=4fa0( ) d=000000 s=00000000 OK ++ wreg (002,00017) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (012,00027) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (022,00037) a=ffff(rl.cntl ) d=100000 s=00000000! OK ## steering file for all cpu tests ## steering file for all cp tests # test_cp_gr: test cp access to general registers --------------------- # write set 0 ++ wreg (032,00017) a=0003(c0.psw ) d=000000 s=00000000! OK -- wreg (042,00007) a=0008(c0.r0 ) d=000001 s=00000000! OK -- wreg (052,00007) a=0009(c0.r1 ) d=000101 s=00000000! OK -- wreg (062,00007) a=000a(c0.r2 ) d=000201 s=00000000! OK -- wreg (072,00007) a=000b(c0.r3 ) d=000301 s=00000000! OK -- wreg (102,00007) a=000c(c0.r4 ) d=000401 s=00000000! OK -- wreg (112,00027) a=000d(c0.r5 ) d=000501 s=00000000! OK # write set 1 ++ wreg (122,00017) a=0003(c0.psw ) d=004000 s=00000000! OK -- wreg (132,00007) a=0008(c0.r0 ) d=010001 s=00000000! OK -- wreg (142,00007) a=0009(c0.r1 ) d=010101 s=00000000! OK -- wreg (152,00007) a=000a(c0.r2 ) d=010201 s=00000000! OK -- wreg (162,00007) a=000b(c0.r3 ) d=010301 s=00000000! OK -- wreg (172,00007) a=000c(c0.r4 ) d=010401 s=00000000! OK -- wreg (202,00027) a=000d(c0.r5 ) d=010501 s=00000000! OK # write all sp and pc ++ wreg (212,00017) a=0003(c0.psw ) d=000000 s=00000000! OK -- wreg (222,00007) a=000e(c0.sp ) d=000601 s=00000000! OK -- wreg (232,00007) a=0003(c0.psw ) d=040000 s=00000000! OK -- wreg (242,00007) a=000e(c0.sp ) d=010601 s=00000000! OK -- wreg (252,00007) a=0003(c0.psw ) d=140000 s=00000000! OK -- wreg (262,00007) a=000e(c0.sp ) d=020601 s=00000000! OK -- wreg (272,00007) a=0003(c0.psw ) d=000000 s=00000000! OK -- wreg (302,00027) a=000f(c0.pc ) d=000701 s=00000000! OK # read set 0 ++ wreg (312,00017) a=0003(c0.psw ) d=000000 s=00000000! OK -- rreg (240,00007) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (250,00007) a=0009(c0.r1 ) d=000101! s=00000000! OK -- rreg (260,00007) a=000a(c0.r2 ) d=000201! s=00000000! OK -- rreg (270,00007) a=000b(c0.r3 ) d=000301! s=00000000! OK -- rreg (300,00007) a=000c(c0.r4 ) d=000401! s=00000000! OK -- rreg (310,00027) a=000d(c0.r5 ) d=000501! s=00000000! OK # read set 1 ++ wreg (322,00017) a=0003(c0.psw ) d=004000 s=00000000! OK -- rreg (320,00007) a=0008(c0.r0 ) d=010001! s=00000000! OK -- rreg (330,00007) a=0009(c0.r1 ) d=010101! s=00000000! OK -- rreg (340,00007) a=000a(c0.r2 ) d=010201! s=00000000! OK -- rreg (350,00007) a=000b(c0.r3 ) d=010301! s=00000000! OK -- rreg (360,00007) a=000c(c0.r4 ) d=010401! s=00000000! OK -- rreg (370,00027) a=000d(c0.r5 ) d=010501! s=00000000! OK # read all sp and pc ++ wreg (332,00017) a=0003(c0.psw ) d=000000 s=00000000! OK -- rreg (000,00007) a=000e(c0.sp ) d=000601! s=00000000! OK -- wreg (342,00007) a=0003(c0.psw ) d=040000 s=00000000! OK -- rreg (010,00007) a=000e(c0.sp ) d=010601! s=00000000! OK -- wreg (352,00007) a=0003(c0.psw ) d=140000 s=00000000! OK -- rreg (020,00007) a=000e(c0.sp ) d=020601! s=00000000! OK -- wreg (362,00007) a=0003(c0.psw ) d=000000 s=00000000! OK -- rreg (030,00027) a=000f(c0.pc ) d=000701! s=00000000! OK test_cp_gr.tcl: PASS # test_cp_psw: test psw access via all methods ------------------------ # write/read via cp ++ wreg (372,00017) a=0003(c0.psw ) d=000000 s=00000000! OK -- rreg (040,00027) a=0003(c0.psw ) d=000000! s=00000000! OK ++ wreg (002,00017) a=0003(c0.psw ) d=000017 s=00000000! OK -- rreg (050,00027) a=0003(c0.psw ) d=000017! s=00000000! OK # write/read via 16bit cp addressing ++ wreg (012,00037) a=0004(c0.al ) d=177776 s=00000000! OK ++ wreg (022,00017) a=0006(c0.mem ) d=000000 s=00000000! OK -- rreg (060,00007) a=0006(c0.mem ) d=000000! s=00000000! OK -- rreg (070,00027) a=0003(c0.psw ) d=000000! s=00000000! OK ++ wreg (032,00017) a=0006(c0.mem ) d=000017 s=00000000! OK -- rreg (100,00007) a=0006(c0.mem ) d=000017! s=00000000! OK -- rreg (110,00027) a=0003(c0.psw ) d=000017! s=00000000! OK # write/read via 22bit cp addressing ++ wreg (042,00017) a=0004(c0.al ) d=177776 s=00000000! OK -- wreg (052,00027) a=0005(c0.ah ) d=000177 s=00000000! OK ++ wreg (062,00017) a=0006(c0.mem ) d=000000 s=00000000! OK -- rreg (120,00007) a=0006(c0.mem ) d=000000! s=00000000! OK -- rreg (130,00027) a=0003(c0.psw ) d=000000! s=00000000! OK ++ wreg (072,00017) a=0006(c0.mem ) d=000017 s=00000000! OK -- rreg (140,00007) a=0006(c0.mem ) d=000017! s=00000000! OK -- rreg (150,00027) a=0003(c0.psw ) d=000017! s=00000000! OK # write/read via ibr window ++ wreg (102,00017) a=4fff(i0.psw ) d=000000 s=00000000! OK -- rreg (160,00007) a=4fff(i0.psw ) d=000000! s=00000000! OK -- rreg (170,00027) a=0003(c0.psw ) d=000000! s=00000000! OK ++ wreg (112,00017) a=4fff(i0.psw ) d=000017 s=00000000! OK -- rreg (200,00007) a=4fff(i0.psw ) d=000017! s=00000000! OK -- rreg (210,00027) a=0003(c0.psw ) d=000017! s=00000000! OK test_cp_psw.tcl: PASS # test_cp_membasics: Test very basic memory interface gymnastics ------ # A1: write/read address register --------------------------- ++ wreg (122,00017) a=0004(c0.al ) d=002000 s=00000000! OK -- rreg (220,00007) a=0004(c0.al ) d=002000! s=00000000! OK -- rreg (230,00027) a=0005(c0.ah ) d=000000! s=00000000! OK ++ wreg (132,00017) a=0004(c0.al ) d=003000 s=00000000! OK -- wreg (142,00007) a=0005(c0.ah ) d=000001 s=00000000! OK -- rreg (240,00007) a=0004(c0.al ) d=003000! s=00000000! OK -- rreg (250,00027) a=0005(c0.ah ) d=000001! s=00000000! OK # A2: write/read memory via wm/wmi/rm/rmi (16 bit mode) ----- ++ wreg (152,00017) a=0004(c0.al ) d=002000 s=00000000! OK -- wreg (162,00007) a=0006(c0.mem ) d=001100 s=00000000! OK -- rreg (260,00007) a=0004(c0.al ) d=002000! s=00000000! OK -- rreg (270,00007) a=0005(c0.ah ) d=000000! s=00000000! OK -- rreg (300,00027) a=0006(c0.mem ) d=001100! s=00000000! OK ++ wreg (172,00017) a=0004(c0.al ) d=002000 s=00000000! OK -- wreg (202,00007) a=0006(c0.mem ) d=002200 s=00000000! OK -- wreg (212,00007) a=0006(c0.mem ) d=002210 s=00000000! OK -- rreg (310,00007) a=0004(c0.al ) d=002000! s=00000000! OK -- rreg (320,00007) a=0005(c0.ah ) d=000000! s=00000000! OK -- rreg (330,00027) a=0006(c0.mem ) d=002210! s=00000000! OK ++ wreg (222,00017) a=0004(c0.al ) d=002100 s=00000000! OK -- wreg (232,00007) a=0007(c0.memi ) d=003300 s=00000000! OK -- wreg (242,00007) a=0007(c0.memi ) d=003310 s=00000000! OK -- wreg (252,00007) a=0007(c0.memi ) d=003320 s=00000000! OK -- rreg (340,00007) a=0004(c0.al ) d=002106! s=00000000! OK -- rreg (350,00027) a=0005(c0.ah ) d=000000! s=00000000! OK ++ wreg (262,00017) a=0004(c0.al ) d=002100 s=00000000! OK -- rreg (360,00007) a=0007(c0.memi ) d=003300! s=00000000! OK -- rreg (370,00007) a=0007(c0.memi ) d=003310! s=00000000! OK -- rreg (000,00007) a=0007(c0.memi ) d=003320! s=00000000! OK -- rreg (010,00007) a=0004(c0.al ) d=002106! s=00000000! OK -- rreg (020,00027) a=0005(c0.ah ) d=000000! s=00000000! OK # A3: write/read memory via bwm/brm (16 bit mode) ----------- ++ wreg (272,00017) a=0004(c0.al ) d=002200 s=00000000! OK -- wblk (003,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 007700 007710 007720 007730 ++ wreg (302,00017) a=0004(c0.al ) d=002200 s=00000000! OK -- rblk (001,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 007700! 007710! 007720! 007730! # A4: write/read memory - test membe (16 bit mode) ---------- ++ wreg (312,00017) a=0004(c0.al ) d=002300 s=00000000! OK -- wblk (013,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 125252 135673 146314 156735 -- wreg (322,00007) a=0004(c0.al ) d=002300 s=00000000! OK -- rblk (011,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 125252! 135673! 146314! 156735! ++ wreg (332,00017) a=0004(c0.al ) d=002300 s=00000000! OK -- wreg (342,00007) a=0010(c0.membe ) d=000000 s=00000000! OK -- rreg (030,00007) a=0010(c0.membe ) d=000000! s=00000000! OK -- wreg (352,00007) a=0007(c0.memi ) d=000000 s=00000000! OK -- rreg (040,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (362,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- rreg (050,00007) a=0010(c0.membe ) d=000001! s=00000000! OK -- wreg (372,00007) a=0007(c0.memi ) d=010421 s=00000000! OK -- rreg (060,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (002,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- rreg (070,00007) a=0010(c0.membe ) d=000002! s=00000000! OK -- wreg (012,00007) a=0007(c0.memi ) d=021042 s=00000000! OK -- rreg (100,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (022,00007) a=0010(c0.membe ) d=000003 s=00000000! OK -- rreg (110,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (032,00007) a=0007(c0.memi ) d=031463 s=00000000! OK -- rreg (120,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (042,00007) a=0004(c0.al ) d=002300 s=00000000! OK -- rblk (021,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 125252! 135421! 021314! 031463! ++ wreg (052,00017) a=0004(c0.al ) d=002300 s=00000000! OK -- wreg (062,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- rreg (130,00007) a=0010(c0.membe ) d=000001! s=00000000! OK -- wreg (072,00007) a=0007(c0.memi ) d=000000 s=00000000! OK -- rreg (140,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (102,00007) a=0007(c0.memi ) d=114631 s=00000000! OK -- rreg (150,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- wreg (112,00007) a=0004(c0.al ) d=002300 s=00000000! OK -- rblk (031,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 125000! 114631! 021314! 031463! ++ wreg (122,00017) a=0004(c0.al ) d=002300 s=00000000! OK -- wreg (132,00007) a=0010(c0.membe ) d=000006 s=00000000! OK -- rreg (160,00007) a=0010(c0.membe ) d=000006! s=00000000! OK -- wreg (142,00007) a=0007(c0.memi ) d=042104 s=00000000! OK -- wreg (152,00007) a=0007(c0.memi ) d=052525 s=00000000! OK -- wreg (162,00007) a=0007(c0.memi ) d=063146 s=00000000! OK -- wreg (172,00007) a=0007(c0.memi ) d=073567 s=00000000! OK -- rreg (170,00007) a=0010(c0.membe ) d=000006! s=00000000! OK -- wreg (202,00007) a=0004(c0.al ) d=002300 s=00000000! OK -- rblk (041,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 042000! 052631! 063314! 073463! -- wreg (212,00007) a=0010(c0.membe ) d=000003 s=00000000! OK -- rreg (200,00027) a=0010(c0.membe ) d=000003! s=00000000! OK # A5: write/read memory via bwm/brm (22 bit mode) ----------- ++ rreg (210,00037) a=4ff8(i0.losize ) d=167777 s=00000000! OK ++ wreg (222,00017) a=0004(c0.al ) d=177700 s=00000000! OK -- wreg (232,00007) a=0005(c0.ah ) d=000172 s=00000000! OK -- wblk (023,00027) a=0007(c0.memi ) n= 32= 32 s=00000000! OK 0: 123000 123001 123002 123003 123004 123005 123006 123007 8: 123010 123011 123012 123013 123014 123015 123016 123017 16: 123020 123021 123022 123023 123024 123025 123026 123027 24: 123030 123031 123032 123033 123034 123035 123036 123037 ++ wreg (242,00017) a=0004(c0.al ) d=177700 s=00000000! OK -- wreg (252,00007) a=0005(c0.ah ) d=000172 s=00000000! OK -- rblk (051,00027) a=0007(c0.memi ) n= 32= 32 s=00000000! OK 0: 123000! 123001! 123002! 123003! 123004! 123005! 123006! 123007! 8: 123010! 123011! 123012! 123013! 123014! 123015! 123016! 123017! 16: 123020! 123021! 123022! 123023! 123024! 123025! 123026! 123027! 24: 123030! 123031! 123032! 123033! 123034! 123035! 123036! 123037! test_cp_membasics.tcl: PASS # test_cp_ibrbasics: Test very basic ibus interface gymnastics -------- # write/read ibus space (MMU PAR SM I regs) via bwm/brm ++ wreg (262,00017) a=0004(c0.al ) d=172240 s=00000000! OK -- wblk (033,00027) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 012340 012342 012344 ++ wreg (272,00017) a=0004(c0.al ) d=172240 s=00000000! OK -- rblk (061,00027) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 012340! 012342! 012344! # write/read ibus space (MMU PAR SM I regs) via wibr/ribr ++ rreg (220,00017) a=4a50(i0.parsi.0 ) d=012340! s=00000000! OK -- rreg (230,00007) a=4a51(i0.parsi.1 ) d=012342! s=00000000! OK -- rreg (240,00027) a=4a52(i0.parsi.2 ) d=012344! s=00000000! OK ++ wreg (302,00017) a=4a50(i0.parsi.0 ) d=022340 s=00000000! OK -- wreg (312,00007) a=4a51(i0.parsi.1 ) d=022342 s=00000000! OK -- wreg (322,00027) a=4a52(i0.parsi.2 ) d=022344 s=00000000! OK ++ rreg (250,00017) a=4a50(i0.parsi.0 ) d=022340! s=00000000! OK -- rreg (260,00007) a=4a51(i0.parsi.1 ) d=022342! s=00000000! OK -- rreg (270,00027) a=4a52(i0.parsi.2 ) d=022344! s=00000000! OK # membe with wibr (non sticky) ++ wreg (332,00017) a=4a50(i0.parsi.0 ) d=000400 s=00000000! OK -- wreg (342,00007) a=4a51(i0.parsi.1 ) d=001402 s=00000000! OK -- wreg (352,00027) a=4a52(i0.parsi.2 ) d=002404 s=00000000! OK # membe = 0 (no byte selected) ++ wreg (362,00017) a=0010(c0.membe ) d=000000 s=00000000! OK -- wreg (372,00007) a=4a51(i0.parsi.1 ) d=177777 s=00000000! OK -- rreg (300,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- rreg (310,00027) a=4a51(i0.parsi.1 ) d=001402! s=00000000! OK # membe = 1 (lsb selected) ++ wreg (002,00017) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (012,00007) a=4a51(i0.parsi.1 ) d=177652 s=00000000! OK -- rreg (320,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- rreg (330,00027) a=4a51(i0.parsi.1 ) d=001652! s=00000000! OK # membe = 2 (msb selected) ++ wreg (022,00017) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (032,00007) a=4a51(i0.parsi.1 ) d=135777 s=00000000! OK -- rreg (340,00007) a=0010(c0.membe ) d=000003! s=00000000! OK -- rreg (350,00027) a=4a51(i0.parsi.1 ) d=135652! s=00000000! OK ++ rreg (360,00017) a=4a50(i0.parsi.0 ) d=000400! s=00000000! OK -- rreg (370,00007) a=4a51(i0.parsi.1 ) d=135652! s=00000000! OK -- rreg (000,00027) a=4a52(i0.parsi.2 ) d=002404! s=00000000! OK # membe with wibr (sticky) ++ wreg (042,00017) a=4a50(i0.parsi.0 ) d=010420 s=00000000! OK -- wreg (052,00007) a=4a51(i0.parsi.1 ) d=011422 s=00000000! OK -- wreg (062,00027) a=4a52(i0.parsi.2 ) d=012424 s=00000000! OK # membe = 0 + stick (no byte selected) ++ wreg (072,00017) a=0010(c0.membe ) d=000004 s=00000000! OK -- wreg (102,00007) a=4a51(i0.parsi.1 ) d=177777 s=00000000! OK -- rreg (010,00007) a=0010(c0.membe ) d=000004! s=00000000! OK -- rreg (020,00027) a=4a51(i0.parsi.1 ) d=011422! s=00000000! OK # membe = 1 + stick (lsb selected) ++ wreg (112,00017) a=0010(c0.membe ) d=000005 s=00000000! OK -- wreg (122,00007) a=4a50(i0.parsi.0 ) d=177652 s=00000000! OK -- rreg (030,00007) a=0010(c0.membe ) d=000005! s=00000000! OK -- wreg (132,00007) a=4a51(i0.parsi.1 ) d=177673 s=00000000! OK -- rreg (040,00007) a=0010(c0.membe ) d=000005! s=00000000! OK -- wreg (142,00007) a=4a52(i0.parsi.2 ) d=177714 s=00000000! OK -- rreg (050,00027) a=0010(c0.membe ) d=000005! s=00000000! OK ++ rreg (060,00017) a=4a50(i0.parsi.0 ) d=010652! s=00000000! OK -- rreg (070,00007) a=4a51(i0.parsi.1 ) d=011673! s=00000000! OK -- rreg (100,00027) a=4a52(i0.parsi.2 ) d=012714! s=00000000! OK # membe = 2 + stick (msb selected) ++ wreg (152,00017) a=0010(c0.membe ) d=000006 s=00000000! OK -- wreg (162,00007) a=4a50(i0.parsi.0 ) d=146377 s=00000000! OK -- rreg (110,00007) a=0010(c0.membe ) d=000006! s=00000000! OK -- wreg (172,00007) a=4a51(i0.parsi.1 ) d=135777 s=00000000! OK -- rreg (120,00007) a=0010(c0.membe ) d=000006! s=00000000! OK -- wreg (202,00007) a=4a52(i0.parsi.2 ) d=125377 s=00000000! OK -- rreg (130,00027) a=0010(c0.membe ) d=000006! s=00000000! OK ++ rreg (140,00017) a=4a50(i0.parsi.0 ) d=146252! s=00000000! OK -- rreg (150,00007) a=4a51(i0.parsi.1 ) d=135673! s=00000000! OK -- rreg (160,00027) a=4a52(i0.parsi.2 ) d=125314! s=00000000! OK # membe = 3 again ++ wreg (212,00017) a=0010(c0.membe ) d=000003 s=00000000! OK -- rreg (170,00027) a=0010(c0.membe ) d=000003! s=00000000! OK test_cp_ibrbasics.tcl: PASS # test_cp_ubmap: Test ubmap and memory access via ubmap ------------ # A1: write/read ubmap registers ---------------------------- # write ubmap registers ++ wreg (222,00017) a=0004(c0.al ) d=170200 s=00000000! OK -- wblk (043,00027) a=0007(c0.memi ) n= 62= 62 s=00000000! OK 0: 110000 000040 110010 000041 110020 000042 110030 000043 8: 110040 000044 110050 000045 110060 000046 110070 000047 16: 110100 000050 110110 000051 110120 000052 110130 000053 24: 110140 000054 110150 000055 110160 000056 110170 000057 32: 110200 000060 110210 000061 110220 000062 110230 000063 40: 110240 000064 110250 000065 110260 000066 110270 000067 48: 110300 000070 110310 000071 110320 000072 110330 000073 56: 110340 000074 110350 000075 110360 000076 # read and check ubmap registers ++ wreg (232,00017) a=0004(c0.al ) d=170200 s=00000000! OK -- rblk (071,00027) a=0007(c0.memi ) n= 62= 62 s=00000000! OK 0: 110000! 000040! 110010! 000041! 110020! 000042! 110030! 000043! 8: 110040! 000044! 110050! 000045! 110060! 000046! 110070! 000047! 16: 110100! 000050! 110110! 000051! 110120! 000052! 110130! 000053! 24: 110140! 000054! 110150! 000055! 110160! 000056! 110170! 000057! 32: 110200! 000060! 110210! 000061! 110220! 000062! 110230! 000063! 40: 110240! 000064! 110250! 000065! 110260! 000066! 110270! 000067! 48: 110300! 000070! 110310! 000071! 110320! 000072! 110330! 000073! 56: 110340! 000074! 110350! 000075! 110360! 000076! # A2: write/read memory via ubmap --------------------------- # bwm via ubmap with mmr3 ubmap disabled ++ wreg (242,00017) a=0004(c0.al ) d=170200 s=00000000! OK -- wblk (053,00027) a=0007(c0.memi ) n= 2= 2 s=00000000! OK 0: 003000 000000 ++ wreg (252,00017) a=0004(c0.al ) d=001400 s=00000000! OK -- wreg (262,00007) a=0005(c0.ah ) d=000200 s=00000000! OK -- wblk (063,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000111 000222 000333 000444 # check via direct read ++ wreg (272,00017) a=0004(c0.al ) d=001400 s=00000000! OK -- rblk (101,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000111! 000222! 000333! 000444! # bwm via ubmap with mmr3 ubmap enabled ++ wreg (302,00037) a=4aa7(i0.mmr3 ) d=000040 s=00000000! OK ++ wreg (312,00017) a=0004(c0.al ) d=001400 s=00000000! OK -- wreg (322,00007) a=0005(c0.ah ) d=000200 s=00000000! OK -- wblk (073,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 010111 010222 010333 010444 # check via direct read ++ wreg (332,00017) a=0004(c0.al ) d=001400 s=00000000! OK -- rblk (111,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000111! 000222! 000333! 000444! -- wreg (342,00007) a=0004(c0.al ) d=004400 s=00000000! OK -- rblk (121,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 010111! 010222! 010333! 010444! # read via ubmap ++ wreg (352,00017) a=0004(c0.al ) d=001400 s=00000000! OK -- wreg (362,00007) a=0005(c0.ah ) d=000200 s=00000000! OK -- rblk (131,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 010111! 010222! 010333! 010444! # A3: write/read memory via ubmap over page border ---------- ++ wreg (372,00017) a=0004(c0.al ) d=170200 s=00000000! OK -- wblk (103,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 004000 000000 005000 000000 ++ wreg (002,00017) a=0004(c0.al ) d=023774 s=00000000! OK -- wblk (113,00007) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 000000 000000 000000 -- wreg (012,00007) a=0004(c0.al ) d=025000 s=00000000! OK -- wblk (123,00027) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 000000 000000 000000 # bwm via ubmap with mmr3 ubmap enabled ++ wreg (022,00017) a=0004(c0.al ) d=017774 s=00000000! OK -- wreg (032,00007) a=0005(c0.ah ) d=000200 s=00000000! OK -- wblk (133,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 030111 030222 030333 030444 # check via direct read ++ wreg (042,00017) a=0004(c0.al ) d=023774 s=00000000! OK -- rblk (141,00007) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 030111! 030222! 000000! -- wreg (052,00007) a=0004(c0.al ) d=005000 s=00000000! OK -- rblk (151,00027) a=0007(c0.memi ) n= 3= 3 s=00000000! OK 0: 030333! 030444! 000000! # read via ubmap ++ wreg (062,00017) a=0004(c0.al ) d=017774 s=00000000! OK -- wreg (072,00007) a=0005(c0.ah ) d=000200 s=00000000! OK -- rblk (161,00027) a=0007(c0.memi ) n= 5= 5 s=00000000! OK 0: 030111! 030222! 030333! 030444! 000000! test_cp_ubmap.tcl: PASS # test_cp_cpubasics: Test very basic cpu interface gymnastics --------- # A1: start/stop/step basics -------------------------------- # load simple linear code via lsasm ++ wreg (102,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (143,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 005202 005202 005202 000000 # read back and check ++ wreg (112,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- rblk (171,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 005202! 005202! 005202! 000000! # execute via -start ++ wreg (122,00017) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (142,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -+- 2023-01-11 -+- -I- 16:35:31.344624 : ATTN notify apat = 0001 lams = 0 ++ attn (005,00037) d=000001 s=00000000! OK -- wtcpu to=1.000 T=0.009 OK ++ rreg (200,00017) a=000a(c0.r2 ) d=000003! s=00000000! OK -- rreg (210,00027) a=000f(c0.pc ) d=001010! s=00000000! OK # execute via -stapc ++ wreg (152,00017) a=000a(c0.r2 ) d=000100 s=00000000! OK -- wreg (162,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (172,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (202,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (212,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:31.469997 : ATTN notify apat = 0001 lams = 0 dt=0.125365 ++ attn (015,00037) d=000001 s=00000000! OK -- wtcpu to=1.000 T=0.010 OK ++ rreg (220,00017) a=000a(c0.r2 ) d=000103! s=00000000! OK -- rreg (230,00027) a=000f(c0.pc ) d=001010! s=00000000! OK # execute via -step ++ wreg (222,00017) a=000a(c0.r2 ) d=000300 s=00000000! OK -- wreg (232,00027) a=000f(c0.pc ) d=001000 s=00000000! OK ++ wreg (242,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (240,00007) a=000f(c0.pc ) d=001002! s=00000000! OK -- rreg (250,00007) a=000a(c0.r2 ) d=000301! s=00000000! OK -- rreg (260,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (252,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (270,00007) a=000f(c0.pc ) d=001004! s=00000000! OK -- rreg (300,00007) a=000a(c0.r2 ) d=000302! s=00000000! OK -- rreg (310,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (262,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (320,00007) a=000f(c0.pc ) d=001006! s=00000000! OK -- rreg (330,00007) a=000a(c0.r2 ) d=000303! s=00000000! OK -- rreg (340,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (272,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (350,00007) a=000f(c0.pc ) d=001010! s=00000000! OK -- rreg (360,00007) a=000a(c0.r2 ) d=000303! s=00000000! OK -- rreg (370,00027) a=0002(c0.stat ) d=000020! s=00000000! OK # A2: suspend/resume basics; cpugo,cpususp flags ------------ # load simple loop code via lsasm ++ wreg (302,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (153,00027) a=0007(c0.memi ) n= 2= 2 s=00000000! OK 0: 005202 000776 # execute via -stapc, check cpugo and that r2 increments ++ wreg (312,00017) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (342,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000001 s=00010000! OK -- rreg (000,00007) a=000a(c0.r2 ) d=000006 s=00010000| OK -- rreg (010,00027) a=000a(c0.r2 ) d=000013 s=00010000| OK .. r2 increment 6 .. r2 increment 5 # suspend, check cpususp=1 and that r2 doesn't increment ++ wreg (362,00017) a=0001(c0.cntl ) d=000006 s=00111000! OK -- wreg (372,00007) a=000a(c0.r2 ) d=000000 s=00111000! OK -- rreg (020,00007) a=000a(c0.r2 ) d=000000! s=00111000| OK -- rreg (030,00027) a=000a(c0.r2 ) d=000000! s=00111000| OK # resume, check cpususp=0 and that r2 increments again -I- 16:35:32.125931 : ATTN notify apat = 0001 lams = 0 dt=0.655935 ++ wreg (002,00017) a=0001(c0.cntl ) d=000007 s=00111000! OK -- rreg (040,00007) a=000a(c0.r2 ) d=000005 s=00011000| OK -- rreg (050,00027) a=000a(c0.r2 ) d=000013 s=00011000| OK .. r2 increment 5 .. r2 increment 6 # suspend then step, two steps should inc r2 once ++ wreg (012,00017) a=0001(c0.cntl ) d=000006 s=00111000! OK -- wreg (022,00007) a=000a(c0.r2 ) d=000000 s=00111000! OK -- wreg (032,00007) a=0001(c0.cntl ) d=000003 s=00111000! OK -- wreg (042,00007) a=0001(c0.cntl ) d=000003 s=00111000! OK -- rreg (060,00007) a=000a(c0.r2 ) d=000001! s=00111000! OK -- wreg (052,00007) a=0001(c0.cntl ) d=000003 s=00111000! OK -- wreg (062,00007) a=0001(c0.cntl ) d=000003 s=00111000! OK -- rreg (070,00027) a=000a(c0.r2 ) d=000002! s=00111000! OK # stop while suspended, check cpugo=0,cpususp=1,attn=1; harvest attn ++ wreg (072,00037) a=0001(c0.cntl ) d=000002 s=00101000| OK ++ attn (025,00037) d=000001 s=00100000! OK -- wtcpu to=1.000 T=0.000 OK # creset, check cpususp=0 ++ wreg (102,00017) a=0001(c0.cntl ) d=000004 s=00100000! OK -- rreg (100,00027) a=000a(c0.r2 ) d=000002 s=00000000| OK # A3: check that creset clears PSW,STKLIM,MMR0,MMR3 --------- # write ps,stklim,mmr0,mmr3 and read back ++ wreg (112,00017) a=0003(c0.psw ) d=004340 s=00000000! OK -- wreg (122,00007) a=4ffe(i0.stklim ) d=000400 s=00000000! OK -- wreg (132,00007) a=4fbd(i0.mmr0 ) d=171001 s=00000000! OK -- wreg (142,00007) a=4aa7(i0.mmr3 ) d=000067 s=00000000! OK -- rreg (110,00007) a=0003(c0.psw ) d=004340! s=00000000! OK -- rreg (120,00007) a=4ffe(i0.stklim ) d=000400! s=00000000! OK -- rreg (130,00007) a=4fbd(i0.mmr0 ) d=171001! s=00000000! OK -- rreg (140,00027) a=4aa7(i0.mmr3 ) d=000067! s=00000000! OK # creset and check that ps,stklim,mmr0,mmr3 cleared ++ wreg (152,00017) a=0001(c0.cntl ) d=000004 s=00000000! OK -- rreg (150,00007) a=0003(c0.psw ) d=000000! s=00000000! OK -- rreg (160,00007) a=4ffe(i0.stklim ) d=000000! s=00000000! OK -- rreg (170,00007) a=4fbd(i0.mmr0 ) d=000000! s=00000000! OK -- rreg (200,00027) a=4aa7(i0.mmr3 ) d=000000! s=00000000! OK test_cp_cpubasics.tcl: PASS @cp/cp_all.dat: PASS ## steering file for all w11a_ibtst tests # test_ibtst_regs: test cntl/stat register access ---------------------- # A1: write/read cntl--------------------------------- ++ wreg (162,00017) a=4800(i0.it.cntl ) d=000001 s=00000000! OK -- rreg (210,00007) a=4800(i0.it.cntl ) d=000001! s=00000000! OK -- wreg (172,00007) a=4800(i0.it.cntl ) d=000002 s=00000000! OK -- rreg (220,00007) a=4800(i0.it.cntl ) d=000002! s=00000000! OK -- wreg (202,00007) a=4800(i0.it.cntl ) d=000004 s=00000000! OK -- rreg (230,00007) a=4800(i0.it.cntl ) d=000004! s=00000000! OK -- wreg (212,00007) a=4800(i0.it.cntl ) d=000010 s=00000000! OK -- rreg (240,00007) a=4800(i0.it.cntl ) d=000010! s=00000000! OK -- wreg (222,00007) a=4800(i0.it.cntl ) d=000020 s=00000000! OK -- rreg (250,00007) a=4800(i0.it.cntl ) d=000020! s=00000000! OK -- wreg (232,00007) a=4800(i0.it.cntl ) d=000040 s=00000000! OK -- rreg (260,00007) a=4800(i0.it.cntl ) d=000040! s=00000000! OK -- wreg (242,00007) a=4800(i0.it.cntl ) d=000100 s=00000000! OK -- rreg (270,00007) a=4800(i0.it.cntl ) d=000100! s=00000000! OK -- wreg (252,00007) a=4800(i0.it.cntl ) d=000200 s=00000000! OK -- rreg (300,00007) a=4800(i0.it.cntl ) d=000200! s=00000000! OK -- wreg (262,00007) a=4800(i0.it.cntl ) d=000400 s=00000000! OK -- rreg (310,00007) a=4800(i0.it.cntl ) d=000400! s=00000000! OK -- wreg (272,00007) a=4800(i0.it.cntl ) d=000000 s=00000000! OK -- rreg (320,00027) a=4800(i0.it.cntl ) d=000000! s=00000000! OK # A2: reset cntl ------------------------------------- ++ wreg (302,00017) a=4800(i0.it.cntl ) d=177777 s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000005 s=00000000! OK -- rreg (330,00007) a=4800(i0.it.cntl ) d=000014! s=00000000! OK -- rreg (340,00027) a=4801(i0.it.stat ) d=000000! s=00000000! OK # A3: cntl,stat only rem accessible ------------------ ++ rreg (350,00017) a=4801(i0.it.stat ) d=000000! s=00000000! OK -- wreg (322,00007) a=0004(c0.al ) d=170000 s=00000000! OK -- wreg (332,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (360,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (342,00007) a=0004(c0.al ) d=170002 s=00000000! OK -- wreg (352,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (370,00027) a=0006(c0.mem ) d=000000 s=01000001| OK ++ attn (035,00037) d=000000! s=00000000! OK -- wtlam apat=0000 to=0 harvest only OK test_ibtst_regs.tcl: PASS # test_ibtst_data: test data register response ------------------------- # A1: data loc/rem access ---------------------------- ++ wreg (362,00017) a=0004(c0.al ) d=170004 s=00000000! OK -- wreg (372,00007) a=4800(i0.it.cntl ) d=000000 s=00000000! OK -- wreg (002,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (012,00007) a=4802(i0.it.data ) d=157255 s=01000001| OK -- wreg (022,00007) a=4800(i0.it.cntl ) d=000002 s=00000000! OK -- wreg (032,00007) a=0006(c0.mem ) d=157255 s=00000000! OK -- wreg (042,00007) a=4802(i0.it.data ) d=157255 s=01000001| OK -- wreg (052,00007) a=4800(i0.it.cntl ) d=000010 s=00000000! OK -- wreg (062,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (072,00007) a=4802(i0.it.data ) d=157255 s=00000000! OK -- wreg (102,00007) a=4800(i0.it.cntl ) d=000012 s=00000000! OK -- wreg (112,00007) a=0006(c0.mem ) d=157255 s=00000000! OK -- wreg (122,00007) a=4802(i0.it.data ) d=157255 s=00000000! OK -- wreg (132,00007) a=4800(i0.it.cntl ) d=000000 s=00000000! OK -- rreg (000,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (010,00007) a=4802(i0.it.data ) d=000000 s=01000001| OK -- wreg (142,00007) a=4800(i0.it.cntl ) d=000001 s=00000000! OK -- rreg (020,00007) a=0006(c0.mem ) d=157255! s=00000000! OK -- rreg (030,00007) a=4802(i0.it.data ) d=000000 s=01000001| OK -- wreg (152,00007) a=4800(i0.it.cntl ) d=000004 s=00000000! OK -- rreg (040,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (050,00007) a=4802(i0.it.data ) d=157255! s=00000000! OK -- wreg (162,00007) a=4800(i0.it.cntl ) d=000005 s=00000000! OK -- rreg (060,00007) a=0006(c0.mem ) d=157255! s=00000000! OK -- rreg (070,00027) a=4802(i0.it.data ) d=157255! s=00000000! OK # A2: data loc nak and bsy,bsy+ack,timeout ----------- ++ wreg (172,00017) a=4800(i0.it.cntl ) d=000060 s=00000000! OK -- wreg (202,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (100,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (212,00007) a=4800(i0.it.cntl ) d=000460 s=00000000! OK -- wreg (222,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (110,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (232,00007) a=4800(i0.it.cntl ) d=000200 s=00000000! OK -- wreg (242,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (120,00027) a=0006(c0.mem ) d=000000 s=01000001| OK # A3: data byte access (loc only) -------------------- ++ wreg (252,00017) a=4800(i0.it.cntl ) d=000003 s=00000000! OK -- wreg (262,00007) a=0006(c0.mem ) d=177777 s=00000000! OK -- wreg (272,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (302,00007) a=0006(c0.mem ) d=167021 s=00000000! OK -- rreg (130,00007) a=0006(c0.mem ) d=177421! s=00000000! OK -- wreg (312,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (322,00007) a=0006(c0.mem ) d=021335 s=00000000! OK -- rreg (140,00007) a=0006(c0.mem ) d=021021! s=00000000! OK -- wreg (332,00007) a=0010(c0.membe ) d=000003 s=00000000! OK -- wreg (342,00007) a=0006(c0.mem ) d=042063 s=00000000! OK -- rreg (150,00007) a=0006(c0.mem ) d=042063! s=00000000! OK -- wreg (352,00007) a=4800(i0.it.cntl ) d=000103 s=00000000! OK -- wreg (362,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (372,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (002,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (012,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (022,00007) a=0010(c0.membe ) d=000003 s=00000000! OK -- wreg (032,00007) a=0006(c0.mem ) d=137357 s=00000000! OK -- rreg (160,00027) a=0006(c0.mem ) d=137357! s=00000000! OK # A4: reset data ------------------------------------- ++ wreg (042,00017) a=4800(i0.it.cntl ) d=000014 s=00000000! OK -- wreg (052,00007) a=4802(i0.it.data ) d=157255 s=00000000! OK -- wreg (062,00007) a=0001(c0.cntl ) d=000005 s=00000000! OK -- rreg (170,00027) a=4802(i0.it.data ) d=000000! s=00000000! OK ++ attn (045,00037) d=000000! s=00000000! OK -- wtlam apat=0000 to=0 harvest only OK test_ibtst_data.tcl: PASS # test_ibtst_stat: test stat register response ------------------------- # A1: data rem access -------------------------------- ++ wreg (072,00017) a=0004(c0.al ) d=170004 s=00000000! OK -- wreg (102,00007) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wreg (112,00007) a=4802(i0.it.data ) d=011064 s=00000000! OK -- rreg (200,00007) a=4801(i0.it.stat ) d=000172! s=00000000! OK -- rreg (210,00007) a=4802(i0.it.data ) d=011064! s=00000000! OK -- rreg (220,00027) a=4801(i0.it.stat ) d=000171! s=00000000! OK # A2: data loc access -------------------------------- ++ wreg (122,00017) a=4800(i0.it.cntl ) d=000003 s=00000000! OK -- wreg (132,00007) a=0006(c0.mem ) d=177777 s=00000000! OK -- rreg (230,00007) a=4801(i0.it.stat ) d=000072! s=00000000! OK -- wreg (142,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (152,00007) a=0006(c0.mem ) d=167021 s=00000000! OK -- rreg (240,00007) a=4801(i0.it.stat ) d=000052! s=00000000! OK -- rreg (250,00007) a=0006(c0.mem ) d=177421! s=00000000! OK -- wreg (162,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (172,00007) a=0006(c0.mem ) d=021335 s=00000000! OK -- rreg (260,00007) a=4801(i0.it.stat ) d=000062! s=00000000! OK -- rreg (270,00007) a=0006(c0.mem ) d=021021! s=00000000! OK -- rreg (300,00027) a=4801(i0.it.stat ) d=000071! s=00000000! OK # A3: data cpu write -> rem read (busy=0) ------------ ++ wreg (202,00017) a=0004(c0.al ) d=002000 s=00000000! OK -- wblk (163,00027) a=0007(c0.memi ) n= 10= 10 s=00000000! OK 0: 012710 100200 112710 000377 112711 000377 005210 105210 8: 105211 011002 ++ wreg (212,00017) a=0008(c0.r0 ) d=170004 s=00000000! OK -- wreg (222,00007) a=0009(c0.r1 ) d=170005 s=00000000! OK -- wreg (232,00007) a=000a(c0.r2 ) d=157255 s=00000000! OK -- wreg (242,00007) a=000f(c0.pc ) d=002000 s=00000000! OK -- wreg (252,00007) a=0004(c0.al ) d=170004 s=00000000! OK -- wreg (262,00027) a=4800(i0.it.cntl ) d=100007 s=00000000! OK ++ wreg (272,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (310,00007) a=4801(i0.it.stat ) d=000032! s=00000000! OK -- rreg (320,00007) a=4802(i0.it.data ) d=100200! s=00000000! OK -- wreg (302,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (330,00007) a=4801(i0.it.stat ) d=000012! s=00000000! OK -- rreg (340,00007) a=4802(i0.it.data ) d=100377! s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (350,00007) a=4801(i0.it.stat ) d=000022! s=00000000! OK -- rreg (360,00007) a=4802(i0.it.data ) d=177777! s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (370,00007) a=4801(i0.it.stat ) d=000037! s=00000000! OK -- rreg (000,00007) a=4802(i0.it.data ) d=000000! s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (010,00007) a=4801(i0.it.stat ) d=000017! s=00000000! OK -- rreg (020,00007) a=4802(i0.it.data ) d=000001! s=00000000! OK -- wreg (342,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (030,00007) a=4801(i0.it.stat ) d=000027! s=00000000! OK -- rreg (040,00007) a=4802(i0.it.data ) d=000401! s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (050,00007) a=4801(i0.it.stat ) d=000031! s=00000000! OK -- rreg (060,00027) a=000a(c0.r2 ) d=000401! s=00000000! OK # A4: data cpu write -> rem read (busy=8) ------------ ++ wreg (362,00017) a=000a(c0.r2 ) d=157255 s=00000000! OK -- wreg (372,00007) a=000f(c0.pc ) d=002000 s=00000000! OK -- wreg (002,00027) a=4800(i0.it.cntl ) d=100067 s=00000000! OK ++ wreg (012,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (070,00007) a=4801(i0.it.stat ) d=000032! s=00000000! OK -- rreg (100,00007) a=4802(i0.it.data ) d=100200! s=00000000! OK -- wreg (022,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (110,00007) a=4801(i0.it.stat ) d=000012! s=00000000! OK -- rreg (120,00007) a=4802(i0.it.data ) d=100377! s=00000000! OK -- wreg (032,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (130,00007) a=4801(i0.it.stat ) d=000022! s=00000000! OK -- rreg (140,00007) a=4802(i0.it.data ) d=177777! s=00000000! OK -- wreg (042,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (150,00007) a=4801(i0.it.stat ) d=000037! s=00000000! OK -- rreg (160,00007) a=4802(i0.it.data ) d=000000! s=00000000! OK -- wreg (052,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (170,00007) a=4801(i0.it.stat ) d=000017! s=00000000! OK -- rreg (200,00007) a=4802(i0.it.data ) d=000001! s=00000000! OK -- wreg (062,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (210,00007) a=4801(i0.it.stat ) d=000027! s=00000000! OK -- rreg (220,00007) a=4802(i0.it.data ) d=000401! s=00000000! OK -- wreg (072,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (230,00007) a=4801(i0.it.stat ) d=000031! s=00000000! OK -- rreg (240,00027) a=000a(c0.r2 ) d=000401! s=00000000! OK test_ibtst_stat.tcl: PASS # test_ibtst_fifo: test fifo register response ------------------------- # A1: fifo loc/rem access ---------------------------- ++ wreg (102,00017) a=0004(c0.al ) d=170006 s=00000000! OK -- wreg (112,00007) a=4800(i0.it.cntl ) d=100000 s=00000000! OK -- wreg (122,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (132,00007) a=4803(i0.it.fifo ) d=157255 s=01000001| OK -- rreg (250,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (260,00007) a=4803(i0.it.fifo ) d=000000 s=01000001| OK -- wreg (142,00007) a=4800(i0.it.cntl ) d=000003 s=00000000! OK -- wreg (152,00007) a=0006(c0.mem ) d=010421 s=00000000! OK -- wreg (162,00007) a=4803(i0.it.fifo ) d=157255 s=01000001| OK -- rreg (270,00007) a=0006(c0.mem ) d=010421! s=00000000! OK -- rreg (300,00007) a=4803(i0.it.fifo ) d=000000 s=01000001| OK -- wreg (172,00007) a=4800(i0.it.cntl ) d=000006 s=00000000! OK -- wreg (202,00007) a=0006(c0.mem ) d=021042 s=00000000! OK -- wreg (212,00007) a=4803(i0.it.fifo ) d=157255 s=01000001| OK -- rreg (310,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (320,00007) a=4803(i0.it.fifo ) d=021042! s=00000000! OK -- wreg (222,00007) a=4800(i0.it.cntl ) d=000011 s=00000000! OK -- wreg (232,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (242,00007) a=4803(i0.it.fifo ) d=031463 s=00000000! OK -- rreg (330,00007) a=0006(c0.mem ) d=031463! s=00000000! OK -- rreg (340,00007) a=4803(i0.it.fifo ) d=000000 s=01000001| OK -- wreg (252,00007) a=4800(i0.it.cntl ) d=000014 s=00000000! OK -- wreg (262,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- wreg (272,00007) a=4803(i0.it.fifo ) d=042104 s=00000000! OK -- rreg (350,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (360,00027) a=4803(i0.it.fifo ) d=042104! s=00000000! OK # A2: fifo scalar (loc->rem); fifo clr --------------- ++ wreg (302,00017) a=4800(i0.it.cntl ) d=000006 s=00000000! OK -- wreg (312,00007) a=0006(c0.mem ) d=010021 s=00000000! OK -- rreg (370,00007) a=4801(i0.it.stat ) d=010072! s=00000000! OK -- wreg (322,00007) a=0006(c0.mem ) d=010022 s=00000000! OK -- rreg (000,00007) a=4801(i0.it.stat ) d=020072! s=00000000! OK -- wreg (332,00007) a=4800(i0.it.cntl ) d=100006 s=00000000! OK -- wreg (342,00007) a=0006(c0.mem ) d=020021 s=00000000! OK -- rreg (010,00007) a=4801(i0.it.stat ) d=010072! s=00000000! OK -- wreg (352,00007) a=0006(c0.mem ) d=020022 s=00000000! OK -- rreg (020,00007) a=4801(i0.it.stat ) d=020072! s=00000000! OK -- rreg (030,00007) a=4803(i0.it.fifo ) d=020021! s=00000000! OK -- rreg (040,00007) a=4801(i0.it.stat ) d=010171! s=00000000! OK -- rreg (050,00007) a=4803(i0.it.fifo ) d=020022! s=00000000! OK -- rreg (060,00007) a=4801(i0.it.stat ) d=000171! s=00000000! OK -- rreg (070,00007) a=4803(i0.it.fifo ) d=000000 s=01000001| OK -- rreg (100,00027) a=4801(i0.it.stat ) d=000171! s=00000000! OK # A3: fifo scalar (rem->loc) ------------------------- ++ wreg (362,00017) a=4800(i0.it.cntl ) d=000011 s=00000000! OK -- wreg (372,00007) a=4803(i0.it.fifo ) d=030021 s=00000000! OK -- rreg (110,00007) a=4801(i0.it.stat ) d=010172! s=00000000! OK -- wreg (002,00007) a=4803(i0.it.fifo ) d=030022 s=00000000! OK -- rreg (120,00007) a=4801(i0.it.stat ) d=020172! s=00000000! OK -- rreg (130,00007) a=0006(c0.mem ) d=030021! s=00000000! OK -- rreg (140,00007) a=4801(i0.it.stat ) d=010071! s=00000000! OK -- rreg (150,00007) a=0006(c0.mem ) d=030022! s=00000000! OK -- rreg (160,00007) a=4801(i0.it.stat ) d=000071! s=00000000! OK -- rreg (170,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- rreg (200,00027) a=4801(i0.it.stat ) d=000071! s=00000000! OK # A4: fifo block read (loc->rem, rblk, test abort) --- ++ wreg (012,00017) a=4800(i0.it.cntl ) d=000006 s=00000000! OK -- wreg (022,00007) a=0006(c0.mem ) d=040021 s=00000000! OK -- wreg (032,00007) a=0006(c0.mem ) d=040022 s=00000000! OK -- rblk (201,00027) a=4803(i0.it.fifo ) n= 3> 2! s=01000001| OK 0: 040021! 040022! # A5: fifo block write (rem->loc, wblk, test abort) -- ++ wreg (042,00017) a=4800(i0.it.cntl ) d=000011 s=00000000! OK -- wblk (173,00007) a=4803(i0.it.fifo ) n= 8= 8 s=00000000! OK 0: 050000 050021 050042 050063 050104 050125 050146 050167 -- rreg (210,00007) a=4801(i0.it.stat ) d=100172! s=00000000! OK -- wblk (203,00007) a=4803(i0.it.fifo ) n= 8> 7! s=01000001| OK 0: 050210 050231 050252 050273 050314 050335 050356 050377 -- rreg (220,00007) a=4801(i0.it.stat ) d=170172! s=00000000! OK -- rreg (230,00007) a=0006(c0.mem ) d=050000! s=00000000! OK -- rreg (240,00007) a=0006(c0.mem ) d=050021! s=00000000! OK -- rreg (250,00007) a=0006(c0.mem ) d=050042! s=00000000! OK -- rreg (260,00007) a=0006(c0.mem ) d=050063! s=00000000! OK -- rreg (270,00007) a=0006(c0.mem ) d=050104! s=00000000! OK -- rreg (300,00007) a=0006(c0.mem ) d=050125! s=00000000! OK -- rreg (310,00007) a=0006(c0.mem ) d=050146! s=00000000! OK -- rreg (320,00007) a=0006(c0.mem ) d=050167! s=00000000! OK -- rreg (330,00007) a=0006(c0.mem ) d=050210! s=00000000! OK -- rreg (340,00007) a=0006(c0.mem ) d=050231! s=00000000! OK -- rreg (350,00007) a=0006(c0.mem ) d=050252! s=00000000! OK -- rreg (360,00007) a=0006(c0.mem ) d=050273! s=00000000! OK -- rreg (370,00007) a=0006(c0.mem ) d=050314! s=00000000! OK -- rreg (000,00007) a=0006(c0.mem ) d=050335! s=00000000! OK -- rreg (010,00007) a=0006(c0.mem ) d=050356! s=00000000! OK -- rreg (020,00027) a=0006(c0.mem ) d=000000 s=01000001| OK # A6: reset fifo (and stat) -------------------------- ++ wreg (052,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wreg (062,00007) a=4803(i0.it.fifo ) d=157255 s=00000000! OK -- wreg (072,00007) a=0001(c0.cntl ) d=000005 s=00000000! OK -- rreg (030,00007) a=4801(i0.it.stat ) d=000000! s=00000000! OK -- rreg (040,00027) a=4803(i0.it.fifo ) d=000000 s=01000001| OK ++ attn (055,00037) d=000000! s=00000000! OK -- wtlam apat=0000 to=0 harvest only OK test_ibtst_fifo.tcl: PASS @w11a_ibtst/w11a_ibtst_all.dat: PASS ## steering file for all w11a_ibmon tests # test_ibmon_regs: test register response ----------------------------- # A basic register access tests ----------------------------- # A1: write/read cntl--------------------------------- ++ wreg (102,00017) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- rreg (050,00007) a=4000(i0.im.cntl ) d=000000! s=00000000! OK -- wreg (112,00007) a=4000(i0.im.cntl ) d=000015 s=00000000! OK -- rreg (060,00007) a=4000(i0.im.cntl ) d=000010! s=00000000! OK -- wreg (122,00007) a=4000(i0.im.cntl ) d=000025 s=00000000! OK -- rreg (070,00007) a=4000(i0.im.cntl ) d=000020! s=00000000! OK -- wreg (132,00007) a=4000(i0.im.cntl ) d=000045 s=00000000! OK -- rreg (100,00007) a=4000(i0.im.cntl ) d=000040! s=00000000! OK -- wreg (142,00007) a=4000(i0.im.cntl ) d=000105 s=00000000! OK -- rreg (110,00007) a=4000(i0.im.cntl ) d=000100! s=00000000! OK -- wreg (152,00007) a=4000(i0.im.cntl ) d=000205 s=00000000! OK -- rreg (120,00007) a=4000(i0.im.cntl ) d=000200! s=00000000! OK -- wreg (162,00007) a=4000(i0.im.cntl ) d=000405 s=00000000! OK -- rreg (130,00007) a=4000(i0.im.cntl ) d=000400! s=00000000! OK -- wreg (172,00007) a=4000(i0.im.cntl ) d=000135 s=00000000! OK -- rreg (140,00007) a=4000(i0.im.cntl ) d=000130! s=00000000! OK -- wreg (202,00007) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- rreg (150,00007) a=4000(i0.im.cntl ) d=000130! s=00000000! OK -- wreg (212,00007) a=4000(i0.im.cntl ) d=000000 s=00000000! OK -- rreg (160,00027) a=4000(i0.im.cntl ) d=000130! s=00000000! OK # A2: write cntl, read stat -------------------------- ++ wreg (222,00017) a=4000(i0.im.cntl ) d=000115 s=00000000! OK -- rreg (170,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (200,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- wreg (232,00007) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (210,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (220,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- wreg (242,00007) a=4000(i0.im.cntl ) d=000007 s=00000000! OK -- rreg (230,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (240,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- wreg (252,00007) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- rreg (250,00027) a=4001(i0.im.stat ) d=000000! s=00000000! OK ++ wreg (262,00017) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (260,00007) a=4001(i0.im.stat ) d=000000! s=00000000! OK -- wreg (272,00007) a=4000(i0.im.cntl ) d=000007 s=00000000! OK -- rreg (270,00027) a=4001(i0.im.stat ) d=000000! s=00000000! OK ++ wreg (302,00017) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- rreg (300,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- wreg (312,00007) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (310,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- wreg (322,00007) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- rreg (320,00027) a=4001(i0.im.stat ) d=000001! s=00000000! OK ++ wreg (332,00017) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- rreg (330,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- wreg (342,00007) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (340,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- wreg (352,00007) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (350,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- wreg (362,00007) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- rreg (360,00027) a=4001(i0.im.stat ) d=000000! s=00000000! OK ++ rreg (370,00037) a=4001(i0.im.stat ) d=000000 s=00000000! OK # A3: test addr -------------------------------------- # A3.1: write/read addr when stopped ----------------- ++ wreg (372,00017) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rreg (000,00027) a=4004(i0.im.addr ) d=000000! s=00000000! OK ++ wreg (002,00017) a=4004(i0.im.addr ) d=000003 s=00000000! OK -- rreg (010,00027) a=4004(i0.im.addr ) d=000003! s=00000000! OK ++ wreg (012,00017) a=4004(i0.im.addr ) d=001774 s=00000000! OK -- rreg (020,00027) a=4004(i0.im.addr ) d=001774! s=00000000! OK ++ wreg (022,00017) a=4004(i0.im.addr ) d=001777 s=00000000! OK -- rreg (030,00027) a=4004(i0.im.addr ) d=001777! s=00000000! OK # A3.2: verify that starting clears addr ------------- ++ wreg (032,00017) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- wreg (042,00007) a=4004(i0.im.addr ) d=001774 s=00000000! OK -- rreg (040,00007) a=4004(i0.im.addr ) d=001774! s=00000000! OK -- wreg (052,00007) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- rreg (050,00007) a=4004(i0.im.addr ) d=000000! s=00000000! OK -- wreg (062,00027) a=4000(i0.im.cntl ) d=000004 s=00000000! OK # A3.3: test err when started and addr written ------- ++ wreg (072,00017) a=4000(i0.im.cntl ) d=000005 s=00000000! OK -- wreg (102,00007) a=4004(i0.im.addr ) d=000400 s=01000001| OK -- wreg (112,00027) a=4000(i0.im.cntl ) d=000004 s=00000000! OK # A4: test data -------------------------------------- # A4.1: when stopped --------------------------------- ++ wreg (122,00017) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- wreg (132,00007) a=4004(i0.im.addr ) d=000040 s=00000000! OK -- rreg (060,00007) a=4005(i0.im.data ) d=157777 s=00000000! OK -- rreg (070,00007) a=4004(i0.im.addr ) d=000041! s=00000000! OK -- rreg (100,00007) a=4005(i0.im.data ) d=000017 s=00000000! OK -- rreg (110,00007) a=4004(i0.im.addr ) d=000042! s=00000000! OK -- rreg (120,00007) a=4005(i0.im.data ) d=000256 s=00000000! OK -- rreg (130,00007) a=4004(i0.im.addr ) d=000043! s=00000000! OK -- rreg (140,00007) a=4005(i0.im.data ) d=011000 s=00000000! OK -- rreg (150,00027) a=4004(i0.im.addr ) d=000044! s=00000000! OK # A4.2: test err when written ------------------------ ++ wreg (142,00037) a=4005(i0.im.data ) d=000400 s=01000001| OK # A5: test hilim/lolim ------------------------------- ++ wreg (152,00017) a=4002(i0.im.hilim ) d=162346 s=00000000! OK -- wreg (162,00007) a=4003(i0.im.lolim ) d=161234 s=00000000! OK -- rreg (160,00007) a=4002(i0.im.hilim ) d=162346! s=00000000! OK -- rreg (170,00007) a=4003(i0.im.lolim ) d=161234! s=00000000! OK -- wreg (172,00007) a=4002(i0.im.hilim ) d=017777 s=00000000! OK -- wreg (202,00007) a=4003(i0.im.lolim ) d=000001 s=00000000! OK -- rreg (200,00007) a=4002(i0.im.hilim ) d=177776! s=00000000! OK -- rreg (210,00027) a=4003(i0.im.lolim ) d=160000! s=00000000! OK # A6: test reset behavior ---------------------------- # A6.1: no reset on BRESET --------------------------- ++ wreg (212,00017) a=4002(i0.im.hilim ) d=172000 s=00000000! OK -- wreg (222,00007) a=4003(i0.im.lolim ) d=171000 s=00000000! OK -- wreg (232,00007) a=4000(i0.im.cntl ) d=000115 s=00000000! OK -- wreg (242,00007) a=4000(i0.im.cntl ) d=000006 s=00000000! OK -- rreg (220,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (230,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- rreg (240,00007) a=4002(i0.im.hilim ) d=172000! s=00000000! OK -- rreg (250,00007) a=4003(i0.im.lolim ) d=171000! s=00000000! OK -- wreg (252,00007) a=0001(c0.cntl ) d=000005 s=00000000! OK -- rreg (260,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (270,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- rreg (300,00007) a=4002(i0.im.hilim ) d=172000! s=00000000! OK -- rreg (310,00027) a=4003(i0.im.lolim ) d=171000! s=00000000! OK # A6.2: no reset on CRESET --------------------------- ++ wreg (262,00017) a=0001(c0.cntl ) d=000004 s=00000000! OK -- rreg (320,00007) a=4000(i0.im.cntl ) d=000110! s=00000000! OK -- rreg (330,00007) a=4001(i0.im.stat ) d=000003! s=00000000! OK -- rreg (340,00007) a=4002(i0.im.hilim ) d=172000! s=00000000! OK -- rreg (350,00027) a=4003(i0.im.lolim ) d=171000! s=00000000! OK # A6.2: test reset on GRESET ------------------------- ++ init (006,00037) a=0000(c0.conf ) d=000001 s=00000000! OK ++ rreg (360,00017) a=4000(i0.im.cntl ) d=000070! s=00000000! OK -- rreg (370,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- rreg (000,00007) a=4002(i0.im.hilim ) d=177776! s=00000000! OK -- rreg (010,00027) a=4003(i0.im.lolim ) d=160000! s=00000000! OK ++ attn (065,00037) d=000000 s=00000000! OK -- wtlam apat=0000 to=0 harvest only OK test_ibmon_regs.tcl: PASS # test_ibmon_cpu: test basics with cpu register accesses -------------- # A exercise monitor data access via data/addr regs --------- # A1: capture write/read rem and loc ----------------- ++ wreg (272,00017) a=4002(i0.im.hilim ) d=177776 s=00000000! OK -- wreg (302,00007) a=4003(i0.im.lolim ) d=160000 s=00000000! OK -- wreg (312,00007) a=4000(i0.im.cntl ) d=000075 s=00000000! OK -- rreg (020,00007) a=4001(i0.im.stat ) d=000001! s=00000000! OK -- wreg (322,00007) a=4a50(i0.parsi.0 ) d=157255 s=00000000! OK -- rreg (030,00007) a=4a50(i0.parsi.0 ) d=157255! s=00000000! OK -- wreg (332,00007) a=0004(c0.al ) d=172240 s=00000000! OK -- wreg (342,00007) a=0006(c0.mem ) d=137357 s=00000000! OK -- rreg (040,00007) a=0006(c0.mem ) d=137357! s=00000000! OK -- wreg (352,00007) a=4000(i0.im.cntl ) d=000004 s=00000000! OK -- rreg (050,00007) a=4001(i0.im.stat ) d=000000! s=00000000! OK -- rreg (060,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK # A1.1: read all in one rblk ------------------------- ++ wreg (362,00017) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (211,00007) a=4005(i0.im.data ) n= 16= 16 s=00000000! OK 0: 172241! 157255! 001235- 011000! 172241! 157255! 000041- 010000! 8: 152241! 137357! 000135- 011000! 152241! 137357! 000042- 010000! -- rreg (070,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK # A1.2: random address read -------------------------- ++ wreg (372,00017) a=4004(i0.im.addr ) d=000001 s=00000000! OK -- rreg (100,00007) a=4005(i0.im.data ) d=157255! s=00000000! OK -- rreg (110,00027) a=4004(i0.im.addr ) d=000002! s=00000000! OK ++ wreg (002,00017) a=4004(i0.im.addr ) d=000003 s=00000000! OK -- rreg (120,00007) a=4005(i0.im.data ) d=011000! s=00000000! OK -- rreg (130,00027) a=4004(i0.im.addr ) d=000004! s=00000000! OK ++ wreg (012,00017) a=4004(i0.im.addr ) d=000005 s=00000000! OK -- rreg (140,00007) a=4005(i0.im.data ) d=157255! s=00000000! OK -- rreg (150,00027) a=4004(i0.im.addr ) d=000006! s=00000000! OK ++ wreg (022,00017) a=4004(i0.im.addr ) d=000007 s=00000000! OK -- rreg (160,00007) a=4005(i0.im.data ) d=010000! s=00000000! OK -- rreg (170,00027) a=4004(i0.im.addr ) d=000010! s=00000000! OK ++ wreg (032,00017) a=4004(i0.im.addr ) d=000006 s=00000000! OK -- rreg (200,00007) a=4005(i0.im.data ) d=000041 s=00000000! OK -- rreg (210,00027) a=4004(i0.im.addr ) d=000007! s=00000000! OK ++ wreg (042,00017) a=4004(i0.im.addr ) d=000004 s=00000000! OK -- rreg (220,00007) a=4005(i0.im.data ) d=172241! s=00000000! OK -- rreg (230,00027) a=4004(i0.im.addr ) d=000005! s=00000000! OK ++ wreg (052,00017) a=4004(i0.im.addr ) d=000002 s=00000000! OK -- rreg (240,00007) a=4005(i0.im.data ) d=001235 s=00000000! OK -- rreg (250,00027) a=4004(i0.im.addr ) d=000003! s=00000000! OK ++ wreg (062,00017) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rreg (260,00007) a=4005(i0.im.data ) d=172241! s=00000000! OK -- rreg (270,00027) a=4004(i0.im.addr ) d=000001! s=00000000! OK ++ wreg (072,00017) a=4004(i0.im.addr ) d=000011 s=00000000! OK -- rreg (300,00007) a=4005(i0.im.data ) d=137357! s=00000000! OK -- rreg (310,00027) a=4004(i0.im.addr ) d=000012! s=00000000! OK ++ wreg (102,00017) a=4004(i0.im.addr ) d=000013 s=00000000! OK -- rreg (320,00007) a=4005(i0.im.data ) d=011000! s=00000000! OK -- rreg (330,00027) a=4004(i0.im.addr ) d=000014! s=00000000! OK ++ wreg (112,00017) a=4004(i0.im.addr ) d=000015 s=00000000! OK -- rreg (340,00007) a=4005(i0.im.data ) d=137357! s=00000000! OK -- rreg (350,00027) a=4004(i0.im.addr ) d=000016! s=00000000! OK ++ wreg (122,00017) a=4004(i0.im.addr ) d=000017 s=00000000! OK -- rreg (360,00007) a=4005(i0.im.data ) d=010000! s=00000000! OK -- rreg (370,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK ++ wreg (132,00017) a=4004(i0.im.addr ) d=000016 s=00000000! OK -- rreg (000,00007) a=4005(i0.im.data ) d=000042 s=00000000! OK -- rreg (010,00027) a=4004(i0.im.addr ) d=000017! s=00000000! OK ++ wreg (142,00017) a=4004(i0.im.addr ) d=000014 s=00000000! OK -- rreg (020,00007) a=4005(i0.im.data ) d=152241! s=00000000! OK -- rreg (030,00027) a=4004(i0.im.addr ) d=000015! s=00000000! OK ++ wreg (152,00017) a=4004(i0.im.addr ) d=000012 s=00000000! OK -- rreg (040,00007) a=4005(i0.im.data ) d=000135 s=00000000! OK -- rreg (050,00027) a=4004(i0.im.addr ) d=000013! s=00000000! OK ++ wreg (162,00017) a=4004(i0.im.addr ) d=000010 s=00000000! OK -- rreg (060,00007) a=4005(i0.im.data ) d=152241! s=00000000! OK -- rreg (070,00027) a=4004(i0.im.addr ) d=000011! s=00000000! OK # A1.3: random address with rblk length 2 ------------ ++ wreg (172,00017) a=4004(i0.im.addr ) d=000001 s=00000000! OK -- rblk (221,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 157255! 001235- -- rreg (100,00027) a=4004(i0.im.addr ) d=000003! s=00000000! OK ++ wreg (202,00017) a=4004(i0.im.addr ) d=000003 s=00000000! OK -- rblk (231,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 011000! 172241! -- rreg (110,00027) a=4004(i0.im.addr ) d=000005! s=00000000! OK ++ wreg (212,00017) a=4004(i0.im.addr ) d=000005 s=00000000! OK -- rblk (241,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 157255! 000041- -- rreg (120,00027) a=4004(i0.im.addr ) d=000007! s=00000000! OK ++ wreg (222,00017) a=4004(i0.im.addr ) d=000007 s=00000000! OK -- rblk (251,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 010000! 152241! -- rreg (130,00027) a=4004(i0.im.addr ) d=000011! s=00000000! OK ++ wreg (232,00017) a=4004(i0.im.addr ) d=000006 s=00000000! OK -- rblk (261,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 000041- 010000! -- rreg (140,00027) a=4004(i0.im.addr ) d=000010! s=00000000! OK ++ wreg (242,00017) a=4004(i0.im.addr ) d=000004 s=00000000! OK -- rblk (271,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 172241! 157255! -- rreg (150,00027) a=4004(i0.im.addr ) d=000006! s=00000000! OK ++ wreg (252,00017) a=4004(i0.im.addr ) d=000002 s=00000000! OK -- rblk (301,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 001235- 011000! -- rreg (160,00027) a=4004(i0.im.addr ) d=000004! s=00000000! OK ++ wreg (262,00017) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (311,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 172241! 157255! -- rreg (170,00027) a=4004(i0.im.addr ) d=000002! s=00000000! OK ++ wreg (272,00017) a=4004(i0.im.addr ) d=000011 s=00000000! OK -- rblk (321,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 137357! 000135- -- rreg (200,00027) a=4004(i0.im.addr ) d=000013! s=00000000! OK ++ wreg (302,00017) a=4004(i0.im.addr ) d=000013 s=00000000! OK -- rblk (331,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 011000! 152241! -- rreg (210,00027) a=4004(i0.im.addr ) d=000015! s=00000000! OK ++ wreg (312,00017) a=4004(i0.im.addr ) d=000015 s=00000000! OK -- rblk (341,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 137357! 000042- -- rreg (220,00027) a=4004(i0.im.addr ) d=000017! s=00000000! OK ++ wreg (322,00017) a=4004(i0.im.addr ) d=000016 s=00000000! OK -- rblk (351,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 000042- 010000! -- rreg (230,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK ++ wreg (332,00017) a=4004(i0.im.addr ) d=000014 s=00000000! OK -- rblk (361,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 152241! 137357! -- rreg (240,00027) a=4004(i0.im.addr ) d=000016! s=00000000! OK ++ wreg (342,00017) a=4004(i0.im.addr ) d=000012 s=00000000! OK -- rblk (371,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 000135- 011000! -- rreg (250,00027) a=4004(i0.im.addr ) d=000014! s=00000000! OK ++ wreg (352,00017) a=4004(i0.im.addr ) d=000010 s=00000000! OK -- rblk (001,00007) a=4005(i0.im.data ) n= 2= 2 s=00000000! OK 0: 152241! 137357! -- rreg (260,00027) a=4004(i0.im.addr ) d=000012! s=00000000! OK # B test rreg,wreg capture: ack,we,be* flags ---------------- # B1.1: test byte racc access (via wibr/ribr) -------- ++ wreg (362,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (372,00017) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (002,00007) a=4a50(i0.parsi.0 ) d=000252 s=00000000! OK -- rreg (270,00007) a=4a50(i0.parsi.0 ) d=137252! s=00000000! OK -- wreg (012,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (022,00007) a=4a50(i0.parsi.0 ) d=052400 s=00000000! OK -- rreg (300,00007) a=4a50(i0.parsi.0 ) d=052652! s=00000000! OK -- wreg (032,00007) a=0010(c0.membe ) d=000000 s=00000000! OK -- wreg (042,00007) a=4a50(i0.parsi.0 ) d=175336 s=00000000! OK -- rreg (310,00027) a=4a50(i0.parsi.0 ) d=052652! s=00000000! OK ++ wreg (052,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (320,00017) a=4004(i0.im.addr ) d=000030! s=00000000! OK -- wreg (062,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (011,00007) a=4005(i0.im.data ) n= 24= 24 s=00000000! OK 0: 072241! 000252! 020046- 011000! 172241! 137252! 000042- 010000! 8: 132241! 052400! 000135- 011000! 172241! 052652! 000041- 010000! 16: 032241! 175336! 000136- 011000! 172241! 052652! 000041- 010000! -- rreg (330,00027) a=4004(i0.im.addr ) d=000030! s=00000000! OK # B1.2: test byte cacc access (via wm/rm) ------------ ++ wreg (072,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (102,00017) a=0004(c0.al ) d=172240 s=00000000! OK -- wreg (112,00007) a=0010(c0.membe ) d=000001 s=00000000! OK -- wreg (122,00007) a=0006(c0.mem ) d=177464 s=00000000! OK -- rreg (340,00007) a=0006(c0.mem ) d=052464! s=00000000! OK -- wreg (132,00007) a=0010(c0.membe ) d=000002 s=00000000! OK -- wreg (142,00007) a=0006(c0.mem ) d=011377 s=00000000! OK -- rreg (350,00007) a=0006(c0.mem ) d=011064! s=00000000! OK -- wreg (152,00007) a=0010(c0.membe ) d=000000 s=00000000! OK -- wreg (162,00007) a=0006(c0.mem ) d=175336 s=00000000! OK -- rreg (360,00027) a=0006(c0.mem ) d=011064! s=00000000! OK ++ wreg (172,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (370,00017) a=4004(i0.im.addr ) d=000030! s=00000000! OK -- wreg (202,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (021,00007) a=4005(i0.im.data ) n= 24= 24 s=00000000! OK 0: 052241! 177464! 002061- 011000! 152241! 052464! 000042- 010000! 8: 112241! 011377! 000135- 011000! 152241! 011064! 000041- 010000! 16: 012241! 175336! 000135- 011000! 152241! 011064! 000042- 010000! -- rreg (000,00027) a=4004(i0.im.addr ) d=000030! s=00000000! OK # B1.3: test loc access (via cpu code) -------------- ++ wreg (212,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (213,00027) a=0007(c0.memi ) n= 10= 10 s=00000000! OK 0: 012710 177777 005210 011001 105310 011002 105260 000001 8: 011003 000000 ++ wreg (222,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (232,00017) a=0008(c0.r0 ) d=172240 s=00000000! OK -- wreg (242,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (342,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (352,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:40.458620 : ATTN notify apat = 0001 lams = 0 dt=8.332688 ++ attn (075,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.020 OK ++ rreg (010,00037) a=000f(c0.pc ) d=001024! s=00000000! OK ++ rreg (020,00017) a=0009(c0.r1 ) d=000000! s=00000000! OK -- rreg (030,00007) a=000a(c0.r2 ) d=000377! s=00000000! OK -- rreg (040,00027) a=000b(c0.r3 ) d=000777! s=00000000! OK ++ wreg (362,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (050,00017) a=4004(i0.im.addr ) d=000050! s=00000000! OK -- wreg (372,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (031,00007) a=4005(i0.im.data ) n= 40= 40 s=00000000! OK 0: 152240! 177777! 004066- 011000! 152240! 177777! 000005- 010400! 8: 152240! 000000! 000001- 111400! 152240! 000000! 000005- 010000! 16: 052240! 000000! 000005- 010400! 052240! 177777! 000001- 111400! 24: 152240! 000377! 000005- 010000! 112240! 000377! 000007- 010400! 32: 112240! 000401! 000001- 111400! 152240! 000777! 000005- 010000! -- rreg (060,00027) a=4004(i0.im.addr ) d=000050! s=00000000! OK # C test access mode enable flags --------------------------- ++ wreg (002,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (223,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 010110 # C1.1: test conena ---------------------------------- ++ wreg (012,00037) a=4000(i0.im.cntl ) d=000045 s=00000000! OK ++ wreg (022,00017) a=4a50(i0.parsi.0 ) d=000400 s=00000000! OK -- wreg (032,00007) a=0004(c0.al ) d=172242 s=00000000! OK -- wreg (042,00007) a=0006(c0.mem ) d=000401 s=00000000! OK -- wreg (052,00007) a=0008(c0.r0 ) d=172244 s=00000000! OK -- wreg (062,00007) a=0009(c0.r1 ) d=000402 s=00000000! OK -- wreg (072,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (102,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (070,00007) a=000f(c0.pc ) d=001002! s=00000000! OK -- rreg (100,00007) a=4a50(i0.parsi.0 ) d=000400! s=00000000! OK -- wreg (112,00007) a=0004(c0.al ) d=172242 s=00000000! OK -- rreg (110,00007) a=0006(c0.mem ) d=000401! s=00000000! OK -- rreg (120,00027) a=4a52(i0.parsi.2 ) d=000402! s=00000000! OK ++ wreg (122,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (130,00017) a=4004(i0.im.addr ) d=000024! s=00000000! OK -- wreg (132,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (041,00007) a=4005(i0.im.data ) n= 20= 20 s=00000000! OK 0: 172241! 000400! 004050- 011000! 152243! 000401! 000136- 011000! 8: 172241! 000400! 000404- 010000! 152243! 000401! 000121- 010000! 16: 172245! 000402! 000040- 010000! -- rreg (140,00027) a=4004(i0.im.addr ) d=000024! s=00000000! OK # C1.2: test remena ---------------------------------- ++ wreg (142,00037) a=4000(i0.im.cntl ) d=000025 s=00000000! OK ++ wreg (152,00017) a=4a50(i0.parsi.0 ) d=001000 s=00000000! OK -- wreg (162,00007) a=0006(c0.mem ) d=001001 s=00000000! OK -- wreg (172,00007) a=0009(c0.r1 ) d=001002 s=00000000! OK -- wreg (202,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (212,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (150,00007) a=4a50(i0.parsi.0 ) d=001000! s=00000000! OK -- wreg (222,00007) a=0004(c0.al ) d=172242 s=00000000! OK -- rreg (160,00007) a=0006(c0.mem ) d=001001! s=00000000! OK -- rreg (170,00027) a=4a52(i0.parsi.2 ) d=001002! s=00000000! OK ++ wreg (232,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (200,00017) a=4004(i0.im.addr ) d=000014! s=00000000! OK -- wreg (242,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (051,00007) a=4005(i0.im.data ) n= 12= 12 s=00000000! OK 0: 172241! 001000! 001636- 011000! 172241! 001000! 000342- 010000! 8: 172245! 001002! 000163- 010000! -- rreg (210,00027) a=4004(i0.im.addr ) d=000014! s=00000000! OK # C1.3: test locena ---------------------------------- ++ wreg (252,00037) a=4000(i0.im.cntl ) d=000015 s=00000000! OK ++ wreg (262,00017) a=4a50(i0.parsi.0 ) d=001400 s=00000000! OK -- wreg (272,00007) a=0006(c0.mem ) d=001401 s=00000000! OK -- wreg (302,00007) a=0009(c0.r1 ) d=001402 s=00000000! OK -- wreg (312,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (220,00007) a=4a50(i0.parsi.0 ) d=001400! s=00000000! OK -- wreg (332,00007) a=0004(c0.al ) d=172242 s=00000000! OK -- rreg (230,00007) a=0006(c0.mem ) d=001401! s=00000000! OK -- rreg (240,00027) a=4a52(i0.parsi.2 ) d=001402! s=00000000! OK ++ wreg (342,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (250,00017) a=4004(i0.im.addr ) d=000004! s=00000000! OK -- wreg (352,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (061,00007) a=4005(i0.im.data ) n= 4= 4 s=00000000! OK 0: 152244! 001402! 001772- 011000! -- rreg (260,00027) a=4004(i0.im.addr ) d=000004! s=00000000! OK # D test hilim,lolim ---------------------------------------- ++ wreg (362,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (372,00017) a=4002(i0.im.hilim ) d=172242 s=00000000! OK -- wreg (002,00007) a=4003(i0.im.lolim ) d=172240 s=00000000! OK -- wreg (012,00007) a=4a50(i0.parsi.0 ) d=010400 s=00000000! OK -- wreg (022,00007) a=4a51(i0.parsi.1 ) d=010401 s=00000000! OK -- wreg (032,00007) a=4a52(i0.parsi.2 ) d=010402 s=00000000! OK -- rreg (270,00007) a=4a50(i0.parsi.0 ) d=010400! s=00000000! OK -- rreg (300,00007) a=4a51(i0.parsi.1 ) d=010401! s=00000000! OK -- rreg (310,00007) a=4a52(i0.parsi.2 ) d=010402! s=00000000! OK -- wreg (042,00007) a=4002(i0.im.hilim ) d=177777 s=00000000! OK -- wreg (052,00027) a=4003(i0.im.lolim ) d=160000 s=00000000! OK ++ wreg (062,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (320,00017) a=4004(i0.im.addr ) d=000020! s=00000000! OK -- wreg (072,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (071,00007) a=4005(i0.im.data ) n= 16= 16 s=00000000! OK 0: 172241! 010400! 001674- 011000! 172243! 010401! 000065- 011000! 8: 172241! 010400! 000131- 010000! 172243! 010401! 000040- 010000! -- rreg (330,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK test_ibmon_cpu.tcl: PASS # test_ibmon_ibtest: tests with ibd_ibtst as target ------------------- # A exercise ack,nak,tout,busy and nbusy -------------------- ++ wreg (102,00017) a=4002(i0.im.hilim ) d=170006 s=00000000! OK -- wreg (112,00027) a=4003(i0.im.lolim ) d=170004 s=00000000! OK # A1: ack,nak on data -------------------------------- ++ wreg (122,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (132,00017) a=0004(c0.al ) d=170004 s=00000000! OK -- wreg (142,00007) a=4800(i0.it.cntl ) d=000000 s=00000000! OK -- wreg (152,00007) a=4802(i0.it.data ) d=157255 s=01000001| OK -- rreg (340,00007) a=4802(i0.it.data ) d=000000 s=01000001| OK -- wreg (162,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (350,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (172,00007) a=4800(i0.it.cntl ) d=000014 s=00000000! OK -- wreg (202,00007) a=4802(i0.it.data ) d=010421 s=00000000! OK -- rreg (360,00007) a=4802(i0.it.data ) d=010421! s=00000000! OK -- wreg (212,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (370,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (222,00007) a=4800(i0.it.cntl ) d=000003 s=00000000! OK -- wreg (232,00007) a=4802(i0.it.data ) d=157255 s=01000001| OK -- rreg (000,00007) a=4802(i0.it.data ) d=000000 s=01000001| OK -- wreg (242,00007) a=0006(c0.mem ) d=021042 s=00000000! OK -- rreg (010,00027) a=0006(c0.mem ) d=021042! s=00000000! OK ++ wreg (252,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (020,00017) a=4004(i0.im.addr ) d=000060! s=00000000! OK -- wreg (262,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (101,00007) a=4005(i0.im.data ) n= 48= 48 s=00000000! OK 0: 170005! 157255! 002413- 021000! 170005! 000000- 000042- 020000! 8: 150005! 157255! 000055- 021000! 150005! 000000- 000041- 020000! 16: 170005! 010421! 000153- 011000! 170005! 010421! 000042- 010000! 24: 150005! 157255! 000055- 021000! 150005! 010421- 000041- 020000! 32: 170005! 157255! 000135- 021000! 170005! 010421- 000042- 020000! 40: 150005! 021042! 000055- 011000! 150005! 021042! 000041- 010000! -- rreg (030,00027) a=4004(i0.im.addr ) d=000060! s=00000000! OK # A2: ack with busy on data -------------------------- ++ wreg (272,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (302,00017) a=4800(i0.it.cntl ) d=000057 s=00000000! OK -- wreg (312,00007) a=4802(i0.it.data ) d=000401 s=00000000! OK -- rreg (040,00007) a=4802(i0.it.data ) d=000401! s=00000000! OK -- wreg (322,00007) a=0006(c0.mem ) d=000402 s=00000000! OK -- rreg (050,00007) a=0006(c0.mem ) d=000402! s=00000000! OK -- wreg (332,00007) a=4800(i0.it.cntl ) d=000037 s=00000000! OK -- wreg (342,00007) a=4802(i0.it.data ) d=001001 s=00000000! OK -- rreg (060,00007) a=4802(i0.it.data ) d=001001! s=00000000! OK -- wreg (352,00007) a=0006(c0.mem ) d=001002 s=00000000! OK -- rreg (070,00007) a=0006(c0.mem ) d=001002! s=00000000! OK -- wreg (362,00007) a=4800(i0.it.cntl ) d=000077 s=00000000! OK -- wreg (372,00007) a=4802(i0.it.data ) d=001401 s=00000000! OK -- rreg (100,00007) a=4802(i0.it.data ) d=001401! s=00000000! OK -- wreg (002,00007) a=0006(c0.mem ) d=001402 s=00000000! OK -- rreg (110,00027) a=0006(c0.mem ) d=001402! s=00000000! OK ++ wreg (012,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (120,00017) a=4004(i0.im.addr ) d=000060! s=00000000! OK -- wreg (022,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (111,00007) a=4005(i0.im.data ) n= 48= 48 s=00000000! OK 0: 170005! 000401! 002611- 011000! 170005! 000401! 000041- 010000! 8: 150005! 000402! 000056- 015010! 150005! 000402! 000031- 010000! 16: 170005! 001001! 000135- 011000! 170005! 001001! 000042- 010000! 24: 150005! 001002! 000055- 011000! 150005! 001002! 000041- 014010! 32: 170005! 001401! 000125- 011000! 170005! 001401! 000042- 010000! 40: 150005! 001402! 000055- 015010! 150005! 001402! 000031- 014010! -- rreg (130,00027) a=4004(i0.im.addr ) d=000060! s=00000000! OK # A3: nak on data (bsy,bsy+datab,datto,datto+datab) -- ++ wreg (032,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (042,00017) a=4800(i0.it.cntl ) d=000014 s=00000000! OK -- wreg (052,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (140,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (062,00007) a=4800(i0.it.cntl ) d=000054 s=00000000! OK -- wreg (072,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (150,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (102,00007) a=4800(i0.it.cntl ) d=000034 s=00000000! OK -- wreg (112,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (160,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (122,00007) a=4800(i0.it.cntl ) d=000474 s=00000000! OK -- wreg (132,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (170,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (142,00007) a=4800(i0.it.cntl ) d=000214 s=00000000! OK -- wreg (152,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (200,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (162,00007) a=4800(i0.it.cntl ) d=000274 s=00000000! OK -- wreg (172,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (210,00007) a=0006(c0.mem ) d=000000 s=01000001| OK -- wreg (202,00007) a=4800(i0.it.cntl ) d=000674 s=00000000! OK -- wreg (212,00007) a=0006(c0.mem ) d=157255 s=01000001| OK -- rreg (220,00027) a=0006(c0.mem ) d=000000 s=01000001| OK ++ wreg (222,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (230,00017) a=4004(i0.im.addr ) d=000070! s=00000000! OK -- wreg (232,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (121,00007) a=4005(i0.im.data ) n= 56= 56 s=00000000! OK 0: 150005! 157255! 002512- 021000! 150005! 001402- 000041- 020000! 8: 150005! 157255! 000135- 025010! 150005! 001402- 000032- 020000! 16: 150005! 157255! 000135- 021000! 150005! 001402- 000041- 024010! 24: 150005! 157255! 000126- 035010! 150005! 001402- 000031- 034010! 32: 150005! 157255! 000125- 065077! 150005! 001402- 000021- 064077! 40: 150005! 157255! 000047- 065077! 150005! 001402- 000020- 064077! 48: 150005! 157255! 000047- 075077! 150005! 001402- 000020- 074077! -- rreg (240,00027) a=4004(i0.im.addr ) d=000070! s=00000000! OK # B fifo basics --------------------------------------------- # B1: fifo read test (write 2, read 3) ------------- ++ wreg (242,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (252,00017) a=0004(c0.al ) d=170006 s=00000000! OK -- wreg (262,00007) a=4800(i0.it.cntl ) d=100011 s=00000000! OK -- wblk (233,00007) a=4803(i0.it.fifo ) n= 2= 2 s=00000000! OK 0: 000401 000402 -- rblk (131,00027) a=0006(c0.mem ) n= 3> 2! s=01000001| OK 0: 000401! 000402! ++ wreg (272,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (250,00017) a=4004(i0.im.addr ) d=000024! s=00000000! OK -- wreg (302,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (141,00007) a=4005(i0.im.data ) n= 20= 20 s=00000000! OK 0: 170007! 000401! 003031- 011000! 170007! 000402! 000006- 011000! 8: 150007! 000401! 000050- 010000! 150007! 000402! 000006- 010000! 16: 150007! 050314- 000006- 020000! -- rreg (260,00027) a=4004(i0.im.addr ) d=000024! s=00000000! OK # B2: fifo write test (write 16, read 15) ------------ ++ wreg (312,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (322,00017) a=4800(i0.it.cntl ) d=100006 s=00000000! OK -- wblk (243,00007) a=0006(c0.mem ) n= 16> 15! s=01000001| OK 0: 001000 001001 001002 001003 001004 001005 001006 001007 8: 001010 001011 001012 001013 001014 001015 001016 001017 -- rblk (151,00027) a=4803(i0.it.fifo ) n= 15= 15 s=00000000! OK 0: 001000! 001001! 001002! 001003! 001004! 001005! 001006! 001007! 8: 001010! 001011! 001012! 001013! 001014! 001015! 001016! ++ wreg (332,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (270,00017) a=4004(i0.im.addr ) d=000174! s=00000000! OK -- wreg (342,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (161,00007) a=4005(i0.im.data ) n= 124= 124 s=00000000! OK 0: 150007! 001000! 002353- 011000! 150007! 001001! 000006- 011000! 8: 150007! 001002! 000006- 011000! 150007! 001003! 000006- 011000! 16: 150007! 001004! 000006- 011000! 150007! 001005! 000006- 011000! 24: 150007! 001006! 000006- 011000! 150007! 001007! 000006- 011000! 32: 150007! 001010! 000006- 011000! 150007! 001011! 000006- 011000! 40: 150007! 001012! 000006- 011000! 150007! 001013! 000006- 011000! 48: 150007! 001014! 000006- 011000! 150007! 001015! 000006- 011000! 56: 150007! 001016! 000006- 011000! 150007! 001017! 000006- 021000! 64: 170007! 001000! 000030- 010000! 170007! 001001! 000006- 010000! 72: 170007! 001002! 000006- 010000! 170007! 001003! 000006- 010000! 80: 170007! 001004! 000006- 010000! 170007! 001005! 000006- 010000! 88: 170007! 001006! 000006- 010000! 170007! 001007! 000006- 010000! 96: 170007! 001010! 000006- 010000! 170007! 001011! 000006- 010000! 104: 170007! 001012! 000006- 010000! 170007! 001013! 000006- 010000! 112: 170007! 001014! 000006- 010000! 170007! 001015! 000006- 010000! 120: 170007! 001016! 000006- 010000! -- rreg (300,00027) a=4004(i0.im.addr ) d=000174! s=00000000! OK # C test repeat collapes ------------------------------------ # C1: dry run, no collapse active -------------------- ++ wreg (352,00037) a=4000(i0.im.cntl ) d=000075 s=00000000! OK ++ wreg (362,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wblk (253,00007) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 001400 001401 001402 001403 -- rblk (171,00027) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 001400! 001401! 001402! 001403! ++ wreg (372,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (310,00017) a=4004(i0.im.addr ) d=000040! s=00000000! OK -- wreg (002,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (201,00007) a=4005(i0.im.data ) n= 32= 32 s=00000000! OK 0: 170007! 001400! 005051- 011000! 170007! 001401! 000006- 011000! 8: 170007! 001402! 000006- 011000! 170007! 001403! 000006- 011000! 16: 170007! 001400! 000036- 010000! 170007! 001401! 000006- 010000! 24: 170007! 001402! 000006- 010000! 170007! 001403! 000006- 010000! -- rreg (320,00027) a=4004(i0.im.addr ) d=000040! s=00000000! OK # C2.1: read collapse active ------------------------- ++ wreg (012,00037) a=4000(i0.im.cntl ) d=000275 s=00000000! OK ++ wreg (022,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wblk (263,00007) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 002000 002001 002002 002003 -- rblk (211,00027) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 002000! 002001! 002002! 002003! ++ wreg (032,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (330,00017) a=4004(i0.im.addr ) d=000030! s=00000000! OK -- wreg (042,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (221,00007) a=4005(i0.im.data ) n= 24= 24 s=00000000! OK 0: 170007! 002000! 002361- 011000! 170007! 002001! 000006- 011000! 8: 170007! 002002! 000006- 011000! 170007! 002003! 000006- 011000! 16: 170007! 002000! 000030- 010000! 170007! 002003! 000006- 010000! -- rreg (340,00027) a=4004(i0.im.addr ) d=000030! s=00000000! OK # C2.2: write collapse active ------------------------ ++ wreg (052,00037) a=4000(i0.im.cntl ) d=000475 s=00000000! OK ++ wreg (062,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wblk (273,00007) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 002400 002401 002402 002403 -- rblk (231,00027) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 002400! 002401! 002402! 002403! ++ wreg (072,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (350,00017) a=4004(i0.im.addr ) d=000030! s=00000000! OK -- wreg (102,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (241,00007) a=4005(i0.im.data ) n= 24= 24 s=00000000! OK 0: 170007! 002400! 002201- 011000! 170007! 002403! 000006- 011000! 8: 170007! 002400! 000030- 010000! 170007! 002401! 000006- 010000! 16: 170007! 002402! 000006- 010000! 170007! 002403! 000006- 010000! -- rreg (360,00027) a=4004(i0.im.addr ) d=000030! s=00000000! OK # C2.3: read and write collapse active --------------- ++ wreg (112,00037) a=4000(i0.im.cntl ) d=000675 s=00000000! OK ++ wreg (122,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wblk (303,00007) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 003000 003001 003002 003003 -- rblk (251,00027) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 003000! 003001! 003002! 003003! ++ wreg (132,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (370,00017) a=4004(i0.im.addr ) d=000020! s=00000000! OK -- wreg (142,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (261,00007) a=4005(i0.im.data ) n= 16= 16 s=00000000! OK 0: 170007! 003000! 002201- 011000! 170007! 003003! 000006- 011000! 8: 170007! 003000! 000030- 010000! 170007! 003003! 000006- 010000! -- rreg (000,00027) a=4004(i0.im.addr ) d=000020! s=00000000! OK # C2.4: non-collapse of write-read same address ------ ++ wreg (152,00037) a=4000(i0.im.cntl ) d=000675 s=00000000! OK ++ wreg (162,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wreg (172,00007) a=4803(i0.it.fifo ) d=003400 s=00000000! OK -- rreg (010,00007) a=4803(i0.it.fifo ) d=003400! s=00000000! OK -- wreg (202,00007) a=4803(i0.it.fifo ) d=003401 s=00000000! OK -- rreg (020,00007) a=4803(i0.it.fifo ) d=003401! s=00000000! OK -- wreg (212,00007) a=4803(i0.it.fifo ) d=003402 s=00000000! OK -- rreg (030,00007) a=4803(i0.it.fifo ) d=003402! s=00000000! OK -- wreg (222,00007) a=4803(i0.it.fifo ) d=003403 s=00000000! OK -- rreg (040,00027) a=4803(i0.it.fifo ) d=003403! s=00000000! OK ++ wreg (232,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (050,00017) a=4004(i0.im.addr ) d=000040! s=00000000! OK -- wreg (242,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (271,00007) a=4005(i0.im.data ) n= 32= 32 s=00000000! OK 0: 170007! 003400! 001717- 011000! 170007! 003400! 000041- 010000! 8: 170007! 003401! 000055- 011000! 170007! 003401! 000042- 010000! 16: 170007! 003402! 000055- 011000! 170007! 003402! 000041- 010000! 24: 170007! 003403! 000055- 011000! 170007! 003403! 000042- 010000! -- rreg (060,00027) a=4004(i0.im.addr ) d=000040! s=00000000! OK # C2.5: non-collapse of reads to different address --- ++ wreg (252,00037) a=4000(i0.im.cntl ) d=000675 s=00000000! OK ++ wreg (262,00017) a=4800(i0.it.cntl ) d=100014 s=00000000! OK -- wreg (272,00007) a=4802(i0.it.data ) d=135276 s=00000000! OK -- wblk (313,00007) a=4803(i0.it.fifo ) n= 4= 4 s=00000000! OK 0: 004000 004001 004002 004003 -- rreg (070,00007) a=4803(i0.it.fifo ) d=004000! s=00000000! OK -- rreg (100,00007) a=4802(i0.it.data ) d=135276! s=00000000! OK -- rreg (110,00007) a=4803(i0.it.fifo ) d=004001! s=00000000! OK -- rreg (120,00007) a=4802(i0.it.data ) d=135276! s=00000000! OK -- rreg (130,00007) a=4803(i0.it.fifo ) d=004002! s=00000000! OK -- rreg (140,00007) a=4802(i0.it.data ) d=135276! s=00000000! OK -- rreg (150,00007) a=4803(i0.it.fifo ) d=004003! s=00000000! OK -- rreg (160,00027) a=4802(i0.it.data ) d=135276! s=00000000! OK ++ wreg (302,00037) a=4000(i0.im.cntl ) d=000004 s=00000000! OK ++ rreg (170,00017) a=4004(i0.im.addr ) d=000054! s=00000000! OK -- wreg (312,00007) a=4004(i0.im.addr ) d=000000 s=00000000! OK -- rblk (301,00007) a=4005(i0.im.data ) n= 44= 44 s=00000000! OK 0: 170005! 135276! 002157- 011000! 170007! 004000! 000165- 011000! 8: 170007! 004003! 000006- 011000! 170007! 004000! 000024- 010000! 16: 170005! 135276! 000024- 010000! 170007! 004001! 000040- 010000! 24: 170005! 135276! 000040- 010000! 170007! 004002! 000041- 010000! 32: 170005! 135276! 000040- 010000! 170007! 004003! 000040- 010000! 40: 170005! 135276! 000041- 010000! -- rreg (200,00027) a=4004(i0.im.addr ) d=000054! s=00000000! OK test_ibmon_ibtst.tcl: PASS @w11a_ibmon/w11a_ibmon_all.dat: PASS ## steering file for all w11a tests # test_w11a_sdreg: test switch and display register access ------------- ++ wreg (322,00017) a=0004(c0.al ) d=177570 s=00000000! OK -- wreg (332,00007) a=0006(c0.mem ) d=125252 s=00000000! OK -- wreg (342,00007) a=4fbc(i0.sdreg ) d=052525 s=00000000! OK -- rreg (210,00007) a=4fbc(i0.sdreg ) d=125252! s=00000000! OK -- rreg (220,00007) a=0006(c0.mem ) d=052525! s=00000000! OK -- wreg (352,00007) a=0006(c0.mem ) d=157255 s=00000000! OK -- wreg (362,00007) a=4fbc(i0.sdreg ) d=137357 s=00000000! OK -- rreg (230,00007) a=4fbc(i0.sdreg ) d=157255! s=00000000! OK -- rreg (240,00007) a=0006(c0.mem ) d=137357! s=00000000! OK -- wreg (372,00007) a=0006(c0.mem ) d=000000 s=00000000! OK -- wreg (002,00007) a=4fbc(i0.sdreg ) d=000000 s=00000000! OK -- rreg (250,00007) a=4fbc(i0.sdreg ) d=000000! s=00000000! OK -- rreg (260,00027) a=0006(c0.mem ) d=000000! s=00000000! OK test_w11a_sdreg.tcl: PASS # test_w11a_mem70: Test 11/70 memory system and cache ------ # access all 11/70 memory system registers ++ wreg (012,00017) a=0004(c0.al ) d=177740 s=00000000! OK -- rreg (270,00007) a=0007(c0.memi ) d=000000! s=00000000! OK -- rreg (300,00007) a=0007(c0.memi ) d=000000! s=00000000! OK -- rreg (310,00007) a=0007(c0.memi ) d=000000! s=00000000! OK -- rreg (320,00007) a=0007(c0.memi ) d=000000! s=00000000! OK -- rreg (330,00007) a=0007(c0.memi ) d=000000! s=00000000! OK -- rreg (340,00007) a=0007(c0.memi ) d=000067 s=00000000! OK -- wreg (022,00007) a=0004(c0.al ) d=177760 s=00000000! OK -- rreg (350,00007) a=0007(c0.memi ) d=167777 s=00000000! OK -- rreg (360,00027) a=0007(c0.memi ) d=000000! s=00000000! OK # --> detected memory size: 3840 kB # Test 1: cache basic rmiss test - is data from mem on rmiss ? ++ wreg (032,00017) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (042,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- wblk (323,00007) a=0007(c0.memi ) n= 8= 8 s=00000000! OK 0: 000000 000002 000004 000006 000010 000012 000014 000016 -- wreg (052,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (062,00007) a=0005(c0.ah ) d=000102 s=00000000! OK -- wblk (333,00027) a=0007(c0.memi ) n= 8= 8 s=00000000! OK 0: 020000 020002 020004 020006 020010 020012 020014 020016 ++ wreg (072,00017) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (102,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rblk (311,00007) a=0007(c0.memi ) n= 8= 8 s=00000000! OK 0: 000000! 000002! 000004! 000006! 000010! 000012! 000014! 000016! -- wreg (112,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (122,00007) a=0005(c0.ah ) d=000102 s=00000000! OK -- rblk (321,00027) a=0007(c0.memi ) n= 8= 8 s=00000000! OK 0: 020000! 020002! 020004! 020006! 020010! 020012! 020014! 020016! # Test 2: Hit/Miss register ++ wreg (132,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wreg (142,00007) a=0005(c0.ah ) d=000102 s=00000000! OK -- rreg (370,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (000,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (010,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (020,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (030,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (040,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- rreg (050,00007) a=0006(c0.mem ) d=020004! s=00000000! OK -- wreg (152,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (060,00027) a=0006(c0.mem ) d=000077! s=00000000! OK ++ wreg (162,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wreg (172,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rreg (070,00007) a=0006(c0.mem ) d=000004! s=00000000! OK -- wreg (202,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (100,00007) a=0006(c0.mem ) d=000076! s=00000000! OK -- wreg (212,00007) a=0004(c0.al ) d=000006 s=00000000! OK -- wreg (222,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rreg (110,00007) a=0006(c0.mem ) d=000006! s=00000000! OK -- wreg (232,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (120,00007) a=0006(c0.mem ) d=000075! s=00000000! OK -- wreg (242,00007) a=0004(c0.al ) d=000010 s=00000000! OK -- wreg (252,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rreg (130,00007) a=0007(c0.memi ) d=000010! s=00000000! OK -- rreg (140,00007) a=0007(c0.memi ) d=000012! s=00000000! OK -- rreg (150,00007) a=0007(c0.memi ) d=000014! s=00000000! OK -- rreg (160,00007) a=0007(c0.memi ) d=000016! s=00000000! OK -- wreg (262,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (170,00027) a=0006(c0.mem ) d=000025! s=00000000! OK ++ wreg (272,00017) a=0004(c0.al ) d=000020 s=00000000! OK -- wreg (302,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- wblk (343,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000020 000022 000024 000026 -- wreg (312,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (200,00007) a=0006(c0.mem ) d=000020! s=00000000! OK -- wreg (322,00007) a=0004(c0.al ) d=000020 s=00000000! OK -- wreg (332,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rblk (331,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000020! 000022! 000024! 000026! -- wreg (342,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (210,00027) a=0006(c0.mem ) d=000017! s=00000000! OK # Test 3: Control Register: test force miss bits ++ wreg (352,00017) a=0004(c0.al ) d=177746 s=00000000! OK -- wreg (362,00007) a=0006(c0.mem ) d=000014 s=00000000! OK -- wreg (372,00007) a=0004(c0.al ) d=000020 s=00000000! OK -- wreg (002,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rblk (341,00007) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000020! 000022! 000024! 000026! -- wreg (012,00007) a=0004(c0.al ) d=177752 s=00000000! OK -- rreg (220,00007) a=0006(c0.mem ) d=000060! s=00000000! OK -- wreg (022,00007) a=0004(c0.al ) d=177746 s=00000000! OK -- wreg (032,00027) a=0006(c0.mem ) d=000000 s=00000000! OK # Test 4: test full memory (touch (4-7)*2 sections of 16 words # --> 7 chuncks with 512 kB ++ wreg (042,00017) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (052,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- wblk (353,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000000 000010 000020 000030 000040 000050 000060 000070 8: 000100 000110 000120 000130 000140 000150 000160 000170 -- wreg (062,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (072,00007) a=0005(c0.ah ) d=000107 s=00000000! OK -- wblk (363,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000001 000011 000021 000031 000041 000051 000061 000071 8: 000101 000111 000121 000131 000141 000151 000161 000171 -- wreg (102,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (112,00007) a=0005(c0.ah ) d=000110 s=00000000! OK -- wblk (373,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 001000 001010 001020 001030 001040 001050 001060 001070 8: 001100 001110 001120 001130 001140 001150 001160 001170 -- wreg (122,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (132,00007) a=0005(c0.ah ) d=000117 s=00000000! OK -- wblk (003,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 001001 001011 001021 001031 001041 001051 001061 001071 8: 001101 001111 001121 001131 001141 001151 001161 001171 -- wreg (142,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (152,00007) a=0005(c0.ah ) d=000120 s=00000000! OK -- wblk (013,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 002000 002010 002020 002030 002040 002050 002060 002070 8: 002100 002110 002120 002130 002140 002150 002160 002170 -- wreg (162,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (172,00007) a=0005(c0.ah ) d=000127 s=00000000! OK -- wblk (023,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 002001 002011 002021 002031 002041 002051 002061 002071 8: 002101 002111 002121 002131 002141 002151 002161 002171 -- wreg (202,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (212,00007) a=0005(c0.ah ) d=000130 s=00000000! OK -- wblk (033,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 003000 003010 003020 003030 003040 003050 003060 003070 8: 003100 003110 003120 003130 003140 003150 003160 003170 -- wreg (222,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (232,00007) a=0005(c0.ah ) d=000137 s=00000000! OK -- wblk (043,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 003001 003011 003021 003031 003041 003051 003061 003071 8: 003101 003111 003121 003131 003141 003151 003161 003171 -- wreg (242,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (252,00007) a=0005(c0.ah ) d=000140 s=00000000! OK -- wblk (053,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 004000 004010 004020 004030 004040 004050 004060 004070 8: 004100 004110 004120 004130 004140 004150 004160 004170 -- wreg (262,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (272,00007) a=0005(c0.ah ) d=000147 s=00000000! OK -- wblk (063,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 004001 004011 004021 004031 004041 004051 004061 004071 8: 004101 004111 004121 004131 004141 004151 004161 004171 -- wreg (302,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (312,00007) a=0005(c0.ah ) d=000150 s=00000000! OK -- wblk (073,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 005000 005010 005020 005030 005040 005050 005060 005070 8: 005100 005110 005120 005130 005140 005150 005160 005170 -- wreg (322,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (332,00007) a=0005(c0.ah ) d=000157 s=00000000! OK -- wblk (103,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 005001 005011 005021 005031 005041 005051 005061 005071 8: 005101 005111 005121 005131 005141 005151 005161 005171 -- wreg (342,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (352,00007) a=0005(c0.ah ) d=000160 s=00000000! OK -- wblk (113,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 006000 006010 006020 006030 006040 006050 006060 006070 8: 006100 006110 006120 006130 006140 006150 006160 006170 -- wreg (362,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (372,00007) a=0005(c0.ah ) d=000167 s=00000000! OK -- wblk (123,00027) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 006001 006011 006021 006031 006041 006051 006061 006071 8: 006101 006111 006121 006131 006141 006151 006161 006171 ++ wreg (002,00017) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (012,00007) a=0005(c0.ah ) d=000100 s=00000000! OK -- rblk (351,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000000! 000010! 000020! 000030! 000040! 000050! 000060! 000070! 8: 000100! 000110! 000120! 000130! 000140! 000150! 000160! 000170! -- wreg (022,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (032,00007) a=0005(c0.ah ) d=000107 s=00000000! OK -- rblk (361,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000001! 000011! 000021! 000031! 000041! 000051! 000061! 000071! 8: 000101! 000111! 000121! 000131! 000141! 000151! 000161! 000171! -- wreg (042,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (052,00007) a=0005(c0.ah ) d=000110 s=00000000! OK -- rblk (371,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 001000! 001010! 001020! 001030! 001040! 001050! 001060! 001070! 8: 001100! 001110! 001120! 001130! 001140! 001150! 001160! 001170! -- wreg (062,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (072,00007) a=0005(c0.ah ) d=000117 s=00000000! OK -- rblk (001,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 001001! 001011! 001021! 001031! 001041! 001051! 001061! 001071! 8: 001101! 001111! 001121! 001131! 001141! 001151! 001161! 001171! -- wreg (102,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (112,00007) a=0005(c0.ah ) d=000120 s=00000000! OK -- rblk (011,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 002000! 002010! 002020! 002030! 002040! 002050! 002060! 002070! 8: 002100! 002110! 002120! 002130! 002140! 002150! 002160! 002170! -- wreg (122,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (132,00007) a=0005(c0.ah ) d=000127 s=00000000! OK -- rblk (021,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 002001! 002011! 002021! 002031! 002041! 002051! 002061! 002071! 8: 002101! 002111! 002121! 002131! 002141! 002151! 002161! 002171! -- wreg (142,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (152,00007) a=0005(c0.ah ) d=000130 s=00000000! OK -- rblk (031,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 003000! 003010! 003020! 003030! 003040! 003050! 003060! 003070! 8: 003100! 003110! 003120! 003130! 003140! 003150! 003160! 003170! -- wreg (162,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (172,00007) a=0005(c0.ah ) d=000137 s=00000000! OK -- rblk (041,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 003001! 003011! 003021! 003031! 003041! 003051! 003061! 003071! 8: 003101! 003111! 003121! 003131! 003141! 003151! 003161! 003171! -- wreg (202,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (212,00007) a=0005(c0.ah ) d=000140 s=00000000! OK -- rblk (051,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 004000! 004010! 004020! 004030! 004040! 004050! 004060! 004070! 8: 004100! 004110! 004120! 004130! 004140! 004150! 004160! 004170! -- wreg (222,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (232,00007) a=0005(c0.ah ) d=000147 s=00000000! OK -- rblk (061,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 004001! 004011! 004021! 004031! 004041! 004051! 004061! 004071! 8: 004101! 004111! 004121! 004131! 004141! 004151! 004161! 004171! -- wreg (242,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (252,00007) a=0005(c0.ah ) d=000150 s=00000000! OK -- rblk (071,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 005000! 005010! 005020! 005030! 005040! 005050! 005060! 005070! 8: 005100! 005110! 005120! 005130! 005140! 005150! 005160! 005170! -- wreg (262,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (272,00007) a=0005(c0.ah ) d=000157 s=00000000! OK -- rblk (101,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 005001! 005011! 005021! 005031! 005041! 005051! 005061! 005071! 8: 005101! 005111! 005121! 005131! 005141! 005151! 005161! 005171! -- wreg (302,00007) a=0004(c0.al ) d=000000 s=00000000! OK -- wreg (312,00007) a=0005(c0.ah ) d=000160 s=00000000! OK -- rblk (111,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 006000! 006010! 006020! 006030! 006040! 006050! 006060! 006070! 8: 006100! 006110! 006120! 006130! 006140! 006150! 006160! 006170! -- wreg (322,00007) a=0004(c0.al ) d=177740 s=00000000! OK -- wreg (332,00007) a=0005(c0.ah ) d=000167 s=00000000! OK -- rblk (121,00027) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 006001! 006011! 006021! 006031! 006041! 006051! 006061! 006071! 8: 006101! 006111! 006121! 006131! 006141! 006151! 006161! 006171! test_w11a_mem70.tcl: PASS # test_w11a_srcr_word_flow: test srcr flow for word with mov ...,rx # r0 (mode=0) ++ wreg (342,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (133,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 010001 010602 010703 000000 ++ wreg (352,00017) a=0008(c0.r0 ) d=001234 s=00000000! OK -- wreg (362,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (372,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (012,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (042,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (052,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (062,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (072,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:49.695836 : ATTN notify apat = 0001 lams = 0 dt=9.237218 ++ attn (105,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (230,00037) a=000f(c0.pc ) d=001010! s=00000000! OK ++ rreg (240,00017) a=0008(c0.r0 ) d=001234! s=00000000! OK -- rreg (250,00007) a=0009(c0.r1 ) d=001234! s=00000000! OK -- rreg (260,00007) a=000a(c0.r2 ) d=001000! s=00000000! OK -- rreg (270,00007) a=000b(c0.r3 ) d=001006! s=00000000! OK -- rreg (300,00007) a=000c(c0.r4 ) d=000000! s=00000000! OK -- rreg (310,00007) a=000d(c0.r5 ) d=000000! s=00000000! OK -- rreg (320,00027) a=000e(c0.sp ) d=001000! s=00000000! OK # (r0),(r0)+,-(r0) (mode=1,2,4) ++ wreg (102,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (143,00027) a=0007(c0.memi ) n= 8= 8 s=00000000! OK 0: 011001 012002 012003 014004 014005 000000 001001 001002 ++ wreg (112,00017) a=0008(c0.r0 ) d=001014 s=00000000! OK -- wreg (122,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (202,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (212,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (222,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (232,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:50.048925 : ATTN notify apat = 0001 lams = 0 dt=0.353089 ++ attn (115,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (330,00037) a=000f(c0.pc ) d=001014! s=00000000! OK ++ rreg (340,00017) a=0008(c0.r0 ) d=001014! s=00000000! OK -- rreg (350,00007) a=0009(c0.r1 ) d=001001! s=00000000! OK -- rreg (360,00007) a=000a(c0.r2 ) d=001001! s=00000000! OK -- rreg (370,00007) a=000b(c0.r3 ) d=001002! s=00000000! OK -- rreg (000,00007) a=000c(c0.r4 ) d=001002! s=00000000! OK -- rreg (010,00027) a=000d(c0.r5 ) d=001001! s=00000000! OK # @(r0)+,@-(r0) (mode=3,5) ++ wreg (242,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (153,00027) a=0007(c0.memi ) n= 11= 11 s=00000000! OK 0: 013001 013002 010003 015004 015005 000000 001020 001024 8: 002001 000000 002002 ++ wreg (252,00017) a=0008(c0.r0 ) d=001014 s=00000000! OK -- wreg (262,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (342,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (362,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (372,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:50.407796 : ATTN notify apat = 0001 lams = 0 dt=0.358871 ++ attn (125,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (020,00037) a=000f(c0.pc ) d=001014! s=00000000! OK ++ rreg (030,00017) a=0008(c0.r0 ) d=001014! s=00000000! OK -- rreg (040,00007) a=0009(c0.r1 ) d=002001! s=00000000! OK -- rreg (050,00007) a=000a(c0.r2 ) d=002002! s=00000000! OK -- rreg (060,00007) a=000b(c0.r3 ) d=001020! s=00000000! OK -- rreg (070,00007) a=000c(c0.r4 ) d=002002! s=00000000! OK -- rreg (100,00027) a=000d(c0.r5 ) d=002001! s=00000000! OK # nn(r0),@nn(r0) (mode=6,7) ++ wreg (002,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (163,00027) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 016001 000002 017002 000004 016003 000006 017004 000010 8: 000000 177777 003001 001034 003003 001036 003002 003004 ++ wreg (012,00017) a=0008(c0.r0 ) d=001022 s=00000000! OK -- wreg (022,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (072,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (102,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (112,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (122,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (132,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:50.785631 : ATTN notify apat = 0001 lams = 0 dt=0.377834 ++ attn (135,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.010 OK ++ rreg (110,00037) a=000f(c0.pc ) d=001022! s=00000000! OK ++ rreg (120,00017) a=0008(c0.r0 ) d=001022! s=00000000! OK -- rreg (130,00007) a=0009(c0.r1 ) d=003001! s=00000000! OK -- rreg (140,00007) a=000a(c0.r2 ) d=003002! s=00000000! OK -- rreg (150,00007) a=000b(c0.r3 ) d=003003! s=00000000! OK -- rreg (160,00007) a=000c(c0.r4 ) d=003004! s=00000000! OK -- rreg (170,00027) a=000d(c0.r5 ) d=000000! s=00000000! OK # #nn,@#nn,var,@var (mode=27,37,67,77) ++ wreg (142,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (173,00027) a=0007(c0.memi ) n= 13= 13 s=00000000! OK 0: 012701 004001 013702 001024 016703 000012 017704 000002 8: 000000 001030 004002 004003 004004 ++ wreg (152,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (162,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (202,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (222,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (242,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (252,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (262,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (272,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:51.149409 : ATTN notify apat = 0001 lams = 0 dt=0.363779 ++ attn (145,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (200,00037) a=000f(c0.pc ) d=001022! s=00000000! OK ++ rreg (210,00017) a=0008(c0.r0 ) d=000000! s=00000000! OK -- rreg (220,00007) a=0009(c0.r1 ) d=004001! s=00000000! OK -- rreg (230,00007) a=000a(c0.r2 ) d=004002! s=00000000! OK -- rreg (240,00007) a=000b(c0.r3 ) d=004003! s=00000000! OK -- rreg (250,00007) a=000c(c0.r4 ) d=004004! s=00000000! OK -- rreg (260,00027) a=000d(c0.r5 ) d=000000! s=00000000! OK test_w11a_srcr_word_flow.tcl: PASS # test_w11a_dstw_word_flow: test dstw flow for word with mov #nnn,... # r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5) ++ wreg (302,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (203,00027) a=0007(c0.memi ) n= 34= 34 s=00000000! OK 0: 012700 000100 012711 000110 012722 000120 012722 000121 8: 012733 000130 012733 000131 012744 000141 012744 000140 16: 012755 000151 012755 000150 000000 000000 000000 000000 24: 000000 000000 000000 000000 000000 000000 001060 001062 32: 001070 001072 ++ wreg (312,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (322,00007) a=0009(c0.r1 ) d=001052 s=00000000! OK -- wreg (332,00007) a=000a(c0.r2 ) d=001054 s=00000000! OK -- wreg (342,00007) a=000b(c0.r3 ) d=001074 s=00000000! OK -- wreg (352,00007) a=000c(c0.r4 ) d=001070 s=00000000! OK -- wreg (362,00007) a=000d(c0.r5 ) d=001104 s=00000000! OK -- wreg (372,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (002,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (012,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (022,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (032,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:51.616895 : ATTN notify apat = 0001 lams = 0 dt=0.467485 ++ attn (155,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.026 OK ++ rreg (270,00037) a=000f(c0.pc ) d=001052! s=00000000! OK ++ rreg (300,00017) a=0008(c0.r0 ) d=000100! s=00000000! OK -- rreg (310,00007) a=0009(c0.r1 ) d=001052! s=00000000! OK -- rreg (320,00007) a=000a(c0.r2 ) d=001060! s=00000000! OK -- rreg (330,00007) a=000b(c0.r3 ) d=001100! s=00000000! OK -- rreg (340,00007) a=000c(c0.r4 ) d=001064! s=00000000! OK -- rreg (350,00027) a=000d(c0.r5 ) d=001100! s=00000000! OK ++ wreg (042,00017) a=0004(c0.al ) d=001052 s=00000000! OK -- rblk (131,00027) a=0007(c0.memi ) n= 9= 9 s=00000000! OK 0: 000110! 000120! 000121! 000130! 000131! 000140! 000141! 000150! 8: 000151! # nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37) ++ wreg (052,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (213,00027) a=0007(c0.memi ) n= 23= 23 s=00000000! OK 0: 012760 000200 000020 012771 000210 000040 012767 000220 8: 000022 012777 000230 000024 012737 000240 001050 000000 16: 000000 000000 000000 000000 000000 001042 001046 ++ wreg (062,00017) a=0008(c0.r0 ) d=001020 s=00000000! OK -- wreg (072,00007) a=0009(c0.r1 ) d=001012 s=00000000! OK -- wreg (102,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (112,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (122,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (152,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (162,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (172,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (202,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:52.094742 : ATTN notify apat = 0001 lams = 0 dt=0.477849 ++ attn (165,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.015 OK ++ rreg (360,00037) a=000f(c0.pc ) d=001040! s=00000000! OK ++ rreg (370,00017) a=0008(c0.r0 ) d=001020! s=00000000! OK -- rreg (000,00007) a=0009(c0.r1 ) d=001012! s=00000000! OK -- rreg (010,00007) a=000a(c0.r2 ) d=000000! s=00000000! OK -- rreg (020,00007) a=000b(c0.r3 ) d=000000! s=00000000! OK -- rreg (030,00007) a=000c(c0.r4 ) d=000000! s=00000000! OK -- rreg (040,00027) a=000d(c0.r5 ) d=000000! s=00000000! OK ++ wreg (212,00017) a=0004(c0.al ) d=001040 s=00000000! OK -- rblk (141,00027) a=0007(c0.memi ) n= 5= 5 s=00000000! OK 0: 000200! 000210! 000220! 000230! 000240! test_w11a_dstw_word_flow.tcl: PASS # test_w11a_dstr_word_flow: test dstr flow for word with inc ... # r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5) ++ wreg (222,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (223,00027) a=0007(c0.memi ) n= 24= 24 s=00000000! OK 0: 005200 005211 005222 005222 005233 005233 005244 005244 8: 005255 005255 000000 000020 000030 000031 000040 000041 16: 000050 000051 000060 000061 001034 001036 001044 001046 ++ wreg (232,00017) a=0008(c0.r0 ) d=000010 s=00000000! OK -- wreg (242,00007) a=0009(c0.r1 ) d=001026 s=00000000! OK -- wreg (252,00007) a=000a(c0.r2 ) d=001030 s=00000000! OK -- wreg (262,00007) a=000b(c0.r3 ) d=001050 s=00000000! OK -- wreg (272,00007) a=000c(c0.r4 ) d=001044 s=00000000! OK -- wreg (302,00007) a=000d(c0.r5 ) d=001060 s=00000000! OK -- wreg (312,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (342,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (352,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:52.572744 : ATTN notify apat = 0001 lams = 0 dt=0.478001 ++ attn (175,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.025 OK ++ rreg (050,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ rreg (060,00017) a=0008(c0.r0 ) d=000011! s=00000000! OK -- rreg (070,00007) a=0009(c0.r1 ) d=001026! s=00000000! OK -- rreg (100,00007) a=000a(c0.r2 ) d=001034! s=00000000! OK -- rreg (110,00007) a=000b(c0.r3 ) d=001054! s=00000000! OK -- rreg (120,00007) a=000c(c0.r4 ) d=001040! s=00000000! OK -- rreg (130,00027) a=000d(c0.r5 ) d=001054! s=00000000! OK ++ wreg (362,00017) a=0004(c0.al ) d=001026 s=00000000! OK -- rblk (151,00027) a=0007(c0.memi ) n= 9= 9 s=00000000! OK 0: 000021! 000031! 000032! 000041! 000042! 000051! 000052! 000061! 8: 000062! # nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37) ++ wreg (372,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (233,00027) a=0007(c0.memi ) n= 18= 18 s=00000000! OK 0: 005260 000020 005271 000040 005267 000016 005277 000022 8: 005237 001036 000000 000200 000210 000220 000230 000240 16: 001030 001034 ++ wreg (002,00017) a=0008(c0.r0 ) d=001006 s=00000000! OK -- wreg (012,00007) a=0009(c0.r1 ) d=001000 s=00000000! OK -- wreg (022,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (072,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (102,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (112,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (122,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:53.030754 : ATTN notify apat = 0001 lams = 0 dt=0.458010 ++ attn (205,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.015 OK ++ rreg (140,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ rreg (150,00017) a=0008(c0.r0 ) d=001006! s=00000000! OK -- rreg (160,00007) a=0009(c0.r1 ) d=001000! s=00000000! OK -- rreg (170,00007) a=000a(c0.r2 ) d=000000! s=00000000! OK -- rreg (200,00007) a=000b(c0.r3 ) d=000000! s=00000000! OK -- rreg (210,00007) a=000c(c0.r4 ) d=000000! s=00000000! OK -- rreg (220,00027) a=000d(c0.r5 ) d=000000! s=00000000! OK ++ wreg (132,00017) a=0004(c0.al ) d=001026 s=00000000! OK -- rblk (161,00027) a=0007(c0.memi ) n= 5= 5 s=00000000! OK 0: 000201! 000211! 000221! 000231! 000241! test_w11a_dstr_word_flow.tcl: PASS # test_w11a_dsta_flow: test dsta flow with jsr pc,... # (r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=1,2,3,4,5) ++ wreg (142,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (243,00027) a=0007(c0.memi ) n= 40= 40 s=00000000! OK 0: 004710 004721 004732 004732 004743 004754 004754 000000 8: 001050 001060 001110 001100 012725 000100 011625 000207 16: 012725 000110 011625 000207 012725 000120 011625 000207 24: 012725 000121 011625 000207 012725 000130 011625 000207 32: 012725 000140 011625 000207 012725 000141 011625 000207 ++ wreg (152,00017) a=0004(c0.al ) d=001154 s=00000000! OK -- wblk (253,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 177777 ++ wreg (162,00017) a=0008(c0.r0 ) d=001030 s=00000000! OK -- wreg (172,00007) a=0009(c0.r1 ) d=001040 s=00000000! OK -- wreg (202,00007) a=000a(c0.r2 ) d=001020 s=00000000! OK -- wreg (212,00007) a=000b(c0.r3 ) d=001072 s=00000000! OK -- wreg (222,00007) a=000c(c0.r4 ) d=001030 s=00000000! OK -- wreg (232,00007) a=000d(c0.r5 ) d=001120 s=00000000! OK -- wreg (242,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (252,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (262,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (272,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (302,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:53.672350 : ATTN notify apat = 0001 lams = 0 dt=0.641594 ++ attn (215,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.073 OK ++ rreg (230,00037) a=000f(c0.pc ) d=001020! s=00000000! OK ++ rreg (240,00017) a=0008(c0.r0 ) d=001030! s=00000000! OK -- rreg (250,00007) a=0009(c0.r1 ) d=001042! s=00000000! OK -- rreg (260,00007) a=000a(c0.r2 ) d=001024! s=00000000! OK -- rreg (270,00007) a=000b(c0.r3 ) d=001070! s=00000000! OK -- rreg (300,00007) a=000c(c0.r4 ) d=001024! s=00000000! OK -- rreg (310,00007) a=000d(c0.r5 ) d=001154! s=00000000! OK -- rreg (320,00027) a=000e(c0.sp ) d=001000! s=00000000! OK ++ wreg (312,00017) a=0004(c0.al ) d=001120 s=00000000! OK -- rblk (171,00027) a=0007(c0.memi ) n= 15= 15 s=00000000! OK 0: 000100! 001002! 000110! 001004! 000120! 001006! 000121! 001010! 8: 000130! 001012! 000140! 001014! 000141! 001016! 177777! # nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37) ++ wreg (322,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (263,00027) a=0007(c0.memi ) n= 33= 33 s=00000000! OK 0: 004760 000020 004771 000040 004767 000036 004777 000010 8: 004737 001072 000000 001042 001062 012725 001100 011625 16: 000207 012725 001110 011625 000207 012725 001120 011625 24: 000207 012725 001130 011625 000207 012725 001140 011625 32: 000207 ++ wreg (332,00017) a=0004(c0.al ) d=001126 s=00000000! OK -- wblk (273,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 177777 ++ wreg (342,00017) a=0008(c0.r0 ) d=001012 s=00000000! OK -- wreg (352,00007) a=0009(c0.r1 ) d=000766 s=00000000! OK -- wreg (362,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (372,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (012,00007) a=000d(c0.r5 ) d=001102 s=00000000! OK -- wreg (022,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (032,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (042,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (052,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (062,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:54.306369 : ATTN notify apat = 0001 lams = 0 dt=0.634021 ++ attn (225,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.054 OK ++ rreg (330,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ rreg (340,00017) a=0008(c0.r0 ) d=001012! s=00000000! OK -- rreg (350,00007) a=0009(c0.r1 ) d=000766! s=00000000! OK -- rreg (360,00007) a=000a(c0.r2 ) d=000000! s=00000000! OK -- rreg (370,00007) a=000b(c0.r3 ) d=000000! s=00000000! OK -- rreg (000,00007) a=000c(c0.r4 ) d=000000! s=00000000! OK -- rreg (010,00007) a=000d(c0.r5 ) d=001126! s=00000000! OK -- rreg (020,00027) a=000e(c0.sp ) d=001000! s=00000000! OK ++ wreg (072,00017) a=0004(c0.al ) d=001102 s=00000000! OK -- rblk (201,00027) a=0007(c0.memi ) n= 11= 11 s=00000000! OK 0: 001100! 001004! 001110! 001010! 001120! 001014! 001130! 001020! 8: 001140! 001024! 177777! test_w11a_dsta_flow.tcl: PASS # test_w11a_inst_quick: quick instruction test ------------------------ # Word instructions ----------------------------------------- ++ wreg (102,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wblk (303,00027) a=0007(c0.memi ) n= 14= 14 s=00000000! OK 0: 000006 000000 000012 000000 001000 000000 000022 000000 8: 000026 000000 000032 000000 000036 000000 ++ wreg (112,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (313,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 000242 000000 000246 000000 000252 000000 ++ wreg (122,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (323,00027) a=0007(c0.memi ) n= 134= 134 s=00000000! OK 0: 026324 177776 001401 000000 026625 000002 001401 000000 8: 000006 010123 020123 020223 020123 005023 030123 030123 16: 040123 050123 060123 160123 005123 005223 005323 005423 24: 005723 006023 006023 006123 006223 006223 006323 006323 32: 060123 005523 160123 005623 000323 006723 074123 006723 40: 000000 123456 123456 004711 004711 123456 000011 000066 48: 123456 123456 123456 123456 123456 123456 123456 123456 56: 123456 100201 002201 100200 000200 100200 000200 100200 64: 177000 000200 004701 000200 111000 111111 070707 111111 72: 004711 123456 004711 004711 000000 000011 000066 123046 80: 127757 130367 116545 054321 123457 123455 054322 123456 88: 040100 101100 000401 000100 140100 000400 000400 003711 96: 000201 177770 000177 000222 177777 074016 000000 000020 104: 000021 000030 000024 000024 000020 000024 000030 000030 112: 000030 000030 000021 000031 000031 000021 000030 000023 120: 000031 000023 000020 000032 000020 000023 000021 000020 128: 000031 000020 000030 000030 000020 000024 # CRESET ++ wreg (132,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (142,00007) a=0009(c0.r1 ) d=004711 s=00000000! OK -- wreg (152,00007) a=000a(c0.r2 ) d=123456 s=00000000! OK -- wreg (162,00007) a=000b(c0.r3 ) d=001122 s=00000000! OK -- wreg (172,00007) a=000c(c0.r4 ) d=001220 s=00000000! OK -- wreg (202,00007) a=000d(c0.r5 ) d=001316 s=00000000! OK -- wreg (212,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (222,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (232,00007) a=000f(c0.pc ) d=001022 s=00000000! OK -- wreg (242,00007) a=0003(c0.psw ) d=000020 s=00000000! OK -- wreg (252,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:56.013549 : ATTN notify apat = 0001 lams = 0 dt=1.707179 ++ attn (235,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.608 OK ++ rreg (030,00037) a=000f(c0.pc ) d=001122! s=00000000! OK ++ rreg (040,00017) a=0009(c0.r1 ) d=004711! s=00000000! OK -- rreg (050,00007) a=000a(c0.r2 ) d=123456! s=00000000! OK -- rreg (060,00007) a=000b(c0.r3 ) d=001220! s=00000000! OK -- rreg (070,00007) a=000c(c0.r4 ) d=001316! s=00000000! OK -- rreg (100,00007) a=000d(c0.r5 ) d=001414! s=00000000! OK -- rreg (110,00027) a=000e(c0.sp ) d=001000! s=00000000! OK # Byte instructions ----------------------------------------- ++ wreg (262,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wblk (333,00027) a=0007(c0.memi ) n= 14= 14 s=00000000! OK 0: 000006 000000 000012 000000 001000 000000 000022 000000 8: 000026 000000 000032 000000 000036 000000 ++ wreg (272,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (343,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 000242 000000 000246 000000 000252 000000 ++ wreg (302,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (353,00027) a=0007(c0.memi ) n= 74= 74 s=00000000! OK 0: 126324 177777 001401 000000 026625 000002 001401 000000 8: 000006 110123 120123 120223 120123 105023 130123 130123 16: 140123 150123 105123 105223 105323 105423 105723 106023 24: 106023 106123 106223 106223 106323 106323 000000 155733 32: 051511 004733 155444 150511 150721 150721 010601 010210 40: 010220 000220 155523 051511 004400 104044 027133 150322 48: 150457 104100 004021 020310 000040 000020 000021 000030 56: 000024 000024 000020 000024 000030 000020 000021 000031 64: 000031 000021 000030 000023 000031 000023 000020 000032 72: 000020 000023 # CRESET ++ wreg (312,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (322,00007) a=0009(c0.r1 ) d=000123 s=00000000! OK -- wreg (332,00007) a=000a(c0.r2 ) d=000321 s=00000000! OK -- wreg (342,00007) a=000b(c0.r3 ) d=001076 s=00000000! OK -- wreg (352,00007) a=000c(c0.r4 ) d=001124 s=00000000! OK -- wreg (362,00007) a=000d(c0.r5 ) d=001152 s=00000000! OK -- wreg (372,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (002,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (012,00007) a=000f(c0.pc ) d=001022 s=00000000! OK -- wreg (022,00007) a=0003(c0.psw ) d=000020 s=00000000! OK -- wreg (032,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:57.204012 : ATTN notify apat = 0001 lams = 0 dt=1.190461 ++ attn (245,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.411 OK ++ rreg (120,00037) a=000f(c0.pc ) d=001076! s=00000000! OK ++ rreg (130,00017) a=0009(c0.r1 ) d=000123! s=00000000! OK -- rreg (140,00007) a=000a(c0.r2 ) d=000321! s=00000000! OK -- rreg (150,00007) a=000b(c0.r3 ) d=001123! s=00000000! OK -- rreg (160,00007) a=000c(c0.r4 ) d=001151! s=00000000! OK -- rreg (170,00007) a=000d(c0.r5 ) d=001224! s=00000000! OK -- rreg (200,00027) a=000e(c0.sp ) d=001000! s=00000000! OK test_w11a_inst_quick.tcl: PASS # test_w11a_inst_traps: test trap type instructions ------------------- ++ wreg (042,00017) a=0004(c0.al ) d=000014 s=00000000! OK -- wblk (363,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 001062 000340 001074 000341 ++ wreg (052,00017) a=0004(c0.al ) d=000030 s=00000000! OK -- wblk (373,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 001106 000342 001120 000343 ++ wreg (062,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (003,00027) a=0007(c0.memi ) n= 51= 51 s=00000000! OK 0: 012737 000350 177776 000003 012737 000351 177776 000004 8: 012737 000352 177776 104100 012737 000353 177776 104200 16: 012737 000354 177776 104410 012737 000355 177776 104420 24: 000000 013725 177776 012725 001014 000416 013725 177776 32: 012725 001020 000411 013725 177776 012725 001030 000404 40: 013725 177776 012725 001034 011604 010425 016625 000002 48: 016425 177776 000002 ++ wreg (072,00017) a=0004(c0.al ) d=001242 s=00000000! OK -- wblk (013,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 177777 ++ wreg (102,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (112,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (122,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000d(c0.r5 ) d=001146 s=00000000! OK -- wreg (162,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (172,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (202,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (212,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (222,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:35:58.049265 : ATTN notify apat = 0001 lams = 0 dt=0.845254 ++ attn (255,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.182 OK ++ rreg (210,00037) a=000f(c0.pc ) d=001062! s=00000000! OK ++ rreg (220,00017) a=0008(c0.r0 ) d=000000! s=00000000! OK -- rreg (230,00007) a=0009(c0.r1 ) d=000000! s=00000000! OK -- rreg (240,00007) a=000a(c0.r2 ) d=000000! s=00000000! OK -- rreg (250,00007) a=000b(c0.r3 ) d=000000! s=00000000! OK -- rreg (260,00007) a=000d(c0.r5 ) d=001242! s=00000000! OK -- rreg (270,00027) a=000e(c0.sp ) d=001000! s=00000000! OK ++ wreg (232,00017) a=0004(c0.al ) d=001146 s=00000000! OK -- rblk (211,00027) a=0007(c0.memi ) n= 31= 31 s=00000000! OK 0: 000340! 001014! 001010! 000350! 000003! 000341! 001020! 001020! 8: 000351! 000004! 000342! 001030! 001030! 000352! 104100! 000342! 16: 001030! 001040! 000353! 104200! 000343! 001034! 001050! 000354! 24: 104410! 000343! 001034! 001060! 000355! 104420! 177777! test_w11a_inst_traps.tcl: PASS # test_w11a_inst_wait: test wait instruction -------------------------- ++ wreg (242,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (023,00027) a=0007(c0.memi ) n= 2= 2 s=00000000! OK 0: 001010 000340 ++ wreg (252,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (033,00027) a=0007(c0.memi ) n= 7= 7 s=00000000! OK 0: 005200 000001 005200 000000 005067 176756 000002 # A1: test that wait does wait------------------------------- ++ wreg (262,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (272,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (362,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (372,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (002,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK ++ rreg (300,00017) a=0008(c0.r0 ) d=000001! s=00010000! OK -- rreg (310,00007) a=000e(c0.sp ) d=001000! s=00010000! OK -- rreg (320,00007) a=000f(c0.pc ) d=001004! s=00010000! OK -- rreg (330,00027) a=0002(c0.stat ) d=000164! s=00010000! OK ++ rreg (340,00017) a=0008(c0.r0 ) d=000001! s=00010000! OK -- rreg (350,00007) a=000e(c0.sp ) d=001000! s=00010000! OK -- rreg (360,00007) a=000f(c0.pc ) d=001004! s=00010000! OK -- rreg (370,00027) a=0002(c0.stat ) d=000164! s=00010000! OK ++ rreg (000,00017) a=0008(c0.r0 ) d=000001! s=00010000! OK -- rreg (010,00007) a=000e(c0.sp ) d=001000! s=00010000! OK -- rreg (020,00007) a=000f(c0.pc ) d=001004! s=00010000! OK -- rreg (030,00027) a=0002(c0.stat ) d=000164! s=00010000! OK ++ wreg (012,00037) a=4ffd(i0.pirq ) d=002000 s=00010000! OK -I- 16:35:58.747092 : ATTN notify apat = 0001 lams = 0 dt=0.697828 ++ attn (265,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.010 OK ++ rreg (040,00037) a=000f(c0.pc ) d=001010! s=00000000! OK ++ rreg (050,00017) a=0008(c0.r0 ) d=000002! s=00000000! OK -- rreg (060,00007) a=000e(c0.sp ) d=001000! s=00000000! OK -- rreg (070,00027) a=0002(c0.stat ) d=000020! s=00000000! OK # A2: test that doesn't block when single stepped ----------- ++ wreg (022,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (032,00027) a=000f(c0.pc ) d=001000 s=00000000! OK ++ wreg (042,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (100,00007) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (110,00007) a=000f(c0.pc ) d=001002! s=00000000! OK -- rreg (120,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (052,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (130,00007) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (140,00007) a=000f(c0.pc ) d=001004! s=00000000! OK -- rreg (150,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (062,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (160,00007) a=0008(c0.r0 ) d=000002! s=00000000! OK -- rreg (170,00007) a=000f(c0.pc ) d=001006! s=00000000! OK -- rreg (200,00027) a=0002(c0.stat ) d=000100! s=00000000! OK ++ wreg (072,00037) a=0001(c0.cntl ) d=000002 s=00000000! OK test_w11a_inst_wait.tcl: PASS # test_w11a_cdma: test bwm/brm while CPU active ----------------------- # A1: bwm/brm while CPU busy -------------------------------- ++ wreg (102,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (043,00027) a=0007(c0.memi ) n= 17= 17 s=00000000! OK 0: 005000 005001 012702 001032 005201 010203 005223 005223 8: 005223 005223 005700 001770 000000 000000 000000 000000 16: 000000 ++ wreg (112,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (122,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (202,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (212,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (222,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (232,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK ++ wreg (242,00017) a=0004(c0.al ) d=001042 s=00010000! OK -- wblk (053,00027) a=0007(c0.memi ) n= 128= 128 s=00010000! OK 0: 075000 075001 075002 075003 075004 075005 075006 075007 8: 075010 075011 075012 075013 075014 075015 075016 075017 16: 075020 075021 075022 075023 075024 075025 075026 075027 24: 075030 075031 075032 075033 075034 075035 075036 075037 32: 075040 075041 075042 075043 075044 075045 075046 075047 40: 075050 075051 075052 075053 075054 075055 075056 075057 48: 075060 075061 075062 075063 075064 075065 075066 075067 56: 075070 075071 075072 075073 075074 075075 075076 075077 64: 075100 075101 075102 075103 075104 075105 075106 075107 72: 075110 075111 075112 075113 075114 075115 075116 075117 80: 075120 075121 075122 075123 075124 075125 075126 075127 88: 075130 075131 075132 075133 075134 075135 075136 075137 96: 075140 075141 075142 075143 075144 075145 075146 075147 104: 075150 075151 075152 075153 075154 075155 075156 075157 112: 075160 075161 075162 075163 075164 075165 075166 075167 120: 075170 075171 075172 075173 075174 075175 075176 075177 ++ wreg (252,00017) a=0004(c0.al ) d=001042 s=00010000! OK -- rblk (221,00027) a=0007(c0.memi ) n= 128= 128 s=00010000! OK 0: 075000! 075001! 075002! 075003! 075004! 075005! 075006! 075007! 8: 075010! 075011! 075012! 075013! 075014! 075015! 075016! 075017! 16: 075020! 075021! 075022! 075023! 075024! 075025! 075026! 075027! 24: 075030! 075031! 075032! 075033! 075034! 075035! 075036! 075037! 32: 075040! 075041! 075042! 075043! 075044! 075045! 075046! 075047! 40: 075050! 075051! 075052! 075053! 075054! 075055! 075056! 075057! 48: 075060! 075061! 075062! 075063! 075064! 075065! 075066! 075067! 56: 075070! 075071! 075072! 075073! 075074! 075075! 075076! 075077! 64: 075100! 075101! 075102! 075103! 075104! 075105! 075106! 075107! 72: 075110! 075111! 075112! 075113! 075114! 075115! 075116! 075117! 80: 075120! 075121! 075122! 075123! 075124! 075125! 075126! 075127! 88: 075130! 075131! 075132! 075133! 075134! 075135! 075136! 075137! 96: 075140! 075141! 075142! 075143! 075144! 075145! 075146! 075147! 104: 075150! 075151! 075152! 075153! 075154! 075155! 075156! 075157! 112: 075160! 075161! 075162! 075163! 075164! 075165! 075166! 075167! 120: 075170! 075171! 075172! 075173! 075174! 075175! 075176! 075177! ++ wreg (262,00037) a=0008(c0.r0 ) d=000001 s=00010000! OK -I- 16:36:01.363965 : ATTN notify apat = 0001 lams = 0 dt=2.616875 ++ attn (275,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (210,00037) a=000f(c0.pc ) d=001032! s=00000000! OK ++ rreg (220,00037) a=0009(c0.r1 ) d=000165 s=00000000! OK ++ wreg (272,00017) a=0004(c0.al ) d=001032 s=00000000! OK -- rblk (231,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 000165! 000165! 000165! 000165! # A2: bwm/brm while CPU in WAIT ----------------------------- ++ wreg (302,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (063,00027) a=0007(c0.memi ) n= 2= 2 s=00000000! OK 0: 001004 000340 ++ wreg (312,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (073,00027) a=0007(c0.memi ) n= 5= 5 s=00000000! OK 0: 000001 000000 005067 176762 000002 ++ wreg (322,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (332,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (352,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (362,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (372,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (012,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (022,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (032,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (042,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK ++ rreg (230,00037) a=000f(c0.pc ) d=001002! s=00010000! OK ++ wreg (052,00017) a=0004(c0.al ) d=001012 s=00010000! OK -- wblk (103,00027) a=0007(c0.memi ) n= 128= 128 s=00010000! OK 0: 075000 075001 075002 075003 075004 075005 075006 075007 8: 075010 075011 075012 075013 075014 075015 075016 075017 16: 075020 075021 075022 075023 075024 075025 075026 075027 24: 075030 075031 075032 075033 075034 075035 075036 075037 32: 075040 075041 075042 075043 075044 075045 075046 075047 40: 075050 075051 075052 075053 075054 075055 075056 075057 48: 075060 075061 075062 075063 075064 075065 075066 075067 56: 075070 075071 075072 075073 075074 075075 075076 075077 64: 075100 075101 075102 075103 075104 075105 075106 075107 72: 075110 075111 075112 075113 075114 075115 075116 075117 80: 075120 075121 075122 075123 075124 075125 075126 075127 88: 075130 075131 075132 075133 075134 075135 075136 075137 96: 075140 075141 075142 075143 075144 075145 075146 075147 104: 075150 075151 075152 075153 075154 075155 075156 075157 112: 075160 075161 075162 075163 075164 075165 075166 075167 120: 075170 075171 075172 075173 075174 075175 075176 075177 ++ rreg (240,00037) a=000f(c0.pc ) d=001002! s=00010000! OK ++ wreg (062,00017) a=0004(c0.al ) d=001012 s=00010000! OK -- rblk (241,00027) a=0007(c0.memi ) n= 128= 128 s=00010000! OK 0: 075000! 075001! 075002! 075003! 075004! 075005! 075006! 075007! 8: 075010! 075011! 075012! 075013! 075014! 075015! 075016! 075017! 16: 075020! 075021! 075022! 075023! 075024! 075025! 075026! 075027! 24: 075030! 075031! 075032! 075033! 075034! 075035! 075036! 075037! 32: 075040! 075041! 075042! 075043! 075044! 075045! 075046! 075047! 40: 075050! 075051! 075052! 075053! 075054! 075055! 075056! 075057! 48: 075060! 075061! 075062! 075063! 075064! 075065! 075066! 075067! 56: 075070! 075071! 075072! 075073! 075074! 075075! 075076! 075077! 64: 075100! 075101! 075102! 075103! 075104! 075105! 075106! 075107! 72: 075110! 075111! 075112! 075113! 075114! 075115! 075116! 075117! 80: 075120! 075121! 075122! 075123! 075124! 075125! 075126! 075127! 88: 075130! 075131! 075132! 075133! 075134! 075135! 075136! 075137! 96: 075140! 075141! 075142! 075143! 075144! 075145! 075146! 075147! 104: 075150! 075151! 075152! 075153! 075154! 075155! 075156! 075157! 112: 075160! 075161! 075162! 075163! 075164! 075165! 075166! 075167! 120: 075170! 075171! 075172! 075173! 075174! 075175! 075176! 075177! ++ rreg (250,00037) a=000f(c0.pc ) d=001002! s=00010000! OK ++ wreg (072,00037) a=4ffd(i0.pirq ) d=002000 s=00010000! OK -I- 16:36:02.860225 : ATTN notify apat = 0001 lams = 0 dt=1.496260 ++ attn (305,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (260,00037) a=000f(c0.pc ) d=001004! s=00000000! OK test_w11a_cdma.tcl: PASS # test_w11a_cpu_halt: test CPU fatal halt conditions ------------------ ++ wreg (102,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wblk (113,00027) a=0007(c0.memi ) n= 14= 14 s=00000000! OK 0: 000006 000000 000012 000000 000016 000000 000022 000000 8: 000026 000000 000032 000000 000036 000000 ++ wreg (112,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (123,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 000242 000000 000246 000000 000252 000000 ++ wreg (122,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (133,00027) a=0007(c0.memi ) n= 36= 36 s=00000000! OK 0: 012706 001000 012705 077406 010567 171264 010567 171262 8: 005067 171270 010567 171266 012767 000000 171302 012767 16: 000200 171276 012767 001400 171302 012767 177600 171276 24: 012767 001104 176742 012767 000001 176476 005200 104100 32: 005200 000000 005200 000002 ++ wreg (132,00017) a=0004(c0.al ) d=020100 s=00000000! OK -- wblk (143,00027) a=0007(c0.memi ) n= 23= 23 s=00000000! OK 0: 012706 020100 005067 152170 012767 000001 157454 005200 8: 104100 005200 000000 012706 001000 012767 077402 152140 16: 012767 000001 157424 005200 104100 005200 000000 ++ wreg (142,00017) a=0004(c0.al ) d=020256 s=00000000! OK -- wblk (153,00027) a=0007(c0.memi ) n= 24= 24 s=00000000! OK 0: 012706 020256 012767 020256 157504 012767 000001 157274 8: 005200 005046 005200 000000 012706 140000 012767 020256 16: 157454 012767 000001 157244 005200 005046 005200 000000 # A1: initial set up of MMU, execute EMT -------------------- ++ wreg (152,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (162,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (172,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (202,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (212,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:03.632100 : ATTN notify apat = 0001 lams = 0 dt=0.771872 ++ attn (315,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.047 OK ++ rreg (270,00017) a=0008(c0.r0 ) d=000003! s=00000000! OK -- rreg (300,00007) a=000f(c0.pc ) d=001104! s=00000000! OK -- rreg (310,00027) a=0002(c0.stat ) d=000020! s=00000000! OK # A2: vecfet halt after unmap page 0 and EMT ---------------- ++ wreg (222,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (232,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (242,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (252,00007) a=000f(c0.pc ) d=020100 s=00000000! OK -- wreg (262,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:03.764980 : ATTN notify apat = 0001 lams = 0 dt=0.132884 ++ attn (325,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (320,00017) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (330,00007) a=000f(c0.pc ) d=020122! s=00000000! OK -- rreg (340,00027) a=0002(c0.stat ) d=000200! s=00000000! OK # A3: recser halt cases ------------------------------------- # A3.1: after page 0 read-only and EMT ---------- ++ wreg (272,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (302,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (322,00007) a=000f(c0.pc ) d=020126 s=00000000! OK -- wreg (332,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:03.905106 : ATTN notify apat = 0001 lams = 0 dt=0.140128 ++ attn (335,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.014 OK ++ rreg (350,00017) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (360,00007) a=000f(c0.pc ) d=020152! s=00000000! OK -- rreg (370,00027) a=0002(c0.stat ) d=000220! s=00000000! OK # A3.2: after STKLIM abort ---------------------- ++ wreg (342,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (362,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (372,00007) a=000f(c0.pc ) d=020256 s=00000000! OK -- wreg (002,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:04.042520 : ATTN notify apat = 0001 lams = 0 dt=0.137414 ++ attn (345,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.012 OK ++ rreg (000,00017) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (010,00007) a=000f(c0.pc ) d=020302! s=00000000! OK -- rreg (020,00027) a=0002(c0.stat ) d=000220! s=00000000! OK # A3.3: after MMU abort ------------------------- ++ wreg (012,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (022,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (032,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (042,00007) a=000f(c0.pc ) d=020306 s=00000000! OK -- wreg (052,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:04.179034 : ATTN notify apat = 0001 lams = 0 dt=0.136517 ++ attn (355,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.012 OK ++ rreg (030,00017) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (040,00007) a=000f(c0.pc ) d=020332! s=00000000! OK -- rreg (050,00027) a=0002(c0.stat ) d=000220! s=00000000! OK test_w11a_cpu_halt.tcl: PASS @w11a/w11a_all.dat: PASS ## steering file for all w11a_cmon tests # test_cmon_regs: test register response ------------------------------ # A basic register access tests ----------------------------- # A1: write/read cntl--------------------------------- ++ wreg (062,00017) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- rreg (060,00007) a=0048(c0.cm.cntl ) d=000000! s=00000000! OK -- wreg (072,00007) a=0048(c0.cm.cntl ) d=000015 s=00000000! OK -- rreg (070,00007) a=0048(c0.cm.cntl ) d=000010! s=00000000! OK -- wreg (102,00007) a=0048(c0.cm.cntl ) d=000025 s=00000000! OK -- rreg (100,00007) a=0048(c0.cm.cntl ) d=000020! s=00000000! OK -- wreg (112,00007) a=0048(c0.cm.cntl ) d=000045 s=00000000! OK -- rreg (110,00007) a=0048(c0.cm.cntl ) d=000040! s=00000000! OK -- wreg (122,00007) a=0048(c0.cm.cntl ) d=000055 s=00000000! OK -- rreg (120,00007) a=0048(c0.cm.cntl ) d=000050! s=00000000! OK -- wreg (132,00007) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- rreg (130,00007) a=0048(c0.cm.cntl ) d=000050! s=00000000! OK -- wreg (142,00007) a=0048(c0.cm.cntl ) d=000000 s=00000000! OK -- rreg (140,00027) a=0048(c0.cm.cntl ) d=000050! s=00000000! OK # A2: write cntl, read stat -------------------------- ++ wreg (152,00017) a=0048(c0.cm.cntl ) d=000035 s=00000000! OK -- rreg (150,00007) a=0048(c0.cm.cntl ) d=000030! s=00000000! OK -- rreg (160,00007) a=0049(c0.cm.stat ) d=006001! s=00000000! OK -- wreg (162,00007) a=0048(c0.cm.cntl ) d=000006 s=00000000! OK -- rreg (170,00007) a=0048(c0.cm.cntl ) d=000030! s=00000000! OK -- rreg (200,00007) a=0049(c0.cm.stat ) d=006003! s=00000000! OK -- wreg (172,00007) a=0048(c0.cm.cntl ) d=000007 s=00000000! OK -- rreg (210,00007) a=0048(c0.cm.cntl ) d=000030! s=00000000! OK -- rreg (220,00007) a=0049(c0.cm.stat ) d=006001! s=00000000! OK -- wreg (202,00007) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- rreg (230,00027) a=0049(c0.cm.stat ) d=006000! s=00000000! OK ++ wreg (212,00017) a=0048(c0.cm.cntl ) d=000006 s=00000000! OK -- rreg (240,00007) a=0049(c0.cm.stat ) d=006000! s=00000000! OK -- wreg (222,00007) a=0048(c0.cm.cntl ) d=000007 s=00000000! OK -- rreg (250,00027) a=0049(c0.cm.stat ) d=006000! s=00000000! OK ++ wreg (232,00017) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- rreg (260,00007) a=0049(c0.cm.stat ) d=006001! s=00000000! OK -- wreg (242,00007) a=0048(c0.cm.cntl ) d=000006 s=00000000! OK -- rreg (270,00007) a=0049(c0.cm.stat ) d=006003! s=00000000! OK -- wreg (252,00007) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- rreg (300,00027) a=0049(c0.cm.stat ) d=006001! s=00000000! OK ++ wreg (262,00017) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- rreg (310,00007) a=0049(c0.cm.stat ) d=006001! s=00000000! OK -- wreg (272,00007) a=0048(c0.cm.cntl ) d=000006 s=00000000! OK -- rreg (320,00007) a=0049(c0.cm.stat ) d=006003! s=00000000! OK -- wreg (302,00007) a=0048(c0.cm.cntl ) d=000006 s=00000000! OK -- rreg (330,00007) a=0049(c0.cm.stat ) d=006003! s=00000000! OK -- wreg (312,00007) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- rreg (340,00027) a=0049(c0.cm.stat ) d=006000! s=00000000! OK ++ rreg (350,00037) a=0049(c0.cm.stat ) d=006000 s=00000000! OK # A3: test addr -------------------------------------- # A3.1: write/read addr when stopped ----------------- ++ wreg (322,00017) a=004a(c0.cm.addr ) d=000000 s=00000000! OK -- rreg (360,00027) a=004a(c0.cm.addr ) d=000000! s=00000000! OK ++ wreg (332,00017) a=004a(c0.cm.addr ) d=000007 s=00000000! OK -- rreg (370,00027) a=004a(c0.cm.addr ) d=000007! s=00000000! OK ++ wreg (342,00017) a=004a(c0.cm.addr ) d=007760 s=00000000! OK -- rreg (000,00027) a=004a(c0.cm.addr ) d=007760! s=00000000! OK ++ wreg (352,00017) a=004a(c0.cm.addr ) d=007770 s=00000000! OK -- rreg (010,00027) a=004a(c0.cm.addr ) d=007770! s=00000000! OK # A3.2: verify that starting clears addr ------------- ++ wreg (362,00017) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- wreg (372,00007) a=004a(c0.cm.addr ) d=007760 s=00000000! OK -- rreg (020,00007) a=004a(c0.cm.addr ) d=007760! s=00000000! OK -- wreg (002,00007) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- rreg (030,00007) a=004a(c0.cm.addr ) d=000000! s=00000000! OK -- wreg (012,00027) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK # A3.3: test err when started and addr written ------- ++ wreg (022,00017) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- wreg (032,00007) a=004a(c0.cm.addr ) d=000400 s=00000001| OK -- wreg (042,00027) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK # A4: test data -------------------------------------- # A4.1: when stopped --------------------------------- ++ wreg (052,00017) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- wreg (062,00007) a=004a(c0.cm.addr ) d=000200 s=00000000! OK -- rreg (040,00007) a=004b(c0.cm.data ) d=000001 s=00000000! OK -- rreg (050,00007) a=004a(c0.cm.addr ) d=000201! s=00000000! OK -- rreg (060,00007) a=004b(c0.cm.data ) d=177572 s=00000000! OK -- rreg (070,00007) a=004a(c0.cm.addr ) d=000202! s=00000000! OK -- rreg (100,00007) a=004b(c0.cm.data ) d=000001 s=00000000! OK -- rreg (110,00007) a=004a(c0.cm.addr ) d=000203! s=00000000! OK -- rreg (120,00007) a=004b(c0.cm.data ) d=177572 s=00000000! OK -- rreg (130,00027) a=004a(c0.cm.addr ) d=000204! s=00000000! OK ++ rreg (140,00017) a=004b(c0.cm.data ) d=000001 s=00000000! OK -- rreg (150,00007) a=004a(c0.cm.addr ) d=000205! s=00000000! OK -- rreg (160,00007) a=004b(c0.cm.data ) d=000000 s=00000000! OK -- rreg (170,00007) a=004a(c0.cm.addr ) d=000206! s=00000000! OK -- rreg (200,00007) a=004b(c0.cm.data ) d=012767 s=00000000! OK -- rreg (210,00007) a=004a(c0.cm.addr ) d=000207! s=00000000! OK -- rreg (220,00007) a=004b(c0.cm.data ) d=020270 s=00000000! OK -- rreg (230,00007) a=004a(c0.cm.addr ) d=000210! s=00000000! OK -- rreg (240,00007) a=004b(c0.cm.data ) d=142553 s=00000000! OK -- rreg (250,00027) a=004a(c0.cm.addr ) d=000220! s=00000000! OK # A4.2: test err when written ------------------------ ++ wreg (072,00037) a=004b(c0.cm.data ) d=000400 s=00000001| OK # A5: test imon section; readable, not writable ------ ++ rreg (260,00017) a=004c(c0.cm.iaddr ) d=000000 s=00000000! OK -- rreg (270,00007) a=004d(c0.cm.ipc ) d=020330 s=00000000! OK -- rreg (300,00007) a=004e(c0.cm.ireg ) d=005046 s=00000000! OK -- rreg (310,00007) a=004f(c0.cm.imal ) d=137776 s=00000000! OK -- wreg (102,00007) a=004c(c0.cm.iaddr ) d=000000 s=00000001| OK -- wreg (112,00007) a=004d(c0.cm.ipc ) d=000000 s=00000001| OK -- wreg (122,00007) a=004e(c0.cm.ireg ) d=000000 s=00000001| OK -- wreg (132,00027) a=004f(c0.cm.imal ) d=000000 s=00000001| OK test_cmon_regs.tcl: PASS # test_cmon_imon: test last instruction monitor ----------------------- ++ wreg (142,00017) a=0048(c0.cm.cntl ) d=000005 s=00000000! OK -- wreg (152,00007) a=0048(c0.cm.cntl ) d=000004 s=00000000! OK -- rreg (320,00027) a=0048(c0.cm.cntl ) d=000000! s=00000000! OK # A: simple linear code, word access ------------------------ ++ wreg (162,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (163,00027) a=0007(c0.memi ) n= 35= 35 s=00000000! OK 0: 000240 005000 005200 010001 012702 001066 012703 001076 8: 012204 011204 014204 013304 015304 016704 000030 017704 16: 000036 013704 001066 016204 000002 017304 000002 067777 24: 000020 000020 000000 000123 000234 000345 000001 001066 32: 001070 001072 001074 # A1: run code --------------------------------------- ++ wreg (172,00017) a=0004(c0.al ) d=001074 s=00000000! OK -- wreg (202,00027) a=0007(c0.memi ) d=000001 s=00000000! OK ++ wreg (212,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (222,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (302,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (322,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (332,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:05.623912 : ATTN notify apat = 0001 lams = 0 dt=1.444872 ++ attn (365,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.035 OK ++ rreg (330,00037) a=000f(c0.pc ) d=001066! s=00000000! OK ++ rreg (340,00017) a=0008(c0.r0 ) d=000001! s=00000000! OK -- rreg (350,00007) a=0009(c0.r1 ) d=000001! s=00000000! OK -- rreg (360,00007) a=000a(c0.r2 ) d=001066! s=00000000! OK -- rreg (370,00007) a=000b(c0.r3 ) d=001076! s=00000000! OK -- rreg (000,00027) a=000c(c0.r4 ) d=000234! s=00000000! OK ++ wreg (342,00017) a=0004(c0.al ) d=001074 s=00000000! OK -- rblk (251,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 000346! # A2: test ipc,ireg ---------------------------------- ++ wreg (352,00017) a=0004(c0.al ) d=001074 s=00000000! OK -- wreg (362,00027) a=0007(c0.memi ) d=000001 s=00000000! OK ++ wreg (372,00017) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (002,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (012,00027) a=000f(c0.pc ) d=001000 s=00000000! OK ++ wreg (022,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (010,00007) a=004d(c0.cm.ipc ) d=001000! s=00000000! OK -- rreg (020,00027) a=004e(c0.cm.ireg ) d=000240! s=00000000! OK ++ wreg (032,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (030,00007) a=004d(c0.cm.ipc ) d=001002! s=00000000! OK -- rreg (040,00027) a=004e(c0.cm.ireg ) d=005000! s=00000000! OK ++ wreg (042,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (050,00007) a=004d(c0.cm.ipc ) d=001004! s=00000000! OK -- rreg (060,00027) a=004e(c0.cm.ireg ) d=005200! s=00000000! OK ++ wreg (052,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (070,00007) a=004d(c0.cm.ipc ) d=001006! s=00000000! OK -- rreg (100,00027) a=004e(c0.cm.ireg ) d=010001! s=00000000! OK ++ wreg (062,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (110,00007) a=004d(c0.cm.ipc ) d=001010! s=00000000! OK -- rreg (120,00027) a=004e(c0.cm.ireg ) d=012702! s=00000000! OK ++ wreg (072,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (130,00007) a=004d(c0.cm.ipc ) d=001014! s=00000000! OK -- rreg (140,00027) a=004e(c0.cm.ireg ) d=012703! s=00000000! OK ++ wreg (102,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (150,00007) a=004d(c0.cm.ipc ) d=001020! s=00000000! OK -- rreg (160,00027) a=004e(c0.cm.ireg ) d=012204! s=00000000! OK ++ wreg (112,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (170,00007) a=004d(c0.cm.ipc ) d=001022! s=00000000! OK -- rreg (200,00027) a=004e(c0.cm.ireg ) d=011204! s=00000000! OK ++ wreg (122,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (210,00007) a=004d(c0.cm.ipc ) d=001024! s=00000000! OK -- rreg (220,00027) a=004e(c0.cm.ireg ) d=014204! s=00000000! OK ++ wreg (132,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (230,00007) a=004d(c0.cm.ipc ) d=001026! s=00000000! OK -- rreg (240,00027) a=004e(c0.cm.ireg ) d=013304! s=00000000! OK ++ wreg (142,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (250,00007) a=004d(c0.cm.ipc ) d=001030! s=00000000! OK -- rreg (260,00027) a=004e(c0.cm.ireg ) d=015304! s=00000000! OK ++ wreg (152,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (270,00007) a=004d(c0.cm.ipc ) d=001032! s=00000000! OK -- rreg (300,00027) a=004e(c0.cm.ireg ) d=016704! s=00000000! OK ++ wreg (162,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (310,00007) a=004d(c0.cm.ipc ) d=001036! s=00000000! OK -- rreg (320,00027) a=004e(c0.cm.ireg ) d=017704! s=00000000! OK ++ wreg (172,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (330,00007) a=004d(c0.cm.ipc ) d=001042! s=00000000! OK -- rreg (340,00027) a=004e(c0.cm.ireg ) d=013704! s=00000000! OK ++ wreg (202,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (350,00007) a=004d(c0.cm.ipc ) d=001046! s=00000000! OK -- rreg (360,00027) a=004e(c0.cm.ireg ) d=016204! s=00000000! OK ++ wreg (212,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (370,00007) a=004d(c0.cm.ipc ) d=001052! s=00000000! OK -- rreg (000,00027) a=004e(c0.cm.ireg ) d=017304! s=00000000! OK ++ wreg (222,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (010,00007) a=004d(c0.cm.ipc ) d=001056! s=00000000! OK -- rreg (020,00027) a=004e(c0.cm.ireg ) d=067777! s=00000000! OK # A3: test imal (memory access log) ------------------ ++ wreg (232,00017) a=0004(c0.al ) d=001074 s=00000000! OK -- wreg (242,00027) a=0007(c0.memi ) d=000001 s=00000000! OK ++ wreg (252,00017) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (262,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (272,00027) a=000f(c0.pc ) d=001000 s=00000000! OK ++ wreg (302,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (030,00007) a=004d(c0.cm.ipc ) d=001000! s=00000000! OK -- rreg (040,00027) a=0049(c0.cm.stat ) d=000000! s=00000000! OK ++ wreg (312,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (050,00007) a=004d(c0.cm.ipc ) d=001002! s=00000000! OK -- rreg (060,00027) a=0049(c0.cm.stat ) d=000000! s=00000000! OK ++ wreg (322,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (070,00007) a=004d(c0.cm.ipc ) d=001004! s=00000000! OK -- rreg (100,00027) a=0049(c0.cm.stat ) d=000000! s=00000000! OK ++ wreg (332,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (110,00007) a=004d(c0.cm.ipc ) d=001006! s=00000000! OK -- rreg (120,00027) a=0049(c0.cm.stat ) d=000000! s=00000000! OK ++ wreg (342,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (130,00007) a=004d(c0.cm.ipc ) d=001010! s=00000000! OK -- rreg (140,00007) a=0049(c0.cm.stat ) d=002000! s=00000000! OK -- rblk (261,00027) a=004f(c0.cm.imal ) n= 2= 2 s=00000000! OK 0: 001012! 001066! ++ wreg (352,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (150,00007) a=004d(c0.cm.ipc ) d=001014! s=00000000! OK -- rreg (160,00007) a=0049(c0.cm.stat ) d=002000! s=00000000! OK -- rblk (271,00027) a=004f(c0.cm.imal ) n= 2= 2 s=00000000! OK 0: 001016! 001076! ++ wreg (362,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (170,00007) a=004d(c0.cm.ipc ) d=001020! s=00000000! OK -- rreg (200,00007) a=0049(c0.cm.stat ) d=002000! s=00000000! OK -- rblk (301,00027) a=004f(c0.cm.imal ) n= 2= 2 s=00000000! OK 0: 001066! 000123! ++ wreg (372,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (210,00007) a=004d(c0.cm.ipc ) d=001022! s=00000000! OK -- rreg (220,00007) a=0049(c0.cm.stat ) d=002000! s=00000000! OK -- rblk (311,00027) a=004f(c0.cm.imal ) n= 2= 2 s=00000000! OK 0: 001070! 000234! ++ wreg (002,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (230,00007) a=004d(c0.cm.ipc ) d=001024! s=00000000! OK -- rreg (240,00007) a=0049(c0.cm.stat ) d=002000! s=00000000! OK -- rblk (321,00027) a=004f(c0.cm.imal ) n= 2= 2 s=00000000! OK 0: 001066! 000123! ++ wreg (012,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (250,00007) a=004d(c0.cm.ipc ) d=001026! s=00000000! OK -- rreg (260,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (331,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001076! 001066! 001066! 000123! ++ wreg (022,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (270,00007) a=004d(c0.cm.ipc ) d=001030! s=00000000! OK -- rreg (300,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (341,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001076! 001066! 001066! 000123! ++ wreg (032,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (310,00007) a=004d(c0.cm.ipc ) d=001032! s=00000000! OK -- rreg (320,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (351,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001034! 000030! 001066! 000123! ++ wreg (042,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (330,00007) a=004d(c0.cm.ipc ) d=001036! s=00000000! OK -- rreg (340,00007) a=0049(c0.cm.stat ) d=006000! s=00000000! OK -- rblk (361,00027) a=004f(c0.cm.imal ) n= 6= 6 s=00000000! OK 0: 001040! 000036! 001100! 001070! 001070! 000234! ++ wreg (052,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (350,00007) a=004d(c0.cm.ipc ) d=001042! s=00000000! OK -- rreg (360,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (371,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001044! 001066! 001066! 000123! ++ wreg (062,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (370,00007) a=004d(c0.cm.ipc ) d=001046! s=00000000! OK -- rreg (000,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (001,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001050! 000002! 001070! 000234! ++ wreg (072,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (010,00007) a=004d(c0.cm.ipc ) d=001052! s=00000000! OK -- rreg (020,00007) a=0049(c0.cm.stat ) d=006000! s=00000000! OK -- rblk (011,00027) a=004f(c0.cm.imal ) n= 6= 6 s=00000000! OK 0: 001054! 000002! 001100! 001070! 001070! 000234! ++ wreg (102,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (030,00007) a=004d(c0.cm.ipc ) d=001056! s=00000000! OK -- rreg (040,00007) a=0049(c0.cm.stat ) d=016000! s=00000000! OK -- rblk (021,00027) a=004f(c0.cm.imal ) n= 14= 14 s=00000000! OK 0: 001060! 000020! 001102! 001072! 001072! 000345! 001062! 000020! 8: 001104! 001074! 001074! 000001! 001074! 000346! # B: simple linear code, byte access ------------------------ ++ wreg (112,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (173,00027) a=0007(c0.memi ) n= 17= 17 s=00000000! OK 0: 000240 116700 000026 116701 000023 110067 000020 110167 8: 000015 105267 000012 105267 000007 000000 005005 000000 16: 125125 # B1: test imal (memory access log) ------------------ ++ wreg (122,00017) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (132,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (142,00027) a=000f(c0.pc ) d=001000 s=00000000! OK ++ wreg (152,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (050,00007) a=004d(c0.cm.ipc ) d=001000! s=00000000! OK -- rreg (060,00027) a=0049(c0.cm.stat ) d=000000! s=00000000! OK ++ wreg (162,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (070,00007) a=004d(c0.cm.ipc ) d=001002! s=00000000! OK -- rreg (100,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (031,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001004! 000026! 001034! 000005! ++ wreg (172,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (110,00007) a=004d(c0.cm.ipc ) d=001006! s=00000000! OK -- rreg (120,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (041,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001010! 000023! 001035! 000012! ++ wreg (202,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (130,00007) a=004d(c0.cm.ipc ) d=001012! s=00000000! OK -- rreg (140,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (051,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001014! 000020! 001036! 000005! ++ wreg (212,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (150,00007) a=004d(c0.cm.ipc ) d=001016! s=00000000! OK -- rreg (160,00007) a=0049(c0.cm.stat ) d=004000! s=00000000! OK -- rblk (061,00027) a=004f(c0.cm.imal ) n= 4= 4 s=00000000! OK 0: 001020! 000015! 001037! 000012! ++ wreg (222,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (170,00007) a=004d(c0.cm.ipc ) d=001022! s=00000000! OK -- rreg (200,00007) a=0049(c0.cm.stat ) d=006000! s=00000000! OK -- rblk (071,00027) a=004f(c0.cm.imal ) n= 6= 6 s=00000000! OK 0: 001024! 000012! 001040! 000125! 001040! 000126! ++ wreg (232,00017) a=0001(c0.cntl ) d=000003 s=00000000! OK -- rreg (210,00007) a=004d(c0.cm.ipc ) d=001026! s=00000000! OK -- rreg (220,00007) a=0049(c0.cm.stat ) d=006000! s=00000000! OK -- rblk (101,00027) a=004f(c0.cm.imal ) n= 6= 6 s=00000000! OK 0: 001030! 000007! 001041! 000252! 001041! 000253! test_cmon_imon.tcl: PASS @w11a_cmon/w11a_cmon_all.dat: PASS ## steering file for all w11a_hbpt tests # test_hbpt_regs: test register response ------------------------------ # A1: test cntl,stat for unit 0 ----------------------------- ++ wreg (242,00017) a=0050(c0.hb0.cntl ) d=000021 s=00000000! OK -- wreg (252,00007) a=0051(c0.hb0.stat ) d=000004 s=00000000! OK -- rreg (230,00007) a=0050(c0.hb0.cntl ) d=000021! s=00000000! OK -- rreg (240,00027) a=0051(c0.hb0.stat ) d=000004! s=00000000! OK ++ wreg (262,00017) a=0050(c0.hb0.cntl ) d=000043 s=00000000! OK -- wreg (272,00007) a=0051(c0.hb0.stat ) d=000006 s=00000000! OK -- rreg (250,00007) a=0050(c0.hb0.cntl ) d=000043! s=00000000! OK -- rreg (260,00027) a=0051(c0.hb0.stat ) d=000006! s=00000000! OK ++ wreg (302,00017) a=0050(c0.hb0.cntl ) d=000067 s=00000000! OK -- wreg (312,00007) a=0051(c0.hb0.stat ) d=000007 s=00000000! OK -- rreg (270,00007) a=0050(c0.hb0.cntl ) d=000067! s=00000000! OK -- rreg (300,00027) a=0051(c0.hb0.stat ) d=000007! s=00000000! OK ++ wreg (322,00017) a=0050(c0.hb0.cntl ) d=000000 s=00000000! OK -- wreg (332,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- rreg (310,00007) a=0050(c0.hb0.cntl ) d=000000! s=00000000! OK -- rreg (320,00027) a=0051(c0.hb0.stat ) d=000000! s=00000000! OK # A2: test hilim,lolim for unit 0 --------------------------- ++ wreg (342,00017) a=0052(c0.hb0.hilim) d=177777 s=00000000! OK -- wreg (352,00007) a=0053(c0.hb0.lolim) d=100000 s=00000000! OK -- rreg (330,00007) a=0052(c0.hb0.hilim) d=177776! s=00000000! OK -- rreg (340,00027) a=0053(c0.hb0.lolim) d=100000! s=00000000! OK ++ wreg (362,00017) a=0052(c0.hb0.hilim) d=100000 s=00000000! OK -- wreg (372,00007) a=0053(c0.hb0.lolim) d=177777 s=00000000! OK -- rreg (350,00007) a=0052(c0.hb0.hilim) d=100000! s=00000000! OK -- rreg (360,00027) a=0053(c0.hb0.lolim) d=177776! s=00000000! OK ++ wreg (002,00017) a=0052(c0.hb0.hilim) d=000000 s=00000000! OK -- wreg (012,00007) a=0053(c0.hb0.lolim) d=000000 s=00000000! OK -- rreg (370,00007) a=0052(c0.hb0.hilim) d=000000! s=00000000! OK -- rreg (000,00027) a=0053(c0.hb0.lolim) d=000000! s=00000000! OK # A3: test cntl,stat,hi,lolim for all 2 units --------------- ++ wreg (022,00017) a=0050(c0.hb0.cntl ) d=000001 s=00000000! OK -- wreg (032,00007) a=0051(c0.hb0.stat ) d=000001 s=00000000! OK -- wreg (042,00007) a=0052(c0.hb0.hilim) d=004644 s=00000000! OK -- wreg (052,00027) a=0053(c0.hb0.lolim) d=011122 s=00000000! OK ++ wreg (062,00017) a=0054(c0.hb1.cntl ) d=000002 s=00000000! OK -- wreg (072,00007) a=0055(c0.hb1.stat ) d=000002 s=00000000! OK -- wreg (102,00007) a=0056(c0.hb1.hilim) d=011510 s=00000000! OK -- wreg (112,00027) a=0057(c0.hb1.lolim) d=022244 s=00000000! OK ++ rreg (010,00017) a=0050(c0.hb0.cntl ) d=000001! s=00000000! OK -- rreg (020,00007) a=0051(c0.hb0.stat ) d=000001! s=00000000! OK -- rreg (030,00007) a=0052(c0.hb0.hilim) d=004644! s=00000000! OK -- rreg (040,00027) a=0053(c0.hb0.lolim) d=011122! s=00000000! OK ++ rreg (050,00017) a=0054(c0.hb1.cntl ) d=000002! s=00000000! OK -- rreg (060,00007) a=0055(c0.hb1.stat ) d=000002! s=00000000! OK -- rreg (070,00007) a=0056(c0.hb1.hilim) d=011510! s=00000000! OK -- rreg (100,00027) a=0057(c0.hb1.lolim) d=022244! s=00000000! OK test_hbpt_regs.tcl: PASS # test_hbpt_basics: basic tests with 1 unit --------------------------- # setup: clear all bpts ++ wreg (122,00017) a=0050(c0.hb0.cntl ) d=000000 s=00000000! OK -- wreg (132,00027) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK ++ wreg (142,00017) a=0054(c0.hb1.cntl ) d=000000 s=00000000! OK -- wreg (152,00027) a=0055(c0.hb1.stat ) d=000000 s=00000000! OK # A basic ir,dr,dw break tests ------------------------------ ++ wreg (162,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (203,00027) a=0007(c0.memi ) n= 20= 20 s=00000000! OK 0: 000240 005000 005200 005200 005200 016701 000016 017702 8: 000022 010167 000012 010277 000014 000000 000123 000234 16: 000000 000000 001036 001042 # A1: run code without breaks ------------------------ ++ wreg (172,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (202,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (222,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (262,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (272,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (302,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (312,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:09.006747 : ATTN notify apat = 0001 lams = 0 dt=3.382835 ++ attn (375,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (110,00037) a=000f(c0.pc ) d=001034! s=00000000! OK ++ rreg (120,00017) a=0008(c0.r0 ) d=000003! s=00000000! OK -- rreg (130,00007) a=0009(c0.r1 ) d=000123! s=00000000! OK -- rreg (140,00027) a=000a(c0.r2 ) d=000234! s=00000000! OK ++ wreg (322,00017) a=0004(c0.al ) d=001040 s=00000000! OK -- rblk (111,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 000123! ++ wreg (332,00017) a=0004(c0.al ) d=001042 s=00000000! OK -- rblk (121,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 000234! # A2.1: ir break on single instruction --------------- ++ wreg (342,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (352,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (362,00007) a=0052(c0.hb0.hilim) d=001004 s=00000000! OK -- wreg (372,00027) a=0053(c0.hb0.lolim) d=001004 s=00000000! OK ++ wreg (002,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (012,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (072,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (102,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (112,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (122,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:09.332215 : ATTN notify apat = 0001 lams = 0 dt=0.325468 ++ attn (005,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (150,00017) a=0051(c0.hb0.stat ) d=000004! s=00110000! OK -- rreg (160,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (170,00007) a=000f(c0.pc ) d=001006! s=00110000! OK -- rreg (200,00027) a=0008(c0.r0 ) d=000001! s=00110000! OK # A2.2: step after ir break -------------------------- ++ wreg (132,00037) a=0001(c0.cntl ) d=000003 s=00110000! OK ++ rreg (210,00017) a=0051(c0.hb0.stat ) d=000004! s=00110000! OK -- rreg (220,00007) a=0002(c0.stat ) d=000514! s=00110000! OK -- rreg (230,00007) a=000f(c0.pc ) d=001010! s=00110000! OK -- rreg (240,00027) a=0008(c0.r0 ) d=000002! s=00110000! OK # A2.3: resume after ir break ------------------------ ++ wreg (142,00037) a=0001(c0.cntl ) d=000007 s=00110000! OK -I- 16:36:09.503381 : ATTN notify apat = 0001 lams = 0 dt=0.171167 ++ attn (015,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.010 OK ++ rreg (250,00037) a=000f(c0.pc ) d=001034! s=00000000! OK ++ rreg (260,00017) a=0008(c0.r0 ) d=000003! s=00000000! OK -- rreg (270,00007) a=0009(c0.r1 ) d=000123! s=00000000! OK -- rreg (300,00027) a=000a(c0.r2 ) d=000234! s=00000000! OK # A3.1: ir break on range of instructions ------------ ++ wreg (152,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (162,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (172,00007) a=0052(c0.hb0.hilim) d=001010 s=00000000! OK -- wreg (202,00027) a=0053(c0.hb0.lolim) d=001006 s=00000000! OK ++ wreg (212,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (222,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (302,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (322,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (332,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:09.756075 : ATTN notify apat = 0001 lams = 0 dt=0.252694 ++ attn (025,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (310,00017) a=0051(c0.hb0.stat ) d=000004! s=00110000! OK -- rreg (320,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (330,00007) a=000f(c0.pc ) d=001010! s=00110000! OK -- rreg (340,00027) a=0008(c0.r0 ) d=000002! s=00110000! OK # A3.2: resume, should re-break ---------------------- ++ wreg (342,00037) a=0001(c0.cntl ) d=000007 s=00110000! OK -I- 16:36:09.851579 : ATTN notify apat = 0001 lams = 0 dt=0.095506 ++ attn (035,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (350,00017) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (360,00007) a=000f(c0.pc ) d=001012! s=00110000! OK -- rreg (370,00027) a=0008(c0.r0 ) d=000003! s=00110000! OK # A3.3: resume, should run to end -------------------- ++ wreg (352,00037) a=0001(c0.cntl ) d=000007 s=00110000! OK -I- 16:36:09.945358 : ATTN notify apat = 0001 lams = 0 dt=0.093781 ++ attn (045,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.010 OK ++ rreg (000,00037) a=000f(c0.pc ) d=001034! s=00000000! OK ++ rreg (010,00017) a=0008(c0.r0 ) d=000003! s=00000000! OK -- rreg (020,00007) a=0009(c0.r1 ) d=000123! s=00000000! OK -- rreg (030,00027) a=000a(c0.r2 ) d=000234! s=00000000! OK # A4.1: dr break on direct read location ------------- ++ wreg (362,00017) a=0050(c0.hb0.cntl ) d=000041 s=00000000! OK -- wreg (372,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (002,00007) a=0052(c0.hb0.hilim) d=001034 s=00000000! OK -- wreg (012,00027) a=0053(c0.hb0.lolim) d=001034 s=00000000! OK ++ wreg (022,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (032,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (072,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (102,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (112,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (122,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (132,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (142,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:10.199367 : ATTN notify apat = 0001 lams = 0 dt=0.254004 ++ attn (055,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (040,00017) a=0051(c0.hb0.stat ) d=000001! s=00110000! OK -- rreg (050,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (060,00007) a=000f(c0.pc ) d=001016! s=00110000! OK -- rreg (070,00027) a=0009(c0.r1 ) d=000123! s=00110000! OK # A4.2: dr break on pointer used in indirect write --- ++ wreg (152,00017) a=0050(c0.hb0.cntl ) d=000041 s=00110000! OK -- wreg (162,00007) a=0051(c0.hb0.stat ) d=000000 s=00110000! OK -- wreg (172,00007) a=0052(c0.hb0.hilim) d=001046 s=00110000! OK -- wreg (202,00027) a=0053(c0.hb0.lolim) d=001046 s=00110000! OK ++ wreg (212,00037) a=0001(c0.cntl ) d=000007 s=00110000! OK -I- 16:36:10.347879 : ATTN notify apat = 0001 lams = 0 dt=0.148517 ++ attn (065,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (100,00017) a=0051(c0.hb0.stat ) d=000001! s=00110000! OK -- rreg (110,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (120,00007) a=000f(c0.pc ) d=001032! s=00110000! OK -- rreg (130,00027) a=000a(c0.r2 ) d=000234! s=00110000! OK # A5.1: dw break on direct written location ---------- ++ wreg (222,00017) a=0050(c0.hb0.cntl ) d=000042 s=00110000! OK -- wreg (232,00007) a=0051(c0.hb0.stat ) d=000000 s=00110000! OK -- wreg (242,00007) a=0052(c0.hb0.hilim) d=001040 s=00110000! OK -- wreg (252,00027) a=0053(c0.hb0.lolim) d=001040 s=00110000! OK ++ wreg (262,00017) a=0008(c0.r0 ) d=000000 s=00110000! OK -- wreg (272,00007) a=0009(c0.r1 ) d=000000 s=00110000! OK -- wreg (302,00007) a=000a(c0.r2 ) d=000000 s=00110000! OK -- wreg (312,00007) a=000b(c0.r3 ) d=000000 s=00110000! OK -- wreg (322,00007) a=000c(c0.r4 ) d=000000 s=00110000! OK -- wreg (332,00007) a=000d(c0.r5 ) d=000000 s=00110000! OK -- wreg (342,00007) a=000e(c0.sp ) d=001000 s=00110000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000002 s=00100000! OK -- wreg (362,00007) a=0001(c0.cntl ) d=000004 s=00100000! OK -- wreg (372,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (002,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:10.592863 : ATTN notify apat = 0001 lams = 0 dt=0.244980 ++ attn (075,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (140,00017) a=0051(c0.hb0.stat ) d=000002! s=00110000! OK -- rreg (150,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (160,00007) a=000f(c0.pc ) d=001026! s=00110000! OK -- rreg (170,00027) a=000a(c0.r2 ) d=000234! s=00110000! OK # A5.2: dw break on indirect write location ---------- ++ wreg (012,00017) a=0050(c0.hb0.cntl ) d=000042 s=00110000! OK -- wreg (022,00007) a=0051(c0.hb0.stat ) d=000000 s=00110000! OK -- wreg (032,00007) a=0052(c0.hb0.hilim) d=001042 s=00110000! OK -- wreg (042,00027) a=0053(c0.hb0.lolim) d=001042 s=00110000! OK ++ wreg (052,00037) a=0001(c0.cntl ) d=000007 s=00110000! OK -I- 16:36:10.739717 : ATTN notify apat = 0001 lams = 0 dt=0.146852 ++ attn (105,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (200,00017) a=0051(c0.hb0.stat ) d=000002! s=00110000! OK -- rreg (210,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (220,00007) a=000f(c0.pc ) d=001032! s=00110000! OK -- rreg (230,00027) a=000a(c0.r2 ) d=000234! s=00110000! OK # B specific ir tests --------------------------------------- ++ wreg (062,00017) a=0004(c0.al ) d=001000 s=00110000! OK -- wblk (213,00027) a=0007(c0.memi ) n= 14= 14 s=00110000! OK 0: 000240 012700 001026 016701 000014 016002 000002 006567 8: 000010 012603 000000 000123 000234 000345 # B1: run code without breaks ------------------------ ++ wreg (072,00017) a=0008(c0.r0 ) d=000000 s=00110000! OK -- wreg (102,00007) a=0009(c0.r1 ) d=000000 s=00110000! OK -- wreg (112,00007) a=000a(c0.r2 ) d=000000 s=00110000! OK -- wreg (122,00007) a=000b(c0.r3 ) d=000000 s=00110000! OK -- wreg (132,00007) a=000c(c0.r4 ) d=000000 s=00110000! OK -- wreg (142,00007) a=000d(c0.r5 ) d=000000 s=00110000! OK -- wreg (152,00007) a=000e(c0.sp ) d=001000 s=00110000! OK -- wreg (162,00007) a=0001(c0.cntl ) d=000002 s=00100000! OK -- wreg (172,00007) a=0001(c0.cntl ) d=000004 s=00100000! OK -- wreg (202,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (212,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:11.064241 : ATTN notify apat = 0001 lams = 0 dt=0.324525 ++ attn (115,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (240,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ rreg (250,00017) a=0008(c0.r0 ) d=001026! s=00000000! OK -- rreg (260,00007) a=0009(c0.r1 ) d=000123! s=00000000! OK -- rreg (270,00007) a=000a(c0.r2 ) d=000234! s=00000000! OK -- rreg (300,00027) a=000b(c0.r3 ) d=000345! s=00000000! OK # B2: ensure that immediate fetch doesn't ir break --- ++ wreg (222,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (232,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (242,00007) a=0052(c0.hb0.hilim) d=001004 s=00000000! OK -- wreg (252,00027) a=0053(c0.hb0.lolim) d=001004 s=00000000! OK ++ wreg (262,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (272,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (362,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (372,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (002,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:11.333566 : ATTN notify apat = 0001 lams = 0 dt=0.269325 ++ attn (125,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (310,00037) a=000f(c0.pc ) d=001026! s=00000000! OK # B3: ensure that index fetch (reg != pc) doesn't ir break --- ++ wreg (012,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (022,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (032,00007) a=0052(c0.hb0.hilim) d=001010 s=00000000! OK -- wreg (042,00027) a=0053(c0.hb0.lolim) d=001010 s=00000000! OK ++ wreg (052,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (062,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (072,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (102,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (112,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (122,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (142,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (152,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (162,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (172,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:11.555482 : ATTN notify apat = 0001 lams = 0 dt=0.221916 ++ attn (135,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (320,00037) a=000f(c0.pc ) d=001026! s=00000000! OK # B4: ensure that index fetch (reg == pc) doesn't ir break --- ++ wreg (202,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (212,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (222,00007) a=0052(c0.hb0.hilim) d=001014 s=00000000! OK -- wreg (232,00027) a=0053(c0.hb0.lolim) d=001014 s=00000000! OK ++ wreg (242,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (252,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (342,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (352,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (362,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:11.777502 : ATTN notify apat = 0001 lams = 0 dt=0.222023 ++ attn (145,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (330,00037) a=000f(c0.pc ) d=001026! s=00000000! OK # B5: ensure that mfpi doesn't ir break --- ++ wreg (372,00017) a=0050(c0.hb0.cntl ) d=000044 s=00000000! OK -- wreg (002,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (012,00007) a=0052(c0.hb0.hilim) d=001032 s=00000000! OK -- wreg (022,00027) a=0053(c0.hb0.lolim) d=001032 s=00000000! OK ++ wreg (032,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (042,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (072,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (102,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (112,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (122,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (132,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (142,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (152,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:11.999334 : ATTN notify apat = 0001 lams = 0 dt=0.221832 ++ attn (155,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (340,00037) a=000f(c0.pc ) d=001026! s=00000000! OK # C test mode logic and mfpd/mtpd --------------------------- ++ wreg (162,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (223,00027) a=0007(c0.memi ) n= 23= 23 s=00000000! OK 0: 000240 012737 170000 177776 016700 000032 010067 000030 8: 000240 012737 030000 177776 106567 000016 011601 106667 16: 000012 000240 000000 000123 000000 000234 000000 # C1: run code without breaks ------------------------ ++ wreg (172,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (202,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (222,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (262,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (272,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (302,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (312,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:12.345203 : ATTN notify apat = 0001 lams = 0 dt=0.345865 ++ attn (165,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.021 OK ++ rreg (350,00037) a=000f(c0.pc ) d=001046! s=00000000! OK ++ rreg (360,00017) a=0008(c0.r0 ) d=000123! s=00000000! OK -- rreg (370,00027) a=0009(c0.r1 ) d=000234! s=00000000! OK ++ wreg (322,00017) a=0004(c0.al ) d=001050 s=00000000! OK -- rblk (131,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 000123! ++ wreg (332,00017) a=0004(c0.al ) d=001054 s=00000000! OK -- rblk (141,00027) a=0007(c0.memi ) n= 1= 1 s=00000000! OK 0: 000234! # C2.1: kernel dr break on user mode read -> no bpt -- ++ wreg (342,00017) a=0050(c0.hb0.cntl ) d=000001 s=00000000! OK -- wreg (352,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (362,00007) a=0052(c0.hb0.hilim) d=001046 s=00000000! OK -- wreg (372,00027) a=0053(c0.hb0.lolim) d=001046 s=00000000! OK ++ wreg (002,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (012,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (052,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (062,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (072,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (102,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (112,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (122,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:12.683116 : ATTN notify apat = 0001 lams = 0 dt=0.337913 ++ attn (175,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.023 OK ++ rreg (000,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C2.2: super dr break on user mode read -> no bpt --- ++ wreg (132,00017) a=0050(c0.hb0.cntl ) d=000021 s=00000000! OK -- wreg (142,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (152,00007) a=0052(c0.hb0.hilim) d=001046 s=00000000! OK -- wreg (162,00027) a=0053(c0.hb0.lolim) d=001046 s=00000000! OK ++ wreg (172,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (202,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (222,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (232,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (262,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (272,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (302,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (312,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:12.918604 : ATTN notify apat = 0001 lams = 0 dt=0.235492 ++ attn (205,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.021 OK ++ rreg (010,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C2.3: user dw break on user mode write -> bpt ----- ++ wreg (322,00017) a=0050(c0.hb0.cntl ) d=000062 s=00000000! OK -- wreg (332,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (342,00007) a=0052(c0.hb0.hilim) d=001050 s=00000000! OK -- wreg (352,00027) a=0053(c0.hb0.lolim) d=001050 s=00000000! OK ++ wreg (362,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (372,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (012,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (052,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (062,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (072,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (102,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:13.135674 : ATTN notify apat = 0001 lams = 0 dt=0.217068 ++ attn (215,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.009 OK ++ rreg (020,00017) a=0051(c0.hb0.stat ) d=000002! s=00110000! OK -- rreg (030,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (040,00027) a=000f(c0.pc ) d=001020! s=00110000! OK # C3.1: kernel dr break on mfpd (pm=user) -> no bpt -- ++ wreg (112,00017) a=0050(c0.hb0.cntl ) d=000001 s=00110000! OK -- wreg (122,00007) a=0051(c0.hb0.stat ) d=000000 s=00110000! OK -- wreg (132,00007) a=0052(c0.hb0.hilim) d=001052 s=00110000! OK -- wreg (142,00027) a=0053(c0.hb0.lolim) d=001052 s=00110000! OK ++ wreg (152,00017) a=0008(c0.r0 ) d=000000 s=00110000! OK -- wreg (162,00007) a=0009(c0.r1 ) d=000000 s=00110000! OK -- wreg (172,00007) a=000a(c0.r2 ) d=000000 s=00110000! OK -- wreg (202,00007) a=000b(c0.r3 ) d=000000 s=00110000! OK -- wreg (212,00007) a=000c(c0.r4 ) d=000000 s=00110000! OK -- wreg (222,00007) a=000d(c0.r5 ) d=000000 s=00110000! OK -- wreg (232,00007) a=000e(c0.sp ) d=001000 s=00110000! OK -- wreg (242,00007) a=0001(c0.cntl ) d=000002 s=00100000! OK -- wreg (252,00007) a=0001(c0.cntl ) d=000004 s=00100000! OK -- wreg (262,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (272,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:13.387342 : ATTN notify apat = 0001 lams = 0 dt=0.251667 ++ attn (225,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.023 OK ++ rreg (050,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C3.2: super dr break on mfpd (pm=user) -> no bpt -- ++ wreg (302,00017) a=0050(c0.hb0.cntl ) d=000021 s=00000000! OK -- wreg (312,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (322,00007) a=0052(c0.hb0.hilim) d=001052 s=00000000! OK -- wreg (332,00027) a=0053(c0.hb0.lolim) d=001052 s=00000000! OK ++ wreg (342,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (352,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (362,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (372,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (012,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (032,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (042,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (052,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (062,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:13.622756 : ATTN notify apat = 0001 lams = 0 dt=0.235414 ++ attn (235,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.023 OK ++ rreg (060,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C3.3: user dr break on mfpd (pm=user) -> bpt ----- ++ wreg (072,00017) a=0050(c0.hb0.cntl ) d=000061 s=00000000! OK -- wreg (102,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (112,00007) a=0052(c0.hb0.hilim) d=001052 s=00000000! OK -- wreg (122,00027) a=0053(c0.hb0.lolim) d=001052 s=00000000! OK ++ wreg (132,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (142,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (202,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (222,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (232,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (242,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (252,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:13.847645 : ATTN notify apat = 0001 lams = 0 dt=0.224891 ++ attn (245,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.015 OK ++ rreg (070,00017) a=0051(c0.hb0.stat ) d=000001! s=00110000! OK -- rreg (100,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (110,00027) a=000f(c0.pc ) d=001034! s=00110000! OK # C4.1: kernel dw break on mtpd (pm=user) -> no bpt -- ++ wreg (262,00017) a=0050(c0.hb0.cntl ) d=000002 s=00110000! OK -- wreg (272,00007) a=0051(c0.hb0.stat ) d=000000 s=00110000! OK -- wreg (302,00007) a=0052(c0.hb0.hilim) d=001054 s=00110000! OK -- wreg (312,00027) a=0053(c0.hb0.lolim) d=001054 s=00110000! OK ++ wreg (322,00017) a=0008(c0.r0 ) d=000000 s=00110000! OK -- wreg (332,00007) a=0009(c0.r1 ) d=000000 s=00110000! OK -- wreg (342,00007) a=000a(c0.r2 ) d=000000 s=00110000! OK -- wreg (352,00007) a=000b(c0.r3 ) d=000000 s=00110000! OK -- wreg (362,00007) a=000c(c0.r4 ) d=000000 s=00110000! OK -- wreg (372,00007) a=000d(c0.r5 ) d=000000 s=00110000! OK -- wreg (002,00007) a=000e(c0.sp ) d=001000 s=00110000! OK -- wreg (012,00007) a=0001(c0.cntl ) d=000002 s=00100000! OK -- wreg (022,00007) a=0001(c0.cntl ) d=000004 s=00100000! OK -- wreg (032,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (042,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:14.100853 : ATTN notify apat = 0001 lams = 0 dt=0.253206 ++ attn (255,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.023 OK ++ rreg (120,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C4.2: super dw break on mtpd (pm=user) -> no bpt -- ++ wreg (052,00017) a=0050(c0.hb0.cntl ) d=000022 s=00000000! OK -- wreg (062,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (072,00007) a=0052(c0.hb0.hilim) d=001054 s=00000000! OK -- wreg (102,00027) a=0053(c0.hb0.lolim) d=001054 s=00000000! OK ++ wreg (112,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (122,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (202,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (212,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (222,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (232,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:14.335339 : ATTN notify apat = 0001 lams = 0 dt=0.234486 ++ attn (265,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.023 OK ++ rreg (130,00037) a=000f(c0.pc ) d=001046! s=00000000! OK # C4.3: user dw break on mtpd (pm=user) -> bpt ----- ++ wreg (242,00017) a=0050(c0.hb0.cntl ) d=000062 s=00000000! OK -- wreg (252,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (262,00007) a=0052(c0.hb0.hilim) d=001054 s=00000000! OK -- wreg (272,00027) a=0053(c0.hb0.lolim) d=001054 s=00000000! OK ++ wreg (302,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (312,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (352,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (362,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (372,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (002,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (012,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (022,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:14.567070 : ATTN notify apat = 0001 lams = 0 dt=0.231731 ++ attn (275,00037) d=000001 s=00110000! OK -- wtcpu to=10.000 T=0.020 OK ++ rreg (140,00017) a=0051(c0.hb0.stat ) d=000002! s=00110000! OK -- rreg (150,00007) a=0002(c0.stat ) d=000554! s=00110000! OK -- rreg (160,00027) a=000f(c0.pc ) d=001042! s=00110000! OK ++ wreg (032,00017) a=0001(c0.cntl ) d=000002 s=00100000! OK -- wreg (042,00027) a=0001(c0.cntl ) d=000004 s=00100000! OK ++ wreg (052,00017) a=0050(c0.hb0.cntl ) d=000000 s=00000000! OK -- wreg (062,00007) a=0051(c0.hb0.stat ) d=000000 s=00000000! OK -- wreg (072,00007) a=0052(c0.hb0.hilim) d=000000 s=00000000! OK -- wreg (102,00027) a=0053(c0.hb0.lolim) d=000000 s=00000000! OK test_hbpt_basics.tcl: PASS @w11a_hbpt/w11a_hbpt_all.dat: PASS ## steering file for all w11a_pcnt tests # test_pcnt_regs: test register response ------------------------------ # A basic register access tests ----------------------------- # A1: write cntl, read stat -------------------------- ++ wreg (112,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- rreg (170,00007) a=0061(c0.pc.stat ) d=000000! s=00000000! OK -- wreg (122,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- rreg (200,00007) a=0061(c0.pc.stat ) d=000001! s=00000000! OK -- wreg (132,00007) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- rreg (210,00007) a=0061(c0.pc.stat ) d=000000! s=00000000! OK -- rreg (220,00027) a=0060(c0.pc.cntl ) d=000001 s=00000000! OK ++ wreg (142,00017) a=0060(c0.pc.cntl ) d=007007 s=00000000! OK -- rreg (230,00007) a=0061(c0.pc.stat ) d=007000! s=00000000! OK -- wreg (152,00007) a=0060(c0.pc.cntl ) d=127007 s=00000000! OK -- rreg (240,00007) a=0061(c0.pc.stat ) d=127000! s=00000000! OK -- wreg (162,00007) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- rreg (250,00027) a=0061(c0.pc.stat ) d=000000! s=00000000! OK # A2: test err when written -------------------------- ++ wreg (172,00017) a=0061(c0.pc.stat ) d=000400 s=00000001| OK -- wreg (202,00027) a=0062(c0.pc.data ) d=000400 s=00000001| OK test_pcnt_regs.tcl: PASS # test_pcnt_basics: test basic functionality -------------------------- # A: simple loop code --------------------------------------- ++ wreg (212,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (233,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 005001 012700 000040 005201 077002 000000 # A1: run code, with pcnt running -------------------- ++ wreg (222,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (232,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- rreg (260,00027) a=0061(c0.pc.stat ) d=000001! s=00000000! OK ++ wreg (242,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (252,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (332,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (342,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (352,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (362,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:15.210353 : ATTN notify apat = 0001 lams = 0 dt=0.643282 ++ attn (305,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.077 OK ++ rreg (270,00037) a=000f(c0.pc ) d=001014! s=00000000! OK ++ rreg (300,00017) a=0008(c0.r0 ) d=000000! s=00000000! OK -- rreg (310,00027) a=0009(c0.r1 ) d=000040! s=00000000! OK ++ wreg (372,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- rreg (320,00027) a=0061(c0.pc.stat ) d=000000! s=00000000! OK # A2: test random access (ainc=0) -------------------- ++ wreg (002,00017) a=0060(c0.pc.cntl ) d=006007 s=00000000! OK -- rreg (330,00007) a=0061(c0.pc.stat ) d=006000! s=00000000! OK -- rreg (340,00007) a=0062(c0.pc.data ) d=000103! s=00000000! OK -- rreg (350,00007) a=0061(c0.pc.stat ) d=006400! s=00000000! OK -- rreg (360,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (370,00007) a=0061(c0.pc.stat ) d=006000! s=00000000! OK -- rreg (000,00007) a=0062(c0.pc.data ) d=000103! s=00000000! OK -- rreg (010,00007) a=0061(c0.pc.stat ) d=006400! s=00000000! OK -- rreg (020,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (030,00007) a=0061(c0.pc.stat ) d=006000! s=00000000! OK -- wreg (012,00007) a=0060(c0.pc.cntl ) d=011007 s=00000000! OK -- rreg (040,00007) a=0061(c0.pc.stat ) d=011000! s=00000000! OK -- rreg (050,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- wreg (022,00007) a=0060(c0.pc.cntl ) d=007007 s=00000000! OK -- rreg (060,00007) a=0061(c0.pc.stat ) d=007000! s=00000000! OK -- rreg (070,00007) a=0062(c0.pc.data ) d=000037! s=00000000! OK -- rreg (100,00007) a=0061(c0.pc.stat ) d=007400! s=00000000! OK -- rreg (110,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (120,00027) a=0061(c0.pc.stat ) d=007000! s=00000000! OK # A3: test sequential access (ainc=1) ---------------- ++ wreg (032,00017) a=0060(c0.pc.cntl ) d=106007 s=00000000! OK -- rreg (130,00007) a=0061(c0.pc.stat ) d=106000! s=00000000! OK -- rreg (140,00007) a=0062(c0.pc.data ) d=000103! s=00000000! OK -- rreg (150,00007) a=0061(c0.pc.stat ) d=106400! s=00000000! OK -- rreg (160,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (170,00007) a=0061(c0.pc.stat ) d=107000! s=00000000! OK -- rreg (200,00007) a=0062(c0.pc.data ) d=000037! s=00000000! OK -- rreg (210,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (220,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (230,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (240,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (250,00007) a=0061(c0.pc.stat ) d=111400! s=00000000! OK -- rreg (260,00007) a=0062(c0.pc.data ) d=000000! s=00000000! OK -- rreg (270,00027) a=0061(c0.pc.stat ) d=112000! s=00000000! OK # A3: test block access (ainc=1) --------------------- ++ wreg (042,00017) a=0060(c0.pc.cntl ) d=103007 s=00000000! OK -- rreg (300,00007) a=0061(c0.pc.stat ) d=103000! s=00000000! OK -- rblk (151,00007) a=0062(c0.pc.data ) n= 14= 14 s=00000000! OK 0: 000000! 000000! 000000! 000000! 000000! 000000! 000103! 000000! 8: 000037! 000000! 000000! 000000! 000000! 000000! -- rreg (310,00027) a=0061(c0.pc.stat ) d=112000! s=00000000! OK ++ wreg (052,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (062,00007) a=0060(c0.pc.cntl ) d=103007 s=00000000! OK -- rreg (320,00007) a=0061(c0.pc.stat ) d=103000! s=00000000! OK -- rblk (161,00007) a=0062(c0.pc.data ) n= 14= 14 s=00000000! OK 0: 000000! 000000! 000000! 000000! 000000! 000000! 000000! 000000! 8: 000000! 000000! 000000! 000000! 000000! 000000! -- rreg (330,00027) a=0061(c0.pc.stat ) d=112000! s=00000000! OK test_pcnt_basics.tcl: PASS # test_pcnt_codes: test counters -------------------------------------- # A: rbus and ibus counters --------------------------------- # A1: rbus write ------------------------------------- ++ wreg (072,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (102,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (112,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- wreg (122,00007) a=0004(c0.al ) d=002000 s=00000000! OK -- wblk (243,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000200 000201 000202 000203 000204 000205 000206 000207 8: 000210 000211 000212 000213 000214 000215 000216 000217 -- wreg (132,00027) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK ++ wreg (142,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (152,00007) a=0060(c0.pc.cntl ) d=125007 s=00000000! OK -- rreg (340,00007) a=0061(c0.pc.stat ) d=125000! s=00000000! OK -- rblk (171,00027) a=0062(c0.pc.data ) n= 4= 4 s=00000000! OK 0: 000000 000000 000022 000000 # A2: rbus read -------------------------------------- ++ wreg (162,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (172,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- wreg (202,00007) a=0004(c0.al ) d=002000 s=00000000! OK -- rblk (201,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000200! 000201! 000202! 000203! 000204! 000205! 000206! 000207! 8: 000210! 000211! 000212! 000213! 000214! 000215! 000216! 000217! -- wreg (212,00027) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK ++ wreg (222,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (232,00007) a=0060(c0.pc.cntl ) d=125007 s=00000000! OK -- rreg (350,00007) a=0061(c0.pc.stat ) d=125000! s=00000000! OK -- rblk (211,00027) a=0062(c0.pc.data ) n= 4= 4 s=00000000! OK 0: 000020 000000 000002 000000 # A3: ibus via rbus write ---------------------------- ++ wreg (242,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (252,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (262,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- wreg (272,00007) a=0004(c0.al ) d=177640 s=00000000! OK -- wblk (253,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000200 000201 000202 000203 000204 000205 000206 000207 8: 000210 000211 000212 000213 000214 000215 000216 000217 -- wreg (302,00027) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK ++ wreg (312,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (322,00007) a=0060(c0.pc.cntl ) d=122007 s=00000000! OK -- rreg (360,00007) a=0061(c0.pc.stat ) d=122000! s=00000000! OK -- rblk (221,00027) a=0062(c0.pc.data ) n= 10= 10 s=00000000! OK 0: 000000 000000 000020 000000 000000 000000 000000 000000 8: 000022 000000 # A4: ibus via rbus read ----------------------------- ++ wreg (332,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (342,00007) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK -- wreg (352,00007) a=0004(c0.al ) d=177640 s=00000000! OK -- rblk (231,00007) a=0007(c0.memi ) n= 16= 16 s=00000000! OK 0: 000200! 000201! 000202! 000203! 000204! 000205! 000206! 000207! 8: 000210! 000211! 000212! 000213! 000214! 000215! 000216! 000217! -- wreg (362,00027) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK ++ wreg (372,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (002,00007) a=0060(c0.pc.cntl ) d=122007 s=00000000! OK -- rreg (370,00007) a=0061(c0.pc.stat ) d=122000! s=00000000! OK -- rblk (241,00027) a=0062(c0.pc.data ) n= 10= 10 s=00000000! OK 0: 000020 000000 000000 000000 000000 000000 000020 000000 8: 000002 000000 # B: plain kernel mode codes -------------------------------- # B1: plain sob loop --------------------------------- ++ wreg (012,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (022,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (263,00027) a=0007(c0.memi ) n= 4= 4 s=00000000! OK 0: 012700 000040 077001 000000 ++ wreg (032,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (042,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (052,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (062,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (072,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (102,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (112,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (122,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (142,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (152,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (162,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (172,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:16.952075 : ATTN notify apat = 0001 lams = 0 dt=1.741723 ++ attn (315,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.050 OK ++ rreg (000,00037) a=000f(c0.pc ) d=001010! s=00000000! OK ++ wreg (202,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (212,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (010,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (251,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000251 000000 000000 000000 000000 000000 8: 000000 000000 000042 000000 000037 000000 000000 000000 16: 000000 000000 000043 000000 000000 000000 000043 000000 24: 000000 000000 000000 000000 000000 000000 # B2: sob + inc R loop ------------------------------- ++ wreg (222,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (232,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (273,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 012700 000040 005001 005201 077002 000000 ++ wreg (242,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (252,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (262,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (272,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (312,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (352,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (362,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (372,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (002,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:17.492368 : ATTN notify apat = 0001 lams = 0 dt=0.540292 ++ attn (325,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.077 OK ++ rreg (020,00037) a=000f(c0.pc ) d=001014! s=00000000! OK ++ wreg (012,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (022,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (030,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (261,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000353 000000 000000 000000 000000 000000 8: 000000 000000 000103 000000 000037 000000 000000 000000 16: 000000 000000 000104 000000 000000 000000 000104 000000 24: 000000 000000 000000 000000 000000 000000 # B3: sob + inc mem loop ----------------------------- ++ wreg (032,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (042,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (303,00027) a=0007(c0.memi ) n= 9= 9 s=00000000! OK 0: 012700 000040 005067 000010 005267 000004 077003 000000 8: 000000 ++ wreg (052,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (062,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (072,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (102,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (112,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (122,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (162,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (172,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (202,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (212,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:18.117032 : ATTN notify apat = 0001 lams = 0 dt=0.624665 ++ attn (335,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.152 OK ++ rreg (040,00037) a=000f(c0.pc ) d=001020! s=00000000! OK ++ wreg (222,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (232,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (050,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (271,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000720 000000 000000 000000 000000 000000 8: 000000 000000 000103 000000 000037 000000 000000 000000 16: 000000 000000 000205 000000 000041 000000 000205 000000 24: 000041 000000 000000 000000 000041 000000 # B4: dec+bne+inc @#ibus loop (test ibus access) ----- ++ wreg (242,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (252,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (313,00027) a=0007(c0.memi ) n= 10= 10 s=00000000! OK 0: 012700 000040 005037 177660 005237 177660 005300 001374 8: 000000 000000 ++ wreg (262,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (272,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (302,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (312,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (322,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (332,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (352,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (362,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (372,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (002,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (012,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (022,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:18.804479 : ATTN notify apat = 0001 lams = 0 dt=0.687445 ++ attn (345,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.201 OK ++ rreg (060,00037) a=000f(c0.pc ) d=001022! s=00000000! OK ++ wreg (032,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (042,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (070,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (301,00027) a=0062(c0.pc.data ) n= 38= 38 s=00000000! OK 0: 000000 000000 001122 000000 000000 000000 000000 000000 8: 000000 000000 000143 000000 000037 000000 000000 000000 16: 000000 000000 000205 000000 000000 000000 000205 000000 24: 000000 000000 000000 000000 000000 000000 000000 000000 32: 000000 000000 000040 000000 000041 000000 # C: test kern pri>0, super and user mode ------------------- # C1: kernel pri > 0 --------------------------------- ++ wreg (052,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (062,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (323,00027) a=0007(c0.memi ) n= 11= 11 s=00000000! OK 0: 012737 000340 177776 000240 000240 000240 000240 012737 8: 000000 177776 000000 ++ wreg (072,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (102,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (112,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (122,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (132,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (142,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (202,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (212,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (222,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (232,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:19.326799 : ATTN notify apat = 0001 lams = 0 dt=0.522323 ++ attn (355,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.011 OK ++ rreg (100,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ wreg (242,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (252,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (110,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (311,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000033 000000 000020 000000 000000 000000 000000 000000 8: 000000 000000 000007 000000 000000 000000 000000 000000 16: 000000 000000 000013 000000 000000 000000 000013 000000 24: 000000 000000 000000 000000 000000 000000 # C2: supervisor mode -------------------------------- ++ wreg (262,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (272,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (333,00027) a=0007(c0.memi ) n= 11= 11 s=00000000! OK 0: 012737 040000 177776 000240 000240 000240 000240 012737 8: 000000 177776 000000 ++ wreg (302,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (312,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (322,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (332,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (342,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (352,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (362,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (372,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (012,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (022,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (032,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (042,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:19.822839 : ATTN notify apat = 0001 lams = 0 dt=0.496040 ++ attn (365,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.012 OK ++ rreg (120,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ wreg (052,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (062,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (130,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (321,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000020 000000 000000 000000 000033 000000 8: 000000 000000 000007 000000 000000 000000 000000 000000 16: 000000 000000 000013 000000 000000 000000 000013 000000 24: 000000 000000 000000 000000 000000 000000 # C3: user mode -------------------------------------- ++ wreg (072,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (102,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (343,00027) a=0007(c0.memi ) n= 11= 11 s=00000000! OK 0: 012737 140000 177776 000240 000240 000240 000240 012737 8: 000000 177776 000000 ++ wreg (112,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (122,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (132,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (142,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (152,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (162,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (172,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (202,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (212,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (222,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (232,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (242,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (252,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:20.319208 : ATTN notify apat = 0001 lams = 0 dt=0.496368 ++ attn (375,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.012 OK ++ rreg (140,00037) a=000f(c0.pc ) d=001026! s=00000000! OK ++ wreg (262,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (272,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (150,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (331,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000020 000000 000000 000000 000000 000000 8: 000033 000000 000007 000000 000000 000000 000000 000000 16: 000000 000000 000013 000000 000000 000000 000013 000000 24: 000000 000000 000000 000000 000000 000000 # D: test vector fetch -------------------------------------- # D1: vector via trap instruction -------------------- ++ wreg (302,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (312,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wblk (353,00027) a=0007(c0.memi ) n= 14= 14 s=00000000! OK 0: 000006 000000 000012 000000 000016 000000 000022 000000 8: 000026 000000 000032 000000 000036 000000 ++ wreg (322,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (363,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 000242 000000 000246 000000 000252 000000 ++ wreg (332,00017) a=0004(c0.al ) d=001000 s=00000000! OK -- wblk (373,00027) a=0007(c0.memi ) n= 15= 15 s=00000000! OK 0: 012737 001030 000034 012737 001032 000030 005000 104401 8: 104001 104402 104002 000000 000002 005200 000002 ++ wreg (342,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (352,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (362,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (372,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (002,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (012,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (022,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (032,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (042,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (052,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (062,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (072,00007) a=000f(c0.pc ) d=001000 s=00000000! OK -- wreg (102,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:21.014482 : ATTN notify apat = 0001 lams = 0 dt=0.695274 ++ attn (005,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.040 OK ++ rreg (160,00037) a=000f(c0.pc ) d=001030! s=00000000! OK ++ wreg (112,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (122,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (170,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (341,00027) a=0062(c0.pc.data ) n= 30= 30 s=00000000! OK 0: 000000 000000 000165 000000 000000 000000 000000 000000 8: 000000 000000 000016 000000 000010 000000 000004 000000 16: 000000 000000 000042 000000 000012 000000 000042 000000 24: 000012 000000 000000 000000 000012 000000 # E: test interrupts (via kw11p if avaialable) -------------- ++ wreg (132,00037) a=0001(c0.cntl ) d=000004 s=00000000! OK ++ wreg (142,00017) a=0004(c0.al ) d=000004 s=00000000! OK -- wblk (003,00027) a=0007(c0.memi ) n= 14= 14 s=00000000! OK 0: 000006 000000 000012 000000 000016 000000 000022 000000 8: 000026 000000 000032 000000 000036 000000 ++ wreg (152,00017) a=0004(c0.al ) d=000104 s=00000000! OK -- wblk (013,00027) a=0007(c0.memi ) n= 2= 2 s=00000000! OK 0: 002034 000340 ++ wreg (162,00017) a=0004(c0.al ) d=000240 s=00000000! OK -- wblk (023,00027) a=0007(c0.memi ) n= 6= 6 s=00000000! OK 0: 000242 000000 000246 000000 000252 000000 ++ wreg (172,00017) a=0004(c0.al ) d=002000 s=00000000! OK -- wblk (033,00027) a=0007(c0.memi ) n= 18= 18 s=00000000! OK 0: 000237 012701 000003 012737 000024 172542 012737 000117 8: 172540 000230 012700 000106 077001 000000 005301 001401 16: 000002 000000 ++ wreg (202,00017) a=0060(c0.pc.cntl ) d=000006 s=00000000! OK -- wreg (212,00027) a=0060(c0.pc.cntl ) d=000005 s=00000000! OK ++ wreg (222,00017) a=0008(c0.r0 ) d=000000 s=00000000! OK -- wreg (232,00007) a=0009(c0.r1 ) d=000000 s=00000000! OK -- wreg (242,00007) a=000a(c0.r2 ) d=000000 s=00000000! OK -- wreg (252,00007) a=000b(c0.r3 ) d=000000 s=00000000! OK -- wreg (262,00007) a=000c(c0.r4 ) d=000000 s=00000000! OK -- wreg (272,00007) a=000d(c0.r5 ) d=000000 s=00000000! OK -- wreg (302,00007) a=000e(c0.sp ) d=001000 s=00000000! OK -- wreg (312,00007) a=0001(c0.cntl ) d=000002 s=00000000! OK -- wreg (322,00007) a=0001(c0.cntl ) d=000004 s=00000000! OK -- wreg (332,00007) a=000f(c0.pc ) d=002000 s=00000000! OK -- wreg (342,00027) a=0001(c0.cntl ) d=000001 s=00010000! OK -I- 16:36:21.779783 : ATTN notify apat = 0001 lams = 0 dt=0.765302 ++ attn (015,00037) d=000001 s=00000000! OK -- wtcpu to=10.000 T=0.045 OK ++ rreg (200,00037) a=000f(c0.pc ) d=002044! s=00000000! OK ++ wreg (352,00017) a=0060(c0.pc.cntl ) d=000004 s=00000000! OK -- wreg (362,00007) a=0060(c0.pc.cntl ) d=101007 s=00000000! OK -- rreg (210,00007) a=0061(c0.pc.stat ) d=101000! s=00000000! OK -- rblk (351,00027) a=0062(c0.pc.data ) n= 18= 18 s=00000000! OK 0: 000123 000000 000055 000000 000000 000000 000000 000000 8: 000000 000000 000022 000000 000011 000000 000003 000000 16: 000003 000000 test_pcnt_codes.tcl: PASS @w11a_pcnt/w11a_pcnt_all.dat: PASS @cpu_all.dat: PASS rlink_cext-I: seen EOF, schedule clock stop and exit 3474551.6 ns 416921: DONE ../../../../vlib/rlink/tbcore/tbcore_rlink.vhd:285:5:@3474651666660fs:(report failure): Simulation Finished tb_w11a_arty:error: report failed in process .tb_arty_dram(sim).tbcore@tbcore_rlink(sim).proc_stim real 0m55.745s user 0m1.279s sys 0m0.310s from: process work.tbcore_rlink(sim).proc_stim at tbcore_rlink.vhd:271 tb_w11a_arty:error: simulation failed