tbw-I: create FIFO rlink_cext_fifo_tx
tbw-I: define rlink_cext_conf -> rlink_cext_conf_tmp.tmp
tbw-I: define sysmon_stim -> ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat
../../src/ieee/numeric_std-body.v93:1558:7:@0ms:(assertion warning): NUMERIC_STD.">=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1406:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:1309:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1157:7:@0ms:(assertion warning): NUMERIC_STD."<": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1309:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1157:7:@0ms:(assertion warning): NUMERIC_STD."<": metavalue detected, returning FALSE
../../src/synopsys/std_logic_arith.vhdl:2081:12:@0ms:(assertion warning): CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1710:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1558:7:@0ms:(assertion warning): NUMERIC_STD.">=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1406:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
rlink_cext-I: connected to rlink_cext_fifo_rx
rlink_cext-I: connected to rlink_cext_fifo_tx
++ rreg (000,00017) a=fffe() d=ff02 s=00! OK
-- rreg (010,00007) a=fffd() d=0201 s=00! OK
-- rreg (020,00007) a=fffc() d=0600 s=00! OK
-- rreg (030,00007) a=fffb() d=0000 s=00 OK
-- rreg (040,00007) a=fffa() d=0000 s=00 OK
-- rreg (050,00027) a=ffe8() d=0000 s=02 OK
# .wait 5
# C cmderr
# C |cmdmerr
# C ||cpususp
# C |||cpugo
# C ||||attention flags set
# C |||||rbtout
# C ||||||rbnak
# C |||||||rberr
# C ||||||||
# C 00000000
# C
# C cmd addr ----stat ------------data ---check---
# C
# C ----------------------------------------------------------------------------
# C write registers
++ wreg (002,00017) a=0008(r0 ) d=000001 s=00000000| OK
-- wreg (012,00007) a=0009(r1 ) d=000101 s=00000000| OK
-- wreg (022,00007) a=000a(r2 ) d=000201 s=00000000| OK
-- wreg (032,00007) a=000b(r3 ) d=000301 s=00000000| OK
-- wreg (042,00007) a=000c(r4 ) d=000401 s=00000000| OK
-- wreg (052,00007) a=000d(r5 ) d=000501 s=00000000| OK
-- wreg (062,00007) a=000e(sp ) d=000601 s=00000000| OK
-- wreg (072,00027) a=000f(pc ) d=000701 s=00000000| OK
# C ---------------------------------------------------------------------------
# C read registers
++ rreg (060,00017) a=0008(r0 ) d=000001! s=00000000| OK
-- rreg (070,00007) a=0009(r1 ) d=000101! s=00000000| OK
-- rreg (100,00007) a=000a(r2 ) d=000201! s=00000000| OK
-- rreg (110,00007) a=000b(r3 ) d=000301! s=00000000| OK
-- rreg (120,00007) a=000c(r4 ) d=000401! s=00000000| OK
-- rreg (130,00007) a=000d(r5 ) d=000501! s=00000000| OK
-- rreg (140,00007) a=000e(sp ) d=000601! s=00000000| OK
-- rreg (150,00027) a=000f(pc ) d=000701! s=00000000| OK
# C ---------------------------------------------------------------------------
# C write memory (via wreg, use wreg/memi)
++ wreg (102,00017) a=0004(al ) d=002000 s=00000000| OK
-- wreg (112,00007) a=0007(memi ) d=007700 s=00000000| OK
-- wreg (122,00007) a=0007(memi ) d=007710 s=00000000| OK
-- wreg (132,00007) a=0007(memi ) d=007720 s=00000000| OK
-- wreg (142,00027) a=0007(memi ) d=007730 s=00000000| OK
# C ----------------------------------------------------------------------------
# C read memory (via rreg, use rreg/memi)
++ wreg (152,00017) a=0004(al ) d=002000 s=00000000| OK
-- rreg (160,00007) a=0007(memi ) d=007700! s=00000000| OK
-- rreg (170,00007) a=0007(memi ) d=007710! s=00000000| OK
-- rreg (200,00007) a=0007(memi ) d=007720! s=00000000| OK
-- rreg (210,00027) a=0007(memi ) d=007730! s=00000000| OK
# C ----------------------------------------------------------------------------
# C write memory (via wblk)
++ wreg (162,00017) a=0004(al ) d=002010 s=00000000| OK
-- wblk (003,00027) a=0007(memi ) n= 4= 4! s=00000000| OK
0: 007740 007750 007760 007770
# C ----------------------------------------------------------------------------
# C read memory (via rblk)
++ wreg (172,00017) a=0004(al ) d=002000 s=00000000| OK
-- rblk (001,00027) a=0007(memi ) n= 8= 8! s=00000000| OK
0: 007700! 007710! 007720! 007730! 007740! 007750! 007760! 007770!
# C ----------------------------------------------------------------------------
# C read/write PSW via various mechanisms
# C via wps/rps
++ wreg (202,00017) a=0003(psw ) d=000017 s=00000000| OK
-- rreg (220,00007) a=0003(psw ) d=000017! s=00000000| OK
-- wreg (212,00007) a=0003(psw ) d=000000 s=00000000| OK
-- rreg (230,00027) a=0003(psw ) d=000000! s=00000000| OK
# C via 16bit cp addressing (al 177776)
++ wreg (222,00017) a=0004(al ) d=177776 s=00000000| OK
-- wreg (232,00007) a=0006(mem ) d=000017 s=00000000| OK
-- rreg (240,00007) a=0006(mem ) d=000017! s=00000000| OK
-- rreg (250,00007) a=0003(psw ) d=000017! s=00000000| OK
-- wreg (242,00007) a=0006(mem ) d=000000 s=00000000| OK
-- rreg (260,00007) a=0006(mem ) d=000000! s=00000000| OK
-- rreg (270,00027) a=0003(psw ) d=000000! s=00000000| OK
# C via 22bit cp addressing (al 177776; ah 177)
++ wreg (252,00017) a=0004(al ) d=177776 s=00000000| OK
-- wreg (262,00007) a=0005(ah ) d=000177 s=00000000| OK
-- wreg (272,00007) a=0006(mem ) d=000017 s=00000000| OK
-- rreg (300,00007) a=0006(mem ) d=000017! s=00000000| OK
-- rreg (310,00007) a=0003(psw ) d=000017! s=00000000| OK
-- wreg (302,00007) a=0006(mem ) d=000000 s=00000000| OK
-- rreg (320,00007) a=0006(mem ) d=000000! s=00000000| OK
-- rreg (330,00027) a=0003(psw ) d=000000! s=00000000| OK
# C ----------------------------------------------------------------------------
# C write register set 1, sm,um stack
++ wreg (312,00017) a=0003(psw ) d=004000 s=00000000| OK
-- wreg (322,00007) a=0008(r0 ) d=010001 s=00000000| OK
-- wreg (332,00007) a=0009(r1 ) d=010101 s=00000000| OK
-- wreg (342,00007) a=000a(r2 ) d=010201 s=00000000| OK
-- wreg (352,00007) a=000b(r3 ) d=010301 s=00000000| OK
-- wreg (362,00007) a=000c(r4 ) d=010401 s=00000000| OK
-- wreg (372,00007) a=000d(r5 ) d=010501 s=00000000| OK
-- wreg (002,00007) a=0003(psw ) d=044000 s=00000000| OK
-- wreg (012,00007) a=000e(sp ) d=010601 s=00000000| OK
-- wreg (022,00007) a=0003(psw ) d=144000 s=00000000| OK
-- wreg (032,00027) a=000e(sp ) d=110601 s=00000000| OK
# C ----------------------------------------------------------------------------
# C read all registers set 0/1, km,sm,um stack
++ wreg (042,00017) a=0003(psw ) d=000000 s=00000000| OK
-- rreg (340,00007) a=0008(r0 ) d=000001! s=00000000| OK
-- rreg (350,00007) a=0009(r1 ) d=000101! s=00000000| OK
-- rreg (360,00007) a=000a(r2 ) d=000201! s=00000000| OK
-- rreg (370,00007) a=000b(r3 ) d=000301! s=00000000| OK
-- rreg (000,00007) a=000c(r4 ) d=000401! s=00000000| OK
-- rreg (010,00007) a=000d(r5 ) d=000501! s=00000000| OK
-- rreg (020,00007) a=000e(sp ) d=000601! s=00000000| OK
-- rreg (030,00007) a=000f(pc ) d=000701! s=00000000| OK
-- wreg (052,00007) a=0003(psw ) d=040000 s=00000000| OK
-- rreg (040,00007) a=000e(sp ) d=010601! s=00000000| OK
-- wreg (062,00007) a=0003(psw ) d=140000 s=00000000| OK
-- rreg (050,00007) a=000e(sp ) d=110601! s=00000000| OK
-- wreg (072,00007) a=0003(psw ) d=144000 s=00000000| OK
-- rreg (060,00007) a=0008(r0 ) d=010001! s=00000000| OK
-- rreg (070,00007) a=0009(r1 ) d=010101! s=00000000| OK
-- rreg (100,00007) a=000a(r2 ) d=010201! s=00000000| OK
-- rreg (110,00007) a=000b(r3 ) d=010301! s=00000000| OK
-- rreg (120,00007) a=000c(r4 ) d=010401! s=00000000| OK
-- rreg (130,00007) a=000d(r5 ) d=010501! s=00000000| OK
-- wreg (102,00027) a=0003(psw ) d=000000 s=00000000| OK
# C ----------------------------------------------------------------------------
# C write,read IB space: : MMU SAR supervisor mode (16 bit regs)
++ wreg (112,00017) a=0004(al ) d=172240 s=00000000| OK
-- wreg (122,00007) a=0007(memi ) d=012340 s=00000000| OK
-- wreg (132,00007) a=0007(memi ) d=012342 s=00000000| OK
-- wreg (142,00007) a=0007(memi ) d=012344 s=00000000| OK
-- wreg (152,00007) a=0004(al ) d=172240 s=00000000| OK
-- rreg (140,00007) a=0007(memi ) d=012340! s=00000000| OK
-- rreg (150,00007) a=0007(memi ) d=012342! s=00000000| OK
-- rreg (160,00027) a=0007(memi ) d=012344! s=00000000| OK
# C ----------------------------------------------------------------------------
# C load simple test code 1: '1$:inc r1; sob r0,1$; halt'
++ wreg (162,00017) a=0004(al ) d=002100 s=00000000| OK
-- wreg (172,00007) a=0007(memi ) d=005201 s=00000000| OK
-- wreg (202,00007) a=0007(memi ) d=077002 s=00000000| OK
-- wreg (212,00027) a=0007(memi ) d=000000 s=00000000| OK
# C exec test code 1 w/ r0=2; wait 50 cycle; test regs
++ wreg (222,00017) a=0008(r0 ) d=000002 s=00000000| OK
-- wreg (232,00007) a=0009(r1 ) d=000000 s=00000000| OK
-- wreg (242,00007) a=000f(pc ) d=002100 s=00000000| OK
-- wreg (252,00027) a=0001(cntl ) d=000001 s=00010000| OK
# .wait 50
++ rreg (170,00017) a=0008(r0 ) d=000000! s=00001000| OK
-- rreg (200,00007) a=0009(r1 ) d=000002! s=00001000| OK
-- rreg (210,00007) a=000f(pc ) d=002106! s=00001000| OK
-- attn (005,00007) d=000001! s=00000000| OK
-- wreg (262,00027) a=0001(cntl ) d=000004 s=00000000| OK
# C ----------------------------------------------------------------------------
# C single step through test code 1
++ wreg (272,00017) a=0008(r0 ) d=000003 s=00000000| OK
-- wreg (302,00007) a=0009(r1 ) d=000000 s=00000000| OK
-- wreg (312,00007) a=000f(pc ) d=002100 s=00000000| OK
-- wreg (322,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- rreg (220,00007) a=0008(r0 ) d=000003! s=00000000| OK
-- rreg (230,00007) a=0009(r1 ) d=000001! s=00000000| OK
-- rreg (240,00007) a=000f(pc ) d=002102! s=00000000| OK
-- wreg (332,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- rreg (250,00007) a=0008(r0 ) d=000002! s=00000000| OK
-- rreg (260,00007) a=0009(r1 ) d=000001! s=00000000| OK
-- rreg (270,00007) a=000f(pc ) d=002100! s=00000000| OK
-- wreg (342,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- wreg (352,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- rreg (300,00007) a=0008(r0 ) d=000001! s=00000000| OK
-- rreg (310,00007) a=0009(r1 ) d=000002! s=00000000| OK
-- rreg (320,00027) a=000f(pc ) d=002100! s=00000000| OK
# C ----------------------------------------------------------------------------
# C execute code 1, test stat command while it runs
++ wreg (362,00017) a=0008(r0 ) d=000005 s=00000000| OK
-- wreg (372,00007) a=0009(r1 ) d=000000 s=00000000| OK
-- wreg (002,00007) a=000f(pc ) d=002100 s=00000000| OK
-- wreg (012,00007) a=0001(cntl ) d=000001 s=00010000| OK
-- rreg (330,00007) a=0002(stat ) d=000164 s=00010000 OK
-- rreg (340,00007) a=0002(stat ) d=000020 s=00001000 OK
-- rreg (350,00007) a=0002(stat ) d=000020 s=00001000 OK
-- rreg (360,00007) a=0002(stat ) d=000020 s=00001000 OK
-- rreg (370,00007) a=0002(stat ) d=000020 s=00001000 OK
-- rreg (000,00007) a=0002(stat ) d=000020! s=00001000| OK
-- rreg (010,00007) a=0008(r0 ) d=000000! s=00001000| OK
-- rreg (020,00007) a=0009(r1 ) d=000005! s=00001000| OK
-- rreg (030,00007) a=000f(pc ) d=002106! s=00001000| OK
-- attn (015,00007) d=000001! s=00000000| OK
-- wreg (022,00007) a=0001(cntl ) d=000004 s=00000000| OK
-- rreg (040,00027) a=0002(stat ) d=000000! s=00000000| OK
# C ----------------------------------------------------------------------------
# C execute code 1, look for attn comma to happen
++ wreg (032,00017) a=ffff( ) d=100000 s=00000000| OK
-- wreg (042,00007) a=0008(r0 ) d=000005 s=00000000| OK
-- wreg (052,00007) a=0009(r1 ) d=000000 s=00000000| OK
-- wreg (062,00007) a=000f(pc ) d=002100 s=00000000| OK
-- wreg (072,00027) a=0001(cntl ) d=000001 s=00010000| OK
-+- 2018-12-20 -+-
-I- 08:32:38.907354 : ATTN notify apat = 0001 lams = 0
-- wtlam apat=0001 to=10.000 T=0.008 OK
++ rreg (050,00017) a=0002(stat ) d=000020! s=00001000| OK
-- rreg (060,00007) a=0008(r0 ) d=000000! s=00001000| OK
-- rreg (070,00007) a=0009(r1 ) d=000005! s=00001000| OK
-- rreg (100,00007) a=000f(pc ) d=002106! s=00001000| OK
-- attn (025,00007) d=000001! s=00000000| OK
-- wreg (102,00007) a=0001(cntl ) d=000004 s=00000000| OK
-- rreg (110,00027) a=0002(stat ) d=000000! s=00000000| OK
# C ----------------------------------------------------------------------------
# C load test code 2 for single step testing of 'slow' instructions
++ wreg (112,00017) a=0004(al ) d=002200 s=00000000| OK
-- wblk (013,00027) a=0007(memi ) n= 13= 13! s=00000000| OK
0: 067070 000000 000006 067070 000002 000006 067070 000004
8: 000006 067070 000000 000006 000000
++ wreg (122,00017) a=0004(al ) d=002240 s=00000000| OK
-- wblk (023,00027) a=0007(memi ) n= 12= 12! s=00000000| OK
0: 002260 002262 002264 002266 000001 177777 157255 137257
8: 000010 000100 001000 000001
# C ----------------------------------------------------------------------------
# C single step through test code 2
++ wreg (132,00017) a=000f(pc ) d=002200 s=00000000| OK
-- wreg (142,00007) a=0008(r0 ) d=002240 s=00000000| OK
-- wreg (152,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- wreg (162,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- wreg (172,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- rreg (120,00007) a=0008(r0 ) d=002240! s=00000000| OK
-- rreg (130,00007) a=000f(pc ) d=002222! s=00000000| OK
-- wreg (202,00007) a=0004(al ) d=002240 s=00000000| OK
-- rblk (011,00027) a=0007(memi ) n= 12= 12! s=00000000| OK
0: 002260- 002262- 002264- 002266- 000001! 177777! 157255! 137257!
8: 000010! 000100! 001000! 001111!
++ wreg (212,00017) a=0001(cntl ) d=000003 s=00000000| OK
-- wreg (222,00007) a=0001(cntl ) d=000003 s=00000000| OK
-- rreg (140,00007) a=000f(pc ) d=002232! s=00000000| OK
-- wreg (232,00007) a=0004(al ) d=002260 s=00000000| OK
-- rblk (021,00027) a=0007(memi ) n= 4= 4! s=00000000| OK
0: 000010! 000100! 001000! 001121!
# C ----------------------------------------------------------------------------
# C finally stop and init CPU (clears cpuhalt flag)
543.3 ns 40: START
8705.8 ns 1020: OOB-MSG 00000000 00001111 00000000 : 000 007400
9072.4 ns 1064: OOB-MSG 00000000 00001101 00000000 : 000 006400
rlink_cext-I: seen EOF, schedule clock stop and exit
150810.0 ns 18072: DONE
../../../../vlib/rlink/tbcore/tbcore_rlink.vhd:294:5:@150910ns:(report failure): Simulation Finished
tb_w11a_b3:error: report failed
from: process work.tbcore_rlink(sim).proc_stim at tbcore_rlink.vhd:294
tb_w11a_b3:error: simulation failed
++ wreg (242,00017) a=0001(cntl ) d=000002 s=00000000| OK
-- wreg (252,00027) a=0001(cntl ) d=000004 s=00000000| OK
real 0m2.129s user 0m2.096s sys 0m0.048s