tbw-I: create FIFO rlink_cext_fifo_tx tbw-I: define rlink_cext_conf -> /dev/null ../../src/ieee/numeric_std-body.v93:1558:7:@0ms:(assertion warning): NUMERIC_STD.">=": metavalue detected, returning FALSE ../../src/ieee/numeric_std-body.v93:1406:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE ../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE ../../src/ieee/numeric_std-body.v93:1558:7:@0ms:(assertion warning): NUMERIC_STD.">=": metavalue detected, returning FALSE ../../src/ieee/numeric_std-body.v93:1406:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE ../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 rlink_cext-I: connected to rlink_cext_fifo_rx rlink_cext-I: connected to rlink_cext_fifo_tx ++ rreg (000,00017) a=fffe() d=ff02 s=00! OK -- rreg (010,00007) a=fffd() d=0104 s=00! OK -- rreg (020,00007) a=fffc() d=0300 s=00! OK -- rreg (030,00007) a=fffb() d=0000 s=02 OK -- rreg (040,00007) a=fffa() d=0000 s=02 OK -- rreg (050,00027) a=ffe8() d=0000 s=02 OK ++ wreg (002,00017) a=000f(sr.sstop ) d=0001 s=00! OK -- wreg (012,00027) a=000d(sr.sstat ) d=0000 s=00! OK # tst_sram::test_regs --------------------------------------------- # init: reset SEQ via init, clear sfail ect ++ init (006,00037) a=0000(sr.mdih ) d=0001 s=00! OK # test 1a: test mdi* ,maddr* ++ wreg (022,00017) a=0000(sr.mdih ) d=5555 s=00! OK -- wreg (032,00007) a=0001(sr.mdil ) d=aaaa s=00! OK -- wreg (042,00007) a=0004(sr.maddrh) d=0001 s=00! OK -- wreg (052,00007) a=0005(sr.maddrl) d=cccc s=00! OK -- rreg (060,00007) a=0000(sr.mdih ) d=5555! s=00! OK -- rreg (070,00007) a=0001(sr.mdil ) d=aaaa! s=00! OK -- rreg (100,00007) a=0004(sr.maddrh) d=0001! s=00! OK -- rreg (110,00027) a=0005(sr.maddrl) d=cccc! s=00! OK # test 1b: test maddrh range ++ rreg (120,00037) a=000d(sr.sstat ) d=c000 s=00! OK ++ wreg (062,00017) a=0004(sr.maddrh) d=ffff s=00! OK -- rreg (130,00027) a=0004(sr.maddrh) d=003f! s=00! OK # test 2: test direct memory write/read via mcmd ++ wreg (072,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (102,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (112,00007) a=0000(sr.mdih ) d=dead s=00! OK -- wreg (122,00007) a=0001(sr.mdil ) d=beaf s=00! OK -- wreg (132,00007) a=0006(sr.mcmd ) d=1f00 s=00! OK -- wreg (142,00007) a=0005(sr.maddrl) d=0001 s=00! OK -- wreg (152,00007) a=0000(sr.mdih ) d=a5a5 s=00! OK -- wreg (162,00007) a=0001(sr.mdil ) d=5a5a s=00! OK -- wreg (172,00027) a=0006(sr.mcmd ) d=1f00 s=00! OK ++ wreg (202,00017) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (212,00007) a=0006(sr.mcmd ) d=0f00 s=00! OK -- rreg (140,00007) a=0002(sr.mdoh ) d=dead! s=00! OK -- rreg (150,00007) a=0003(sr.mdol ) d=beaf! s=00! OK -- wreg (222,00007) a=0005(sr.maddrl) d=0001 s=00! OK -- wreg (232,00007) a=0006(sr.mcmd ) d=0f00 s=00! OK -- rreg (160,00007) a=0002(sr.mdoh ) d=a5a5! s=00! OK -- rreg (170,00027) a=0003(sr.mdol ) d=5a5a! s=00! OK ++ rreg (200,00017) a=0000(sr.mdih ) d=a5a5! s=00! OK -- rreg (210,00027) a=0001(sr.mdil ) d=5a5a! s=00! OK ++ rreg (220,00037) a=0006(sr.mcmd ) d=5a5a s=01| OK # test 3: test block write/read via mblk ++ wreg (242,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (252,00007) a=0005(sr.maddrl) d=0010 s=00! OK -- wblk (003,00007) a=0007(sr.mblk ) n= 16= 16 s=00! OK 0: 3020 1000 3121 1101 3222 1202 3323 1303 3424 1404 3525 11: 1505 3626 1606 3727 1707 -- rreg (230,00007) a=0004(sr.maddrh) d=0000! s=00! OK -- rreg (240,00027) a=0005(sr.maddrl) d=0018! s=00! OK ++ wreg (262,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (272,00007) a=0005(sr.maddrl) d=0010 s=00! OK -- rblk (001,00007) a=0007(sr.mblk ) n= 16= 16 s=00! OK 0: 3020! 1000! 3121! 1101! 3222! 1202! 3323! 1303! 3424! 1404! 3525! 11: 1505! 3626! 1606! 3727! 1707! -- rreg (250,00007) a=0004(sr.maddrh) d=0000! s=00! OK -- rreg (260,00027) a=0005(sr.maddrl) d=0018! s=00! OK # test 4: mcmd: ld,inc and be functionality ++ wreg (302,00017) a=0004(sr.maddrh) d=0003 s=00! OK -- wreg (312,00007) a=0005(sr.maddrl) d=0012 s=00! OK -- wreg (322,00007) a=0000(sr.mdih ) d=ffff s=00! OK -- wreg (332,00007) a=0001(sr.mdil ) d=ff42 s=00! OK -- wreg (342,00007) a=0006(sr.mcmd ) d=7100 s=00! OK -- wreg (352,00007) a=0001(sr.mdil ) d=53ff s=00! OK -- wreg (362,00007) a=0006(sr.mcmd ) d=3200 s=00! OK -- wreg (372,00007) a=0000(sr.mdih ) d=ff64 s=00! OK -- wreg (002,00007) a=0001(sr.mdil ) d=ffff s=00! OK -- wreg (012,00007) a=0006(sr.mcmd ) d=3400 s=00! OK -- wreg (022,00007) a=0000(sr.mdih ) d=75ff s=00! OK -- wreg (032,00027) a=0006(sr.mcmd ) d=3800 s=00! OK ++ rreg (270,00017) a=0004(sr.maddrh) d=0000! s=00! OK -- rreg (300,00007) a=0005(sr.maddrl) d=0016! s=00! OK -- wreg (042,00007) a=0005(sr.maddrl) d=0010 s=00! OK -- rblk (011,00027) a=0007(sr.mblk ) n= 16= 16 s=00! OK 0: 3020! 1000! 3121! 1101! 3222! 1242! 3323! 5303! 3464! 1404! 7525! 11: 1505! 3626! 1606! 3727! 1707! # test 5: test saddr,slim,sblk,sblkc,sblkd ++ wreg (052,00017) a=0008(sr.slim ) d=0123 s=00! OK -- wreg (062,00007) a=0009(sr.saddr ) d=0345 s=00! OK -- rreg (310,00007) a=0008(sr.slim ) d=0123! s=00! OK -- rreg (320,00027) a=0009(sr.saddr ) d=0345! s=00! OK ++ wreg (072,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- wblk (013,00007) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 0300 0200 0100 0000 0301 0201 0101 0001 0302 0202 0102 11: 0002 0303 0203 0103 0003 0304 0204 0104 0004 0305 0205 22: 0105 0005 0306 0206 0106 0006 0307 0207 0107 0007 -- rreg (330,00027) a=0009(sr.saddr ) d=0008! s=00! OK ++ wreg (102,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (021,00007) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 0300! 0200! 0100! 0000! 0301! 0201! 0101! 0001! 0302! 0202! 0102! 11: 0002! 0303! 0203! 0103! 0003! 0304! 0204! 0104! 0004! 0305! 0205! 22: 0105! 0005! 0306! 0206! 0106! 0006! 0307! 0207! 0107! 0007! -- rreg (340,00027) a=0009(sr.saddr ) d=0008! s=00! OK ++ wreg (112,00017) a=0009(sr.saddr ) d=0001 s=00! OK -- wblk (023,00007) a=000b(sr.sblkc ) n= 8= 8 s=00! OK 0: 1301 1201 1302 1202 1303 1203 1304 1204 -- rreg (350,00027) a=0009(sr.saddr ) d=0005! s=00! OK ++ wreg (122,00017) a=0009(sr.saddr ) d=0003 s=00! OK -- wblk (033,00007) a=000c(sr.sblkd ) n= 8= 8 s=00! OK 0: 2103 2003 2104 2004 2105 2005 2106 2006 -- rreg (360,00027) a=0009(sr.saddr ) d=0007! s=00! OK ++ wreg (132,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (031,00007) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 0300! 0200! 0100! 0000! 1301! 1201! 0101! 0001! 1302! 1202! 0102! 11: 0002! 1303! 1203! 2103! 2003! 1304! 1204! 2104! 2004! 0305! 0205! 22: 2105! 2005! 0306! 0206! 2106! 2006! 0307! 0207! 0107! 0007! -- rreg (370,00027) a=0009(sr.saddr ) d=0008! s=00! OK ++ wreg (142,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (041,00007) a=000b(sr.sblkc ) n= 16= 16 s=00! OK 0: 0300! 0200! 1301! 1201! 1302! 1202! 1303! 1203! 1304! 1204! 0305! 11: 0205! 0306! 0206! 0307! 0207! -- rreg (000,00027) a=0009(sr.saddr ) d=0008! s=00! OK ++ wreg (152,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (051,00007) a=000c(sr.sblkd ) n= 16= 16 s=00! OK 0: 0100! 0000! 0101! 0001! 0102! 0002! 2103! 2003! 2104! 2004! 2105! 11: 2005! 2106! 2006! 0107! 0007! -- rreg (010,00027) a=0009(sr.saddr ) d=0008! s=00! OK # test 5: test sstat bits ++ wreg (162,00017) a=000d(sr.sstat ) d=0000 s=00! OK -- rreg (020,00007) a=000d(sr.sstat ) d=c000! s=00! OK -- wreg (172,00007) a=000d(sr.sstat ) d=0010 s=00! OK -- rreg (030,00007) a=000d(sr.sstat ) d=c010! s=00! OK -- wreg (202,00007) a=000d(sr.sstat ) d=0020 s=00! OK -- rreg (040,00007) a=000d(sr.sstat ) d=c020! s=00! OK -- wreg (212,00007) a=000d(sr.sstat ) d=0040 s=00! OK -- rreg (050,00007) a=000d(sr.sstat ) d=c040! s=00! OK -- wreg (222,00007) a=000d(sr.sstat ) d=0080 s=00! OK -- rreg (060,00007) a=000d(sr.sstat ) d=c080! s=00! OK -- wreg (232,00007) a=000d(sr.sstat ) d=0100 s=00! OK -- rreg (070,00007) a=000d(sr.sstat ) d=c100! s=00! OK -- wreg (242,00007) a=000d(sr.sstat ) d=0200 s=00! OK -- rreg (100,00027) a=000d(sr.sstat ) d=c200! s=00! OK # test 6: test memory (touch 5(+5) evenly spaced addresses) ++ wreg (252,00017) a=0000(sr.mdih ) d=5500 s=00! OK -- wreg (262,00007) a=0001(sr.mdil ) d=aa00 s=00! OK -- wreg (272,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (302,00007) a=0006(sr.mcmd ) d=7f00 s=00! OK -- wreg (312,00007) a=0000(sr.mdih ) d=5501 s=00! OK -- wreg (322,00007) a=0001(sr.mdil ) d=aa01 s=00! OK -- wreg (332,00007) a=0006(sr.mcmd ) d=7f01 s=00! OK -- wreg (342,00007) a=0000(sr.mdih ) d=5502 s=00! OK -- wreg (352,00007) a=0001(sr.mdil ) d=aa02 s=00! OK -- wreg (362,00007) a=0006(sr.mcmd ) d=7f02 s=00! OK -- wreg (372,00007) a=0000(sr.mdih ) d=5503 s=00! OK -- wreg (002,00007) a=0001(sr.mdil ) d=aa03 s=00! OK -- wreg (012,00007) a=0006(sr.mcmd ) d=7f03 s=00! OK -- rreg (110,00007) a=0005(sr.maddrl) d=0004! s=00! OK -- wreg (022,00007) a=0000(sr.mdih ) d=5504 s=00! OK -- wreg (032,00007) a=0001(sr.mdil ) d=aa04 s=00! OK -- wreg (042,00007) a=0005(sr.maddrl) d=ffff s=00! OK -- wreg (052,00027) a=0006(sr.mcmd ) d=5f03 s=00! OK ++ wreg (062,00017) a=0000(sr.mdih ) d=a500 s=00! OK -- wreg (072,00007) a=0001(sr.mdil ) d=5a00 s=00! OK -- wreg (102,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (112,00007) a=0006(sr.mcmd ) d=7f04 s=00! OK -- wreg (122,00007) a=0000(sr.mdih ) d=5a01 s=00! OK -- wreg (132,00007) a=0001(sr.mdil ) d=5a01 s=00! OK -- wreg (142,00007) a=0006(sr.mcmd ) d=7f10 s=00! OK -- wreg (152,00007) a=0000(sr.mdih ) d=5a02 s=00! OK -- wreg (162,00007) a=0001(sr.mdil ) d=5a02 s=00! OK -- wreg (172,00007) a=0006(sr.mcmd ) d=7f20 s=00! OK -- wreg (202,00007) a=0000(sr.mdih ) d=5a03 s=00! OK -- wreg (212,00007) a=0001(sr.mdil ) d=5a03 s=00! OK -- wreg (222,00007) a=0006(sr.mcmd ) d=7f30 s=00! OK -- rreg (120,00007) a=0005(sr.maddrl) d=0004! s=00! OK -- wreg (232,00007) a=0000(sr.mdih ) d=5a04 s=00! OK -- wreg (242,00007) a=0001(sr.mdil ) d=5a04 s=00! OK -- wreg (252,00007) a=0005(sr.maddrl) d=ffff s=00! OK -- wreg (262,00027) a=0006(sr.mcmd ) d=5f3f s=00! OK ++ wreg (272,00017) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (302,00007) a=0006(sr.mcmd ) d=6f00 s=00! OK -- rreg (130,00007) a=0002(sr.mdoh ) d=5500! s=00! OK -- rreg (140,00007) a=0003(sr.mdol ) d=aa00! s=00! OK -- wreg (312,00007) a=0006(sr.mcmd ) d=6f01 s=00! OK -- rreg (150,00007) a=0002(sr.mdoh ) d=5501! s=00! OK -- rreg (160,00007) a=0003(sr.mdol ) d=aa01! s=00! OK -- wreg (322,00007) a=0006(sr.mcmd ) d=6f02 s=00! OK -- rreg (170,00007) a=0002(sr.mdoh ) d=5502! s=00! OK -- rreg (200,00007) a=0003(sr.mdol ) d=aa02! s=00! OK -- wreg (332,00007) a=0006(sr.mcmd ) d=6f03 s=00! OK -- rreg (210,00007) a=0002(sr.mdoh ) d=5503! s=00! OK -- rreg (220,00007) a=0003(sr.mdol ) d=aa03! s=00! OK -- rreg (230,00007) a=0005(sr.maddrl) d=0004! s=00! OK -- wreg (342,00007) a=0005(sr.maddrl) d=ffff s=00! OK -- wreg (352,00007) a=0006(sr.mcmd ) d=4f03 s=00! OK -- rreg (240,00007) a=0002(sr.mdoh ) d=5504! s=00! OK -- rreg (250,00027) a=0003(sr.mdol ) d=aa04! s=00! OK ++ wreg (362,00017) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (372,00007) a=0006(sr.mcmd ) d=6f04 s=00! OK -- rreg (260,00007) a=0002(sr.mdoh ) d=a500! s=00! OK -- rreg (270,00007) a=0003(sr.mdol ) d=5a00! s=00! OK -- wreg (002,00007) a=0006(sr.mcmd ) d=6f10 s=00! OK -- rreg (300,00007) a=0002(sr.mdoh ) d=5a01! s=00! OK -- rreg (310,00007) a=0003(sr.mdol ) d=5a01! s=00! OK -- wreg (012,00007) a=0006(sr.mcmd ) d=6f20 s=00! OK -- rreg (320,00007) a=0002(sr.mdoh ) d=5a02! s=00! OK -- rreg (330,00007) a=0003(sr.mdol ) d=5a02! s=00! OK -- wreg (022,00007) a=0006(sr.mcmd ) d=6f30 s=00! OK -- rreg (340,00007) a=0002(sr.mdoh ) d=5a03! s=00! OK -- rreg (350,00007) a=0003(sr.mdol ) d=5a03! s=00! OK -- rreg (360,00007) a=0005(sr.maddrl) d=0004! s=00! OK -- wreg (032,00007) a=0005(sr.maddrl) d=ffff s=00! OK -- wreg (042,00007) a=0006(sr.mcmd ) d=4f3f s=00! OK -- rreg (370,00007) a=0002(sr.mdoh ) d=5a04! s=00! OK -- rreg (000,00027) a=0003(sr.mdol ) d=5a04! s=00! OK ++ wreg (052,00037) a=ffff(rl.cntl ) d=8000 s=00! OK # tst_sram::test_seq ---------------------------------------------- # test 1: list of write commands ++ wreg (062,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (043,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0110 7060 5040 01f0 0111 7161 5141 01f0 0112 7262 11: 5242 01f0 0113 7363 5343 01f0 0114 7464 5444 01f0 0115 22: 7565 5545 01f0 0116 7666 5646 01f0 0117 7767 5747 ++ wreg (072,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (102,00007) a=000d(sr.sstat ) d=0000 s=00! OK -- wreg (112,00027) a=000e(sr.sstart) d=0000 s=00! OK -+- 2018-12-23 -+- -I- 08:16:05.398233 : ATTN notify apat = 0001 lams = 0 -- wtlam apat=0001 to=10.000 T=0.009 OK ++ attn (005,00017) d=0001! s=00! OK -- rreg (010,00007) a=000d(sr.sstat ) d=c000! s=00| OK -- rreg (020,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (122,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (132,00007) a=0005(sr.maddrl) d=0110 s=00! OK -- wblk (053,00027) a=0007(sr.mblk ) n= 16= 16 s=00! OK 0: 7060 5040 7161 5141 7262 5242 7363 5343 7464 5444 7565 11: 5545 7666 5646 7767 5747 # test 2: list of read commands ++ wreg (142,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (063,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 00f0 0110 dead 0000 00f0 0111 beaf 1111 00f0 0112 dead 11: 2222 00f0 0113 beaf 3333 00f0 0114 dead 4444 00f0 0115 22: beaf 5555 00f0 0116 dead 6666 00f0 0117 beaf 7777 ++ wreg (152,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (162,00007) a=000d(sr.sstat ) d=0000 s=00! OK -- wreg (172,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:05.574782 : ATTN notify apat = 0001 lams = 0 dt=0.176540 -- wtlam apat=0001 to=10.000 T=0.007 OK ++ attn (015,00017) d=0001! s=00! OK -- rreg (030,00007) a=000d(sr.sstat ) d=c000! s=00| OK -- rreg (040,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (202,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (061,00027) a=000c(sr.sblkd ) n= 16= 16 s=00! OK 0: 7060! 5040! 7161! 5141! 7262! 5242! 7363! 5343! 7464! 5444! 7565! 11: 5545! 7666! 5646! 7767! 5747! # test 3: mixed list of writes (some byte wise) and reads ++ wreg (212,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (073,00037) a=000a(sr.sblk ) n= 112= 112 s=00! OK 0: 0110 0112 0000 0082 0120 0113 0000 9300 00f0 0110 0000 11: 0000 0140 0114 00a4 0000 00f0 0111 0000 0000 0180 0115 22: b500 0000 00f0 0112 0000 0000 00f0 0113 0000 0000 01f0 33: 0118 7868 5848 00f0 0114 0000 0000 01f0 0119 7969 5949 44: 01f0 011a 7a6a 5a4a 00f0 0115 0000 0000 01f0 011b 7b6b 55: 5b4b 00f0 0116 0000 0000 01f0 011c 7c6c 5c4c 01f0 011d 66: 7d6d 5d4d 00f0 0117 0000 0000 00f0 0118 0000 0000 01f0 77: 011e 7e6e 5e4e 01f0 011f 7f6f 5f4f 00f0 0119 0000 0000 88: 00f0 011a 0000 0000 00f0 011b 0000 0000 00f0 011c 0000 99: 0000 00f0 011d 0000 0000 00f0 011e 0000 0000 00f0 011f 110: 0000 0000 ++ wreg (222,00017) a=0008(sr.slim ) d=001b s=00! OK -- wreg (232,00007) a=000d(sr.sstat ) d=0000 s=00! OK -- wreg (242,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:05.863051 : ATTN notify apat = 0001 lams = 0 dt=0.288269 -- wtlam apat=0001 to=10.000 T=0.023 OK ++ attn (025,00017) d=0001! s=00! OK -- rreg (050,00007) a=000d(sr.sstat ) d=c000! s=00| OK -- rreg (060,00027) a=0009(sr.saddr ) d=001c! s=00| OK ++ wreg (252,00017) a=0009(sr.saddr ) d=0000 s=00! OK -- rblk (071,00027) a=000c(sr.sblkd ) n= 56= 56 s=00! OK 0: 0000! 0082! 0000! 9300! 7060! 5040! 00a4! 0000! 7161! 5141! b500! 11: 0000! 7262! 5282! 7363! 9343! 7868! 5848! 74a4! 5444! 7969! 5949! 22: 7a6a! 5a4a! b565! 5545! 7b6b! 5b4b! 7666! 5646! 7c6c! 5c4c! 7d6d! 33: 5d4d! 7767! 5747! 7868! 5848! 7e6e! 5e4e! 7f6f! 5f4f! 7969! 5949! 44: 7a6a! 5a4a! 7b6b! 5b4b! 7c6c! 5c4c! 7d6d! 5d4d! 7e6e! 5e4e! 7f6f! 55: 5f4f! # test 4: sequencer verify mode ++ wreg (262,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (103,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0220 b0a0 9080 01f0 0221 b1a1 9181 00f0 0220 b0a0 11: 9080 01f0 0222 b2a2 9282 00f0 0221 b1a1 9181 01f0 0223 22: b3a3 9383 00f0 0222 b2a2 9282 00f0 0223 b3a3 9383 ++ wreg (272,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (302,00007) a=000d(sr.sstat ) d=0010 s=00! OK -- wreg (312,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.091388 : ATTN notify apat = 0001 lams = 0 dt=0.228337 -- wtlam apat=0001 to=10.000 T=0.008 OK ++ attn (035,00017) d=0001! s=00! OK -- rreg (070,00007) a=000d(sr.sstat ) d=c010! s=00| OK -- rreg (100,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (322,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (113,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0230 b0a0 9080 01f0 0231 b1a1 9181 00f0 0230 b0a0 11: 9080 01f0 0232 b2a2 9282 00f0 0231 0000 0000 01f0 0233 22: b3a3 9383 00f0 0232 b2a2 9282 00f0 0233 b3a3 9383 ++ wreg (332,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (342,00007) a=000d(sr.sstat ) d=0010 s=00! OK -- wreg (352,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.211518 : ATTN notify apat = 0001 lams = 0 dt=0.120131 -- wtlam apat=0001 to=10.000 T=0.007 OK ++ attn (045,00017) d=0001! s=20! OK -- rreg (110,00007) a=000d(sr.sstat ) d=c012! s=20| OK -- rreg (120,00007) a=0010(sr.seaddr) d=0004! s=20| OK -- rreg (130,00007) a=0011(sr.sedath) d=b1a1! s=20| OK -- rreg (140,00027) a=0012(sr.sedatl) d=9181! s=20| OK ++ wreg (362,00017) a=0009(sr.saddr ) d=0000 s=20! OK -- rblk (101,00027) a=000c(sr.sblkd ) n= 16= 16 s=20! OK 0: b0a0! 9080! b1a1! 9181! b0a0! 9080! b2a2! 9282! 0000! 0000! b3a3! 11: 9383! b2a2! 9282! b3a3! 9383! # test 5: test reset via init ++ rreg (150,00017) a=000d(sr.sstat ) d=c012! s=20! OK -- rreg (160,00007) a=0010(sr.seaddr) d=0004! s=20! OK -- rreg (170,00007) a=0011(sr.sedath) d=b1a1! s=20! OK -- rreg (200,00027) a=0012(sr.sedatl) d=9181! s=20! OK ++ init (016,00017) a=0000(sr.mdih ) d=0000 s=20! OK -- rreg (210,00007) a=000d(sr.sstat ) d=c012! s=20! OK -- rreg (220,00007) a=0010(sr.seaddr) d=0004! s=20! OK -- rreg (230,00007) a=0011(sr.sedath) d=b1a1! s=20! OK -- rreg (240,00027) a=0012(sr.sedatl) d=9181! s=20! OK ++ init (026,00017) a=0000(sr.mdih ) d=0001 s=20! OK -- rreg (250,00007) a=000d(sr.sstat ) d=c000! s=00! OK -- rreg (260,00007) a=0010(sr.seaddr) d=0000! s=00! OK -- rreg (270,00007) a=0011(sr.sedath) d=0000! s=00! OK -- rreg (300,00027) a=0012(sr.sedatl) d=0000! s=00! OK # test 6: xord and xora options ++ wreg (372,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (123,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0440 c0b0 a090 01f0 0441 c1b1 a191 00f0 0440 c0b0 11: a090 01f0 0442 c2b2 a292 00f0 0441 c1b1 a191 01f0 0443 22: c3b3 a393 00f0 0442 c2b2 a292 00f0 0443 c3b3 a393 ++ wreg (002,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (012,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (022,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (032,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (042,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (052,00007) a=000d(sr.sstat ) d=0070 s=00! OK -- wreg (062,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.505279 : ATTN notify apat = 0001 lams = 0 dt=0.293760 -- wtlam apat=0001 to=10.000 T=0.008 OK ++ attn (055,00017) d=0001! s=00! OK -- rreg (310,00007) a=000d(sr.sstat ) d=c070! s=00| OK -- rreg (320,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (072,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (102,00007) a=0005(sr.maddrl) d=0440 s=00! OK -- rblk (111,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: c0b0! a090! c1b1! a191! c2b2! a292! c3b3! a393! ++ wreg (112,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (122,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (132,00007) a=0000(sr.mdih ) d=f0f0 s=00! OK -- wreg (142,00027) a=0001(sr.mdil ) d=f0f0 s=00! OK ++ wreg (152,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (162,00007) a=000d(sr.sstat ) d=0050 s=00! OK -- wreg (172,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.622272 : ATTN notify apat = 0001 lams = 0 dt=0.116994 -- wtlam apat=0001 to=10.000 T=0.009 OK ++ attn (065,00017) d=0001! s=00! OK -- rreg (330,00007) a=000d(sr.sstat ) d=c050! s=00| OK -- rreg (340,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (202,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (212,00007) a=0005(sr.maddrl) d=0440 s=00! OK -- rblk (121,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: 3040! 5060! 3141! 5161! 3242! 5262! 3343! 5363! ++ wreg (222,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (232,00007) a=0005(sr.maddrl) d=0000 s=00! OK -- wreg (242,00007) a=0000(sr.mdih ) d=0f0f s=00! OK -- wreg (252,00027) a=0001(sr.mdil ) d=0f0f s=00! OK ++ wreg (262,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (272,00007) a=000d(sr.sstat ) d=0050 s=00! OK -- wreg (302,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.739385 : ATTN notify apat = 0001 lams = 0 dt=0.117111 -- wtlam apat=0001 to=10.000 T=0.008 OK ++ attn (075,00017) d=0001! s=00! OK -- rreg (350,00007) a=000d(sr.sstat ) d=c050! s=00| OK -- rreg (360,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (312,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (322,00007) a=0005(sr.maddrl) d=0440 s=00! OK -- rblk (131,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: cfbf! af9f! cebe! ae9e! cdbd! ad9d! ccbc! ac9c! ++ wreg (332,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (342,00007) a=0005(sr.maddrl) d=1000 s=00! OK -- wreg (352,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (362,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (372,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (002,00007) a=000d(sr.sstat ) d=0030 s=00! OK -- wreg (012,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.857673 : ATTN notify apat = 0001 lams = 0 dt=0.118289 -- wtlam apat=0001 to=10.000 T=0.008 OK ++ attn (105,00017) d=0001! s=00! OK -- rreg (370,00007) a=000d(sr.sstat ) d=c030! s=00| OK -- rreg (000,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (022,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (032,00007) a=0005(sr.maddrl) d=1440 s=00! OK -- rblk (141,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: c0b0! a090! c1b1! a191! c2b2! a292! c3b3! a393! ++ wreg (042,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (052,00007) a=0005(sr.maddrl) d=2000 s=00! OK -- wreg (062,00007) a=0000(sr.mdih ) d=f0f0 s=00! OK -- wreg (072,00027) a=0001(sr.mdil ) d=f0f0 s=00! OK ++ wreg (102,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (112,00007) a=000d(sr.sstat ) d=0070 s=00! OK -- wreg (122,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:06.976162 : ATTN notify apat = 0001 lams = 0 dt=0.118481 -- wtlam apat=0001 to=10.000 T=0.009 OK ++ attn (115,00017) d=0001! s=00! OK -- rreg (010,00007) a=000d(sr.sstat ) d=c070! s=00| OK -- rreg (020,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (132,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (142,00007) a=0005(sr.maddrl) d=2440 s=00! OK -- rblk (151,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: 3040! 5060! 3141! 5161! 3242! 5262! 3343! 5363! ++ wreg (152,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (133,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0550 c0b0 a090 01f0 0551 c1b1 a191 01f0 0552 c2b2 11: a292 01f0 0553 c3b3 a393 00f0 0550 0000 0000 00f0 0551 22: 0000 0000 00f0 0552 0000 0000 00f0 0553 0000 0000 ++ wreg (162,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (172,00007) a=0005(sr.maddrl) d=4000 s=00! OK -- wreg (202,00007) a=0000(sr.mdih ) d=f0f0 s=00! OK -- wreg (212,00027) a=0001(sr.mdil ) d=f0f0 s=00! OK ++ wreg (222,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (232,00007) a=000d(sr.sstat ) d=0070 s=00! OK -- wreg (242,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:07.160320 : ATTN notify apat = 0001 lams = 0 dt=0.184166 -- wtlam apat=0001 to=10.000 T=0.007 OK ++ attn (125,00017) d=0001! s=20! OK -- rreg (030,00007) a=000d(sr.sstat ) d=c072! s=20| OK -- rreg (040,00007) a=0010(sr.seaddr) d=0004! s=20| OK -- rreg (050,00007) a=0011(sr.sedath) d=3040! s=20| OK -- rreg (060,00027) a=0012(sr.sedatl) d=5060! s=20| OK ++ wreg (252,00017) a=0004(sr.maddrh) d=0000 s=20! OK -- wreg (262,00007) a=0005(sr.maddrl) d=4550 s=20! OK -- rblk (161,00027) a=0007(sr.mblk ) n= 8= 8 s=20! OK 0: 3040! 5060! 3141! 5161! 3242! 5262! 3343! 5363! ++ init (036,00037) a=0000(sr.mdih ) d=0001 s=20! OK # test 7: loop option (with xora) ++ wreg (272,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (143,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0000 0010 2030 01f0 0001 0111 2131 00f0 0000 0010 11: 2030 01f0 0002 0212 2232 00f0 0001 0111 2131 01f0 0003 22: 0313 2333 00f0 0002 0212 2232 00f0 0003 0313 2333 ++ wreg (302,00017) a=0004(sr.maddrh) d=0003 s=00! OK -- wreg (312,00007) a=0005(sr.maddrl) d=fff0 s=00! OK -- wreg (322,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (332,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (342,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (352,00007) a=000d(sr.sstat ) d=00b0 s=00! OK -- wreg (362,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:07.474529 : ATTN notify apat = 0001 lams = 0 dt=0.314209 -- wtlam apat=0001 to=10.000 T=0.113 OK ++ attn (135,00017) d=0001! s=00! OK -- rreg (070,00007) a=000d(sr.sstat ) d=c0b0! s=00| OK -- rreg (100,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ rreg (110,00017) a=0004(sr.maddrh) d=0003! s=00! OK -- rreg (120,00027) a=0005(sr.maddrl) d=ffff! s=00! OK ++ wreg (372,00017) a=0004(sr.maddrh) d=0003 s=00! OK -- wreg (002,00007) a=0005(sr.maddrl) d=fffc s=00! OK -- rblk (171,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: 0313! 2333! 0212! 2232! 0111! 2131! 0010! 2030! # test 8: loop option (with xora), verify fail case ++ wreg (012,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (153,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0100 0010 2030 01f0 0101 0111 2131 01f0 0102 0212 11: 2232 01f0 0103 0313 2333 00f0 0100 0010 2030 00f0 0101 22: 0000 0000 00f0 0102 0000 0000 00f0 0103 0000 0000 ++ wreg (022,00017) a=0004(sr.maddrh) d=0003 s=00! OK -- wreg (032,00007) a=0005(sr.maddrl) d=fff0 s=00! OK -- wreg (042,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (052,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (062,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (072,00007) a=000d(sr.sstat ) d=00b0 s=00! OK -- wreg (102,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:07.676451 : ATTN notify apat = 0001 lams = 0 dt=0.201923 -- wtlam apat=0001 to=10.000 T=0.008 OK ++ attn (145,00017) d=0001! s=20! OK -- rreg (130,00007) a=000d(sr.sstat ) d=c0b2! s=20| OK -- rreg (140,00007) a=0010(sr.seaddr) d=0005! s=20| OK -- rreg (150,00007) a=0011(sr.sedath) d=0111! s=20| OK -- rreg (160,00027) a=0012(sr.sedatl) d=2131! s=20| OK ++ rreg (170,00017) a=0004(sr.maddrh) d=0003! s=20! OK -- rreg (200,00027) a=0005(sr.maddrl) d=fff0! s=20! OK ++ init (046,00037) a=0000(sr.mdih ) d=0001 s=20! OK # test 9: wait field in sequencer ++ wreg (112,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (163,00037) a=000a(sr.sblk ) n= 128= 128 s=00! OK 0: 01f0 0110 2000 1000 11f0 0111 2001 1001 21f0 0112 2002 11: 1002 31f0 0113 2003 1003 41f0 0114 2004 1004 51f0 0115 22: 2005 1005 61f0 0116 2006 1006 71f0 0117 2007 1007 81f0 33: 0118 2008 1008 91f0 0119 2009 1009 a1f0 011a 200a 100a 44: b1f0 011b 200b 100b c1f0 011c 200c 100c d1f0 011d 200d 55: 100d e1f0 011e 200e 100e f1f0 011f 200f 100f 00f0 0110 66: 2000 1000 10f0 0111 2001 1001 20f0 0112 2002 1002 30f0 77: 0113 2003 1003 40f0 0114 2004 1004 50f0 0115 2005 1005 88: 60f0 0116 2006 1006 70f0 0117 2007 1007 80f0 0118 2008 99: 1008 90f0 0119 2009 1009 a0f0 011a 200a 100a b0f0 011b 110: 200b 100b c0f0 011c 200c 100c d0f0 011d 200d 100d e0f0 121: 011e 200e 100e f0f0 011f 200f 100f ++ wreg (122,00017) a=0004(sr.maddrh) d=0001 s=00! OK -- wreg (132,00007) a=0005(sr.maddrl) d=1000 s=00! OK -- wreg (142,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (152,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (162,00017) a=0008(sr.slim ) d=001f s=00! OK -- wreg (172,00007) a=000d(sr.sstat ) d=0030 s=00! OK -- wreg (202,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:08.024079 : ATTN notify apat = 0001 lams = 0 dt=0.347619 -- wtlam apat=0001 to=10.000 T=0.036 OK ++ attn (155,00017) d=0001! s=00! OK -- rreg (210,00007) a=000d(sr.sstat ) d=c030! s=00| OK -- rreg (220,00027) a=0009(sr.saddr ) d=0020! s=00| OK ++ wreg (212,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (173,00037) a=000a(sr.sblk ) n= 128= 128 s=00! OK 0: 01f0 0120 3000 2000 01f0 0121 3001 2001 00f0 0120 3000 11: 2000 00f0 0121 3001 2001 11f0 0122 3002 2002 11f0 0123 22: 3003 2003 10f0 0122 3002 2002 10f0 0123 3003 2003 21f0 33: 0124 3004 2004 21f0 0125 3005 2005 20f0 0124 3004 2004 44: 20f0 0125 3005 2005 31f0 0126 3006 2006 31f0 0127 3007 55: 2007 30f0 0126 3006 2006 30f0 0127 3007 2007 41f0 0128 66: 3008 2008 41f0 0129 3009 2009 40f0 0128 3008 2008 40f0 77: 0129 3009 2009 51f0 012a 300a 200a 51f0 012b 300b 200b 88: 50f0 012a 300a 200a 50f0 012b 300b 200b 61f0 012c 300c 99: 200c 61f0 012d 300d 200d 60f0 012c 300c 200c 60f0 012d 110: 300d 200d 71f0 012e 300e 200e 71f0 012f 300f 200f 70f0 121: 012e 300e 200e 70f0 012f 300f 200f ++ wreg (222,00017) a=0004(sr.maddrh) d=0002 s=00! OK -- wreg (232,00007) a=0005(sr.maddrl) d=2000 s=00! OK -- wreg (242,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (252,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (262,00017) a=0008(sr.slim ) d=001f s=00! OK -- wreg (272,00007) a=000d(sr.sstat ) d=0030 s=00! OK -- wreg (302,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:08.337213 : ATTN notify apat = 0001 lams = 0 dt=0.313142 -- wtlam apat=0001 to=10.000 T=0.034 OK ++ attn (165,00017) d=0001! s=00! OK -- rreg (230,00007) a=000d(sr.sstat ) d=c030! s=00| OK -- rreg (240,00027) a=0009(sr.saddr ) d=0020! s=00| OK # test 10: wswap option ++ wreg (312,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (203,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0000 1234 0000 01f1 0011 1234 0011 01f2 0022 1234 11: 0022 01f3 0033 1234 0033 00f0 0000 1234 0000 00f1 0011 22: 1234 0011 00f2 0022 1234 0022 00f3 0033 1234 0033 ++ wreg (322,00017) a=0004(sr.maddrh) d=0000 s=00! OK -- wreg (332,00007) a=0005(sr.maddrl) d=1000 s=00! OK -- wreg (342,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (352,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (362,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (372,00007) a=000d(sr.sstat ) d=0230 s=00! OK -- wreg (002,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:08.490152 : ATTN notify apat = 0001 lams = 0 dt=0.152939 -- wtlam apat=0001 to=10.000 T=0.009 OK ++ attn (175,00017) d=0001! s=00! OK -- rreg (250,00007) a=000d(sr.sstat ) d=c230! s=00| OK -- rreg (260,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ wreg (012,00017) a=0005(sr.maddrl) d=1000 s=00! OK -- wreg (022,00007) a=0006(sr.mcmd ) d=4f00 s=00! OK -- rreg (270,00007) a=0002(sr.mdoh ) d=1234! s=00! OK -- rreg (300,00007) a=0003(sr.mdol ) d=0000! s=00! OK -- wreg (032,00007) a=0005(sr.maddrl) d=1011 s=00! OK -- wreg (042,00007) a=0006(sr.mcmd ) d=4f10 s=00! OK -- rreg (310,00007) a=0002(sr.mdoh ) d=1234! s=00! OK -- rreg (320,00007) a=0003(sr.mdol ) d=0011! s=00! OK -- wreg (052,00007) a=0005(sr.maddrl) d=1022 s=00! OK -- wreg (062,00007) a=0006(sr.mcmd ) d=4f20 s=00! OK -- rreg (330,00007) a=0002(sr.mdoh ) d=1234! s=00! OK -- rreg (340,00007) a=0003(sr.mdol ) d=0022! s=00! OK -- wreg (072,00007) a=0005(sr.maddrl) d=1033 s=00! OK -- wreg (102,00007) a=0006(sr.mcmd ) d=4f30 s=00! OK -- rreg (350,00007) a=0002(sr.mdoh ) d=1234! s=00! OK -- rreg (360,00027) a=0003(sr.mdol ) d=0033! s=00! OK # test 11: wloop option ++ wreg (112,00037) a=0009(sr.saddr ) d=0000 s=00! OK ++ wblk (213,00037) a=000a(sr.sblk ) n= 32= 32 s=00! OK 0: 01f0 0000 0010 2030 01f0 0001 0111 2131 00f0 0000 0010 11: 2030 01f0 0002 0212 2232 00f0 0001 0111 2131 01f0 0003 22: 0313 2333 00f0 0002 0212 2232 00f0 0003 0313 2333 ++ wreg (122,00017) a=0004(sr.maddrh) d=003f s=00! OK -- wreg (132,00007) a=0005(sr.maddrl) d=fff0 s=00! OK -- wreg (142,00007) a=0000(sr.mdih ) d=0000 s=00! OK -- wreg (152,00027) a=0001(sr.mdil ) d=0000 s=00! OK ++ wreg (162,00017) a=0008(sr.slim ) d=0007 s=00! OK -- wreg (172,00007) a=000d(sr.sstat ) d=01b0 s=00! OK -- wreg (202,00027) a=000e(sr.sstart) d=0000 s=00! OK -I- 08:16:08.831960 : ATTN notify apat = 0001 lams = 0 dt=0.341807 tst_sram::test_all errcnt = 0 --> PASS 610.0 ns 40: START rlink_cext-I: seen EOF, schedule clock stop and exit 779450.0 ns 77924: DONE ../../../../vlib/rlink/tbcore/tbcore_rlink.vhd:294:5:@779550ns:(report failure): Simulation Finished tb_tst_sram_n3:error: report failed from: process work.tbcore_rlink(sim).proc_stim at tbcore_rlink.vhd:294 tb_tst_sram_n3:error: simulation failed -- wtlam apat=0001 to=10.000 T=0.114 OK ++ attn (205,00017) d=0001! s=00! OK -- rreg (370,00007) a=000d(sr.sstat ) d=c1b0! s=00| OK -- rreg (000,00027) a=0009(sr.saddr ) d=0008! s=00| OK ++ rreg (010,00017) a=0004(sr.maddrh) d=003f! s=00! OK -- rreg (020,00027) a=0005(sr.maddrl) d=ffff! s=00! OK ++ wreg (212,00017) a=0004(sr.maddrh) d=003f s=00! OK -- wreg (222,00007) a=0005(sr.maddrl) d=fffc s=00! OK -- rblk (201,00027) a=0007(sr.mblk ) n= 8= 8 s=00! OK 0: 0313! 2333! 0212! 2232! 0111! 2131! 0010! 2030! real 0m5.272s user 0m5.208s sys 0m0.108s