tbw-I: define tb_pdp11core_stim -> tb_pdp11core_stim.dat
../../src/ieee/numeric_std-body.v93:1309:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1157:7:@0ms:(assertion warning): NUMERIC_STD."<": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1309:7:@0ms:(assertion warning): NUMERIC_STD."<=": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE
../../src/ieee/numeric_std-body.v93:1157:7:@0ms:(assertion warning): NUMERIC_STD."<": metavalue detected, returning FALSE
../../src/synopsys/std_logic_arith.vhdl:2081:12:@0ms:(assertion warning): CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
.reset
C "Code 0" Some elementary initial tests
C write registers
2 wreg 0 000001 0 1 0 0 000001 000000 00
2 wreg 1 000101 0 1 0 0 000101 000000 00
2 wreg 2 000201 0 1 0 0 000201 000000 00
2 wreg 3 000301 0 1 0 0 000301 000000 00
2 wreg 4 000401 0 1 0 0 000401 000000 00
2 wreg 5 000501 0 1 0 0 000501 000000 00
2 wreg 6 000601 0 1 0 0 000601 000000 00
2 wreg 7 000701 0 1 0 0 000701 000000 00
C read registers
3 rreg 0 000001 0 1 0 0 000001 000000 00 CHECK OK
3 rreg 1 000101 0 1 0 0 000101 000000 00 CHECK OK
3 rreg 2 000201 0 1 0 0 000201 000000 00 CHECK OK
3 rreg 3 000301 0 1 0 0 000301 000000 00 CHECK OK
3 rreg 4 000401 0 1 0 0 000401 000000 00 CHECK OK
3 rreg 5 000501 0 1 0 0 000501 000000 00 CHECK OK
3 rreg 6 000601 0 1 0 0 000601 000000 00 CHECK OK
3 rreg 7 000701 0 1 0 0 000701 000000 00 CHECK OK
C write memory
3 wmem 0 007700 0 1 0 0 000701 000000 00
3 wmem 0 007710 0 1 0 0 000701 000000 00
3 wmem 0 007720 0 1 0 0 000701 000000 00
3 wmem 0 007730 0 1 0 0 000701 000000 00
C read memory
3 rmem 0 007700 0 1 0 0 007700 000000 00 CHECK OK
3 rmem 0 007710 0 1 0 0 007710 000000 00 CHECK OK
3 rmem 0 007720 0 1 0 0 007720 000000 00 CHECK OK
3 rmem 0 007730 0 1 0 0 007730 000000 00 CHECK OK
C write/read PSW via various mechanisms
C via wps/rps
2 wpsw 0 000017 0 1 0 0 000017 000000 00
3 rpsw 0 000017 0 1 0 0 000017 000000 00 CHECK OK
2 wpsw 0 000000 0 1 0 0 000000 000000 00
3 rpsw 0 000000 0 1 0 0 000000 000000 00 CHECK OK
C via 16bit cp addressing (wal 177776)
5 wmem 0 000017 0 1 0 0 000701 000000 00
5 rmem 0 000017 0 1 0 0 000017 000000 00 CHECK OK
3 rpsw 0 000017 0 1 0 0 000017 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 000701 000000 00
5 rmem 0 000000 0 1 0 0 000000 000000 00 CHECK OK
3 rpsw 0 000000 0 1 0 0 000000 000000 00 CHECK OK
C via 22bit cp addressing (wal 177776; wah 177)
5 wmem 0 000017 0 1 0 0 000701 000000 00
5 rmem 0 000017 0 1 0 0 000017 000000 00 CHECK OK
3 rpsw 0 000017 0 1 0 0 000017 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 000701 000000 00
5 rmem 0 000000 0 1 0 0 000000 000000 00 CHECK OK
3 rpsw 0 000000 0 1 0 0 000000 000000 00 CHECK OK
C via ibr (ibrb 177700)
5 wibr 0 000017 0 1 0 0 000701 000000 00
5 ribr 0 000017 0 1 0 0 000017 000000 00 CHECK OK
3 rpsw 0 000017 0 1 0 0 000017 000000 00 CHECK OK
5 wibr 0 000000 0 1 0 0 000701 000000 00
5 ribr 0 000000 0 1 0 0 000000 000000 00 CHECK OK
3 rpsw 0 000000 0 1 0 0 000000 000000 00 CHECK OK
C write register set 1, sm,um stack
2 wpsw 0 004000 0 1 0 0 004000 000000 00
2 wreg 0 010001 0 1 0 0 010001 000000 00
2 wreg 1 010101 0 1 0 0 010101 000000 00
2 wreg 2 010201 0 1 0 0 010201 000000 00
2 wreg 3 010301 0 1 0 0 010301 000000 00
2 wreg 4 010401 0 1 0 0 010401 000000 00
2 wreg 5 010501 0 1 0 0 010501 000000 00
2 wpsw 0 044000 0 1 0 0 044000 000000 00
2 wreg 6 010601 0 1 0 0 010601 000000 00
2 wpsw 0 144000 0 1 0 0 144000 000000 00
2 wreg 6 110601 0 1 0 0 110601 000000 00
C read all registers set 0/1, km,sm,um stack
2 wpsw 0 000000 0 1 0 0 000000 000000 00
3 rreg 0 000001 0 1 0 0 000001 000000 00 CHECK OK
3 rreg 1 000101 0 1 0 0 000101 000000 00 CHECK OK
3 rreg 2 000201 0 1 0 0 000201 000000 00 CHECK OK
3 rreg 3 000301 0 1 0 0 000301 000000 00 CHECK OK
3 rreg 4 000401 0 1 0 0 000401 000000 00 CHECK OK
3 rreg 5 000501 0 1 0 0 000501 000000 00 CHECK OK
3 rreg 6 000601 0 1 0 0 000601 000000 00 CHECK OK
3 rreg 7 000701 0 1 0 0 000701 000000 00 CHECK OK
2 wpsw 0 040000 0 1 0 0 040000 000000 00
3 rreg 6 010601 0 1 0 0 010601 000000 00 CHECK OK
2 wpsw 0 140000 0 1 0 0 140000 000000 00
3 rreg 6 110601 0 1 0 0 110601 000000 00 CHECK OK
2 wpsw 0 144000 0 1 0 0 144000 000000 00
3 rreg 0 010001 0 1 0 0 010001 000000 00 CHECK OK
3 rreg 1 010101 0 1 0 0 010101 000000 00 CHECK OK
3 rreg 2 010201 0 1 0 0 010201 000000 00 CHECK OK
3 rreg 3 010301 0 1 0 0 010301 000000 00 CHECK OK
3 rreg 4 010401 0 1 0 0 010401 000000 00 CHECK OK
3 rreg 5 010501 0 1 0 0 010501 000000 00 CHECK OK
C write IB space: MMU SAR supervisor mode (16 bit regs)
5 wmem 0 012340 0 1 0 0 010501 000000 00
5 wmem 0 012342 0 1 0 0 010501 000000 00
5 wmem 0 012344 0 1 0 0 010501 000000 00
C read IB space: MMU SAR supervisor mode (16 bit regs)
5 rmem 0 012340 0 1 0 0 012340 000000 00 CHECK OK
5 rmem 0 012342 0 1 0 0 012342 000000 00 CHECK OK
5 rmem 0 012344 0 1 0 0 012344 000000 00 CHECK OK
C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
5 ribr 0 012340 0 1 0 0 012340 000000 00 CHECK OK
5 ribr 0 012342 0 1 0 0 012342 000000 00 CHECK OK
5 ribr 0 012344 0 1 0 0 012344 000000 00 CHECK OK
C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
5 wibr 0 177000 0 1 0 0 010501 000000 00
5 wibr 0 177002 0 1 0 0 010501 000000 00
5 wibr 0 177004 0 1 0 0 010501 000000 00
5 rmem 0 012000 0 1 0 0 012000 000000 00 CHECK OK
5 rmem 0 012002 0 1 0 0 012002 000000 00 CHECK OK
5 rmem 0 012004 0 1 0 0 012004 000000 00 CHECK OK
5 wibr 0 000377 0 1 0 0 010501 000000 00
5 wibr 0 022377 0 1 0 0 010501 000000 00
5 wibr 0 044377 0 1 0 0 010501 000000 00
5 rmem 0 000000 0 1 0 0 000000 000000 00 CHECK OK
5 rmem 0 022002 0 1 0 0 022002 000000 00 CHECK OK
5 rmem 0 044004 0 1 0 0 044004 000000 00 CHECK OK
5 wibr 0 012340 0 1 0 0 010501 000000 00
5 wibr 0 012342 0 1 0 0 010501 000000 00
5 wibr 0 012344 0 1 0 0 010501 000000 00
5 rmem 0 012340 0 1 0 0 012340 000000 00 CHECK OK
5 rmem 0 012342 0 1 0 0 012342 000000 00 CHECK OK
5 rmem 0 012344 0 1 0 0 012344 000000 00 CHECK OK
C test access error handling to memory (use 17740000)
C with wm/rm
3 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
3 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
C with bwm/brm
3 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
3 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
3 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
3 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
C test access error handling to IB space (use 00160016)
C (is above ibd_ibmon decoded range, and below other debug stuff)
C with wm/rm
5 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
5 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
C with bwm/brm
5 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
5 wmem 0 000000 0 1 0 1 010501 000000 00 CHECK CMDMERR SEEN
5 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
5 rmem 0 000000 0 1 0 1 000000 000000 00 CHECK CMDMERR SEEN
C Setup trap catchers
3 wmem 0 000006 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000012 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000016 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000022 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000026 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000032 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000036 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000242 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000246 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 000252 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
C Setup MMU
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 077406 0 1 0 0 010501 000000 00
5 wmem 0 000000 0 1 0 0 010501 000000 00
5 wmem 0 000200 0 1 0 0 010501 000000 00
5 wmem 0 000400 0 1 0 0 010501 000000 00
5 wmem 0 000600 0 1 0 0 010501 000000 00
5 wmem 0 001000 0 1 0 0 010501 000000 00
5 wmem 0 001200 0 1 0 0 010501 000000 00
5 wmem 0 001400 0 1 0 0 010501 000000 00
5 wmem 0 177600 0 1 0 0 010501 000000 00
C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions)
3 wmem 0 000261 0 1 0 0 010501 000000 00
3 wmem 0 000250 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 005202 0 1 0 0 010501 000000 00
3 wmem 0 005202 0 1 0 0 010501 000000 00
3 wmem 0 005202 0 1 0 0 010501 000000 00
3 wmem 0 005202 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 005303 0 1 0 0 010501 000000 00
3 wmem 0 001376 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
3 wmem 0 005201 0 1 0 0 010501 000000 00
3 wmem 0 077002 0 1 0 0 010501 000000 00
3 wmem 0 000000 0 1 0 0 010501 000000 00
C Exec code 1 (very basics: start; 'simple' instructions)
C Exec test 1.1 (sec+clc+halt)
2 wreg 7 002100 0 1 0 0 002100 000000 00
2 wpsw 0 000010 0 1 0 0 000010 000000 00
2 sta 0 000000 0 1 0 0 010501 100000 07
13 ---- - ------ 0 0 0 0 010501 000000 01 WAIT GO OK
3 rreg 7 002106 0 1 0 0 002106 000000 01 CHECK OK
3 rpsw 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 1.2 (4 *inc R2, starting from -2)
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 cres 0 000000 0 1 0 0 002106 000000 00
2 wreg 7 002120 0 1 0 0 002120 000000 00
2 sta 0 000000 0 1 0 0 002106 100000 07
13 ---- - ------ 0 0 0 0 002106 000000 01 WAIT GO OK
3 rreg 2 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rreg 7 002132 0 1 0 0 002132 000000 01 CHECK OK
C Exec test 1.3 (dec r3; bne -2; halt)
2 wreg 3 000002 0 1 0 0 000002 000000 01
2 cres 0 000000 0 1 0 0 002132 000000 00
2 wreg 7 002140 0 1 0 0 002140 000000 00
2 sta 0 000000 0 1 0 0 002132 100000 07
16 ---- - ------ 0 0 0 0 002132 000000 01 WAIT GO OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 7 002146 0 1 0 0 002146 000000 01 CHECK OK
C Exec test 1.4 (inc r1; sob r0,-2; halt)
2 wreg 0 000002 0 1 0 0 000002 000000 01
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 cres 0 000000 0 1 0 0 002146 000000 00
2 wreg 7 002160 0 1 0 0 002160 000000 00
2 sta 0 000000 0 1 0 0 002146 100000 07
18 ---- - ------ 0 0 0 0 002146 000000 01 WAIT GO OK
3 rreg 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 1 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rreg 7 002166 0 1 0 0 002166 000000 01 CHECK OK
C Setup code 2 [base 2200] (bpt against trap catcher @14)
3 wmem 0 000257 0 1 0 0 002166 000000 01
3 wmem 0 000261 0 1 0 0 002166 000000 01
3 wmem 0 000003 0 1 0 0 002166 000000 01
3 wmem 0 000000 0 1 0 0 002166 000000 01
C Exec code 2 (bpt against trap catcher @14)
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 002166 000000 00
2 wreg 7 002200 0 1 0 0 002200 000000 00
2 sta 0 000000 0 1 0 0 002166 100000 07
27 ---- - ------ 0 0 0 0 002166 000000 01 WAIT GO OK
3 rreg 6 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rreg 7 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 002206 0 1 0 0 002206 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt)
3 wmem 0 000257 0 1 0 0 000020 000000 01
3 wmem 0 000003 0 1 0 0 000020 000000 01
3 wmem 0 005201 0 1 0 0 000020 000000 01
3 wmem 0 000000 0 1 0 0 000020 000000 01
3 wmem 0 002320 0 1 0 0 000020 000000 01
3 wmem 0 000002 0 1 0 0 000020 000000 01
3 wmem 0 005200 0 1 0 0 000020 000000 01
3 wmem 0 000006 0 1 0 0 000020 000000 01
3 wmem 0 000000 0 1 0 0 000020 000000 01
C Exec code 3 (bpt against trap handler doing inc r0; rtt)
2 wreg 0 000000 0 1 0 0 000000 000000 01
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000020 000000 00
2 wreg 7 002300 0 1 0 0 002300 000000 00
2 sta 0 000000 0 1 0 0 000020 100000 07
35 ---- - ------ 0 0 0 0 000020 000000 01 WAIT GO OK
3 rreg 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rreg 1 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 002310 0 1 0 0 002310 000000 01 CHECK OK
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1)
3 wmem 0 000006 0 1 0 0 002310 000000 01
3 wmem 0 005201 0 1 0 0 002310 000000 01
3 wmem 0 005201 0 1 0 0 002310 000000 01
3 wmem 0 000000 0 1 0 0 002310 000000 01
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1)
2 wreg 0 000000 0 1 0 0 000000 000000 01
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 wreg 6 001374 0 1 0 0 001374 000000 01
3 wmem 0 002402 0 1 0 0 002310 000000 01
3 wmem 0 000020 0 1 0 0 002310 000000 01
2 cres 0 000000 0 1 0 0 002310 000000 00
2 wreg 7 002400 0 1 0 0 002400 000000 00
2 sta 0 000000 0 1 0 0 002310 100000 07
63 ---- - ------ 0 0 0 0 002310 000000 01 WAIT GO OK
3 rreg 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rreg 1 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 002410 0 1 0 0 002410 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 002410 000000 00
3 wmem 0 000016 0 1 0 0 002410 000000 00
3 wmem 0 000000 0 1 0 0 002410 000000 00
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
3 wmem 0 011001 0 1 0 0 002410 000000 00
3 wmem 0 012002 0 1 0 0 002410 000000 00
3 wmem 0 012003 0 1 0 0 002410 000000 00
3 wmem 0 014004 0 1 0 0 002410 000000 00
3 wmem 0 013005 0 1 0 0 002410 000000 00
3 wmem 0 000000 0 1 0 0 002410 000000 00
3 wmem 0 000070 0 1 0 0 002410 000000 00
3 wmem 0 002550 0 1 0 0 002410 000000 00
3 wmem 0 000072 0 1 0 0 002410 000000 00
3 wmem 0 000074 0 1 0 0 002410 000000 00
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
2 wreg 0 002540 0 1 0 0 002540 000000 00
2 wreg 1 000000 0 1 0 0 000000 000000 00
2 wreg 2 000000 0 1 0 0 000000 000000 00
2 wreg 3 000000 0 1 0 0 000000 000000 00
2 wreg 4 000000 0 1 0 0 000000 000000 00
2 wreg 5 000000 0 1 0 0 000000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 cres 0 000000 0 1 0 0 002410 000000 00
2 wreg 7 002500 0 1 0 0 002500 000000 00
2 sta 0 000000 0 1 0 0 002410 100000 07
33 ---- - ------ 0 0 0 0 002410 000000 01 WAIT GO OK
3 rreg 0 002544 0 1 0 0 002544 000000 01 CHECK OK
3 rreg 1 000070 0 1 0 0 000070 000000 01 CHECK OK
3 rreg 2 000070 0 1 0 0 000070 000000 01 CHECK OK
3 rreg 3 002550 0 1 0 0 002550 000000 01 CHECK OK
3 rreg 4 002550 0 1 0 0 002550 000000 01 CHECK OK
3 rreg 5 000072 0 1 0 0 000072 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 002514 0 1 0 0 002514 000000 01 CHECK OK
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
3 wmem 0 016001 0 1 0 0 002514 000000 01
3 wmem 0 000002 0 1 0 0 002514 000000 01
3 wmem 0 017002 0 1 0 0 002514 000000 01
3 wmem 0 000002 0 1 0 0 002514 000000 01
3 wmem 0 012703 0 1 0 0 002514 000000 01
3 wmem 0 000377 0 1 0 0 002514 000000 01
3 wmem 0 013704 0 1 0 0 002514 000000 01
3 wmem 0 002552 0 1 0 0 002514 000000 01
3 wmem 0 112705 0 1 0 0 002514 000000 01
3 wmem 0 000377 0 1 0 0 002514 000000 01
3 wmem 0 000000 0 1 0 0 002514 000000 01
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
2 wreg 0 002540 0 1 0 0 002540 000000 01
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 wreg 2 000000 0 1 0 0 000000 000000 01
2 wreg 3 000000 0 1 0 0 000000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 002514 000000 00
2 wreg 7 002600 0 1 0 0 002600 000000 00
2 sta 0 000000 0 1 0 0 002514 100000 07
38 ---- - ------ 0 0 0 0 002514 000000 01 WAIT GO OK
3 rreg 0 002540 0 1 0 0 002540 000000 01 CHECK OK
3 rreg 1 002550 0 1 0 0 002550 000000 01 CHECK OK
3 rreg 2 000072 0 1 0 0 000072 000000 01 CHECK OK
3 rreg 3 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rreg 4 000074 0 1 0 0 000074 000000 01 CHECK OK
3 rreg 5 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 002626 0 1 0 0 002626 000000 01 CHECK OK
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes)
3 wmem 0 012710 0 1 0 0 002626 000000 01
3 wmem 0 000110 0 1 0 0 002626 000000 01
3 wmem 0 012721 0 1 0 0 002626 000000 01
3 wmem 0 000120 0 1 0 0 002626 000000 01
3 wmem 0 012732 0 1 0 0 002626 000000 01
3 wmem 0 000130 0 1 0 0 002626 000000 01
3 wmem 0 012743 0 1 0 0 002626 000000 01
3 wmem 0 000140 0 1 0 0 002626 000000 01
3 wmem 0 012754 0 1 0 0 002626 000000 01
3 wmem 0 000150 0 1 0 0 002626 000000 01
3 wmem 0 012760 0 1 0 0 002626 000000 01
3 wmem 0 000160 0 1 0 0 002626 000000 01
3 wmem 0 000012 0 1 0 0 002626 000000 01
3 wmem 0 012770 0 1 0 0 002626 000000 01
3 wmem 0 000170 0 1 0 0 002626 000000 01
3 wmem 0 000024 0 1 0 0 002626 000000 01
3 wmem 0 010546 0 1 0 0 002626 000000 01
3 wmem 0 000000 0 1 0 0 002626 000000 01
3 wmem 0 002754 0 1 0 0 002626 000000 01
3 wmem 0 002760 0 1 0 0 002626 000000 01
3 wmem 0 002764 0 1 0 0 002626 000000 01
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes)
2 wreg 0 002750 0 1 0 0 002750 000000 01
2 wreg 1 002752 0 1 0 0 002752 000000 01
2 wreg 2 002770 0 1 0 0 002770 000000 01
2 wreg 3 002760 0 1 0 0 002760 000000 01
2 wreg 4 002774 0 1 0 0 002774 000000 01
2 wreg 5 000666 0 1 0 0 000666 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 002626 000000 00
2 wreg 7 002700 0 1 0 0 002700 000000 00
2 sta 0 000000 0 1 0 0 002626 100000 07
72 ---- - ------ 0 0 0 0 002626 000000 01 WAIT GO OK
3 rreg 0 002750 0 1 0 0 002750 000000 01 CHECK OK
3 rreg 1 002754 0 1 0 0 002754 000000 01 CHECK OK
3 rreg 2 002772 0 1 0 0 002772 000000 01 CHECK OK
3 rreg 3 002756 0 1 0 0 002756 000000 01 CHECK OK
3 rreg 4 002772 0 1 0 0 002772 000000 01 CHECK OK
3 rreg 5 000666 0 1 0 0 000666 000000 01 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 01 CHECK OK
3 rreg 7 002744 0 1 0 0 002744 000000 01 CHECK OK
3 rmem 0 000110 0 1 0 0 000110 000000 01 CHECK OK
3 rmem 0 000120 0 1 0 0 000120 000000 01 CHECK OK
3 rmem 0 000130 0 1 0 0 000130 000000 01 CHECK OK
3 rmem 0 000140 0 1 0 0 000140 000000 01 CHECK OK
3 rmem 0 000150 0 1 0 0 000150 000000 01 CHECK OK
3 rmem 0 000160 0 1 0 0 000160 000000 01 CHECK OK
3 rmem 0 000170 0 1 0 0 000170 000000 01 CHECK OK
3 rmem 0 000666 0 1 0 0 000666 000000 01 CHECK OK
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes)
3 wmem 0 005210 0 1 0 0 002744 000000 01
3 wmem 0 005221 0 1 0 0 002744 000000 01
3 wmem 0 005232 0 1 0 0 002744 000000 01
3 wmem 0 005243 0 1 0 0 002744 000000 01
3 wmem 0 005254 0 1 0 0 002744 000000 01
3 wmem 0 005260 0 1 0 0 002744 000000 01
3 wmem 0 000012 0 1 0 0 002744 000000 01
3 wmem 0 005270 0 1 0 0 002744 000000 01
3 wmem 0 000024 0 1 0 0 002744 000000 01
3 wmem 0 000000 0 1 0 0 002744 000000 01
3 wmem 0 000110 0 1 0 0 002744 000000 01
3 wmem 0 000120 0 1 0 0 002744 000000 01
3 wmem 0 000130 0 1 0 0 002744 000000 01
3 wmem 0 000140 0 1 0 0 002744 000000 01
3 wmem 0 000150 0 1 0 0 002744 000000 01
3 wmem 0 000160 0 1 0 0 002744 000000 01
3 wmem 0 000170 0 1 0 0 002744 000000 01
3 wmem 0 003054 0 1 0 0 002744 000000 01
3 wmem 0 003060 0 1 0 0 002744 000000 01
3 wmem 0 003064 0 1 0 0 002744 000000 01
C Exec code 10 (dstm modes: inc xxx: all non-r modes)
2 wreg 0 003050 0 1 0 0 003050 000000 01
2 wreg 1 003052 0 1 0 0 003052 000000 01
2 wreg 2 003070 0 1 0 0 003070 000000 01
2 wreg 3 003060 0 1 0 0 003060 000000 01
2 wreg 4 003074 0 1 0 0 003074 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 002744 000000 00
2 wreg 7 003000 0 1 0 0 003000 000000 00
2 sta 0 000000 0 1 0 0 002744 100000 07
66 ---- - ------ 0 0 0 0 002744 000000 01 WAIT GO OK
3 rreg 0 003050 0 1 0 0 003050 000000 01 CHECK OK
3 rreg 1 003054 0 1 0 0 003054 000000 01 CHECK OK
3 rreg 2 003072 0 1 0 0 003072 000000 01 CHECK OK
3 rreg 3 003056 0 1 0 0 003056 000000 01 CHECK OK
3 rreg 4 003072 0 1 0 0 003072 000000 01 CHECK OK
3 rreg 7 003024 0 1 0 0 003024 000000 01 CHECK OK
3 rmem 0 000111 0 1 0 0 000111 000000 01 CHECK OK
3 rmem 0 000121 0 1 0 0 000121 000000 01 CHECK OK
3 rmem 0 000131 0 1 0 0 000131 000000 01 CHECK OK
3 rmem 0 000141 0 1 0 0 000141 000000 01 CHECK OK
3 rmem 0 000151 0 1 0 0 000151 000000 01 CHECK OK
3 rmem 0 000161 0 1 0 0 000161 000000 01 CHECK OK
3 rmem 0 000171 0 1 0 0 000171 000000 01 CHECK OK
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes)
3 wmem 0 004710 0 1 0 0 003024 000000 01
3 wmem 0 004721 0 1 0 0 003024 000000 01
3 wmem 0 004732 0 1 0 0 003024 000000 01
3 wmem 0 004743 0 1 0 0 003024 000000 01
3 wmem 0 004754 0 1 0 0 003024 000000 01
3 wmem 0 004760 0 1 0 0 003024 000000 01
3 wmem 0 000050 0 1 0 0 003024 000000 01
3 wmem 0 004770 0 1 0 0 003024 000000 01
3 wmem 0 177734 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 003230 0 1 0 0 003024 000000 01
3 wmem 0 003250 0 1 0 0 003024 000000 01
3 wmem 0 003270 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000110 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000120 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000130 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000140 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000150 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000160 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
3 wmem 0 012725 0 1 0 0 003024 000000 01
3 wmem 0 000170 0 1 0 0 003024 000000 01
3 wmem 0 000207 0 1 0 0 003024 000000 01
3 wmem 0 000000 0 1 0 0 003024 000000 01
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes)
2 wreg 0 003210 0 1 0 0 003210 000000 01
2 wreg 1 003220 0 1 0 0 003220 000000 01
2 wreg 2 003140 0 1 0 0 003140 000000 01
2 wreg 3 003242 0 1 0 0 003242 000000 01
2 wreg 4 003144 0 1 0 0 003144 000000 01
2 wreg 5 003160 0 1 0 0 003160 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 003024 000000 00
2 wreg 7 003100 0 1 0 0 003100 000000 00
2 sta 0 000000 0 1 0 0 003024 100000 07
167 ---- - ------ 0 0 0 0 003024 000000 01 WAIT GO OK
3 rreg 0 003210 0 1 0 0 003210 000000 01 CHECK OK
3 rreg 1 003222 0 1 0 0 003222 000000 01 CHECK OK
3 rreg 2 003142 0 1 0 0 003142 000000 01 CHECK OK
3 rreg 3 003240 0 1 0 0 003240 000000 01 CHECK OK
3 rreg 4 003142 0 1 0 0 003142 000000 01 CHECK OK
3 rreg 5 003176 0 1 0 0 003176 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 003124 0 1 0 0 003124 000000 01 CHECK OK
3 rmem 0 000110 0 1 0 0 000110 000000 01 CHECK OK
3 rmem 0 000120 0 1 0 0 000120 000000 01 CHECK OK
3 rmem 0 000130 0 1 0 0 000130 000000 01 CHECK OK
3 rmem 0 000140 0 1 0 0 000140 000000 01 CHECK OK
3 rmem 0 000150 0 1 0 0 000150 000000 01 CHECK OK
3 rmem 0 000160 0 1 0 0 000160 000000 01 CHECK OK
3 rmem 0 000170 0 1 0 0 000170 000000 01 CHECK OK
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 012710 0 1 0 0 003124 000000 01
3 wmem 0 030000 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000263 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000237 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000274 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000233 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000241 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 112710 0 1 0 0 003124 000000 01
3 wmem 0 000040 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 112711 0 1 0 0 003124 000000 01
3 wmem 0 000020 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 005010 0 1 0 0 003124 000000 01
3 wmem 0 011025 0 1 0 0 003124 000000 01
3 wmem 0 000000 0 1 0 0 003124 000000 01
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr)
2 wpsw 0 000017 0 1 0 0 000017 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 177777 0 1 0 0 177777 000000 01
2 wreg 5 003400 0 1 0 0 003400 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 003124 000000 00
2 wreg 7 003300 0 1 0 0 003300 000000 00
2 sta 0 000000 0 1 0 0 003124 100000 07
149 ---- - ------ 0 0 0 0 003124 000000 01 WAIT GO OK
3 rreg 5 003424 0 1 0 0 003424 000000 01 CHECK OK
3 rreg 7 003356 0 1 0 0 003356 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 030000 0 1 0 0 030000 000000 01 CHECK OK
3 rmem 0 030003 0 1 0 0 030003 000000 01 CHECK OK
3 rmem 0 030341 0 1 0 0 030341 000000 01 CHECK OK
3 rmem 0 030355 0 1 0 0 030355 000000 01 CHECK OK
3 rmem 0 030141 0 1 0 0 030141 000000 01 CHECK OK
3 rmem 0 030140 0 1 0 0 030140 000000 01 CHECK OK
3 rmem 0 030040 0 1 0 0 030040 000000 01 CHECK OK
3 rmem 0 010040 0 1 0 0 010040 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running)
3 wmem 0 000001 0 1 0 0 003356 000000 01
3 wmem 0 000001 0 1 0 0 003356 000000 01
3 wmem 0 000001 0 1 0 0 003356 000000 01
3 wmem 0 000000 0 1 0 0 003356 000000 01
3 wmem 0 005700 0 1 0 0 003356 000000 01
3 wmem 0 001776 0 1 0 0 003356 000000 01
3 wmem 0 000000 0 1 0 0 003356 000000 01
3 wmem 0 000001 0 1 0 0 003356 000000 01
3 wmem 0 000000 0 1 0 0 003356 000000 01
C Exec code 13.1a (run WAIT)
2 cres 0 000000 0 1 0 0 003356 000000 00
2 wreg 7 003500 0 1 0 0 003500 000000 00
2 sta 0 000000 0 1 0 0 003356 100000 07
4 rreg 7 003502 0 1 0 0 003502 100000 07 CHECK OK
4 rreg 7 003502 0 1 0 0 003502 100000 07 CHECK OK
3 sto 0 000000 0 1 0 0 003502 000000 03
3 rreg 7 003502 0 1 0 0 003502 000000 03 CHECK OK
C Exec code 13.1b (step WAIT)
2 wreg 7 003500 0 1 0 0 003500 000000 03
7 step 0 000000 0 0 0 0 003502 000000 04 WAIT STEP OK
3 rreg 7 003502 0 1 0 0 003502 000000 04 CHECK OK
7 step 0 000000 0 0 0 0 003502 000000 04 WAIT STEP OK
3 rreg 7 003504 0 1 0 0 003504 000000 04 CHECK OK
7 step 0 000000 0 0 0 0 003504 000000 04 WAIT STEP OK
3 rreg 7 003506 0 1 0 0 003506 000000 04 CHECK OK
7 step 0 000000 0 0 0 0 003506 000000 01 WAIT STEP OK
3 rreg 7 003510 0 1 0 0 003510 000000 01 CHECK OK
C Exec code 13.2 (test bwm/brm while CPU busy looping)
2 wreg 0 000000 0 1 0 0 000000 000000 01
2 cres 0 000000 0 1 0 0 003510 000000 00
2 wreg 7 003520 0 1 0 0 003520 000000 00
2 sta 0 000000 0 1 0 0 003510 100000 07
7 wmem 0 003560 0 1 0 0 000000 100000 07
7 wmem 0 003562 0 1 0 0 001400 100000 07
7 wmem 0 003564 0 1 0 0 000000 100000 07
7 wmem 0 003566 0 1 0 0 001400 100000 07
7 wmem 0 003570 0 1 0 0 000000 100000 07
7 wmem 0 003572 0 1 0 0 001400 100000 07
7 wmem 0 003574 0 1 0 0 000000 100000 07
7 wmem 0 003576 0 1 0 0 001400 100000 07
7 rmem 0 003560 0 1 0 0 003560 100000 07 CHECK OK
7 rmem 0 003562 0 1 0 0 003562 100000 07 CHECK OK
7 rmem 0 003564 0 1 0 0 003564 100000 07 CHECK OK
7 rmem 0 003566 0 1 0 0 003566 100000 07 CHECK OK
7 rmem 0 003570 0 1 0 0 003570 100000 07 CHECK OK
7 rmem 0 003572 0 1 0 0 003572 100000 07 CHECK OK
7 rmem 0 003574 0 1 0 0 003574 100000 07 CHECK OK
7 rmem 0 003576 0 1 0 0 003576 100000 07 CHECK OK
6 wreg 0 000001 0 1 0 0 000001 100000 07
14 ---- - ------ 0 0 0 0 000001 000000 01 WAIT GO OK
3 rreg 7 003526 0 1 0 0 003526 000000 01 CHECK OK
C Exec code 13.3 (test bwm/brm while CPU on WAIT)
2 cres 0 000000 0 1 0 0 003526 000000 00
2 wreg 7 003540 0 1 0 0 003540 000000 00
2 sta 0 000000 0 1 0 0 003526 100000 07
7 wmem 0 073560 0 1 0 0 177777 100000 07
4 wmem 0 073562 0 1 0 0 177777 100000 07
4 wmem 0 073564 0 1 0 0 177777 100000 07
4 wmem 0 073566 0 1 0 0 177777 100000 07
4 wmem 0 073570 0 1 0 0 177777 100000 07
4 wmem 0 073572 0 1 0 0 177777 100000 07
4 wmem 0 073574 0 1 0 0 177777 100000 07
4 wmem 0 073576 0 1 0 0 177777 100000 07
4 rmem 0 073560 0 1 0 0 073560 100000 07 CHECK OK
4 rmem 0 073562 0 1 0 0 073562 100000 07 CHECK OK
4 rmem 0 073564 0 1 0 0 073564 100000 07 CHECK OK
4 rmem 0 073566 0 1 0 0 073566 100000 07 CHECK OK
4 rmem 0 073570 0 1 0 0 073570 100000 07 CHECK OK
4 rmem 0 073572 0 1 0 0 073572 100000 07 CHECK OK
4 rmem 0 073574 0 1 0 0 073574 100000 07 CHECK OK
4 rmem 0 073576 0 1 0 0 073576 100000 07 CHECK OK
3 sto 0 000000 0 1 0 0 177777 000000 03
3 rreg 7 003542 0 1 0 0 003542 000000 03 CHECK OK
C Setup code 15 [base 3600; use 36-37] (test 4 traps)
3 wmem 0 000003 0 1 0 0 003542 000000 03
3 wmem 0 000004 0 1 0 0 003542 000000 03
3 wmem 0 104077 0 1 0 0 003542 000000 03
3 wmem 0 104477 0 1 0 0 003542 000000 03
3 wmem 0 000000 0 1 0 0 003542 000000 03
3 wmem 0 010025 0 1 0 0 003542 000000 03
3 wmem 0 000405 0 1 0 0 003542 000000 03
3 wmem 0 010125 0 1 0 0 003542 000000 03
3 wmem 0 000403 0 1 0 0 003542 000000 03
3 wmem 0 010225 0 1 0 0 003542 000000 03
3 wmem 0 000401 0 1 0 0 003542 000000 03
3 wmem 0 010325 0 1 0 0 003542 000000 03
3 wmem 0 011604 0 1 0 0 003542 000000 03
3 wmem 0 016425 0 1 0 0 003542 000000 03
3 wmem 0 177776 0 1 0 0 003542 000000 03
3 wmem 0 000002 0 1 0 0 003542 000000 03
3 wmem 0 003620 0 1 0 0 003542 000000 03
3 wmem 0 000000 0 1 0 0 003542 000000 03
3 wmem 0 003624 0 1 0 0 003542 000000 03
3 wmem 0 000000 0 1 0 0 003542 000000 03
3 wmem 0 003630 0 1 0 0 003542 000000 03
3 wmem 0 000000 0 1 0 0 003542 000000 03
3 wmem 0 003634 0 1 0 0 003542 000000 03
3 wmem 0 000000 0 1 0 0 003542 000000 03
C Exec code 15 (test 4 traps)
2 wreg 0 000011 0 1 0 0 000011 000000 03
2 wreg 1 000022 0 1 0 0 000022 000000 03
2 wreg 2 000033 0 1 0 0 000033 000000 03
2 wreg 3 000044 0 1 0 0 000044 000000 03
2 wreg 5 003700 0 1 0 0 003700 000000 03
2 wreg 6 001400 0 1 0 0 001400 000000 03
2 cres 0 000000 0 1 0 0 003542 000000 00
2 wreg 7 003600 0 1 0 0 003600 000000 00
2 sta 0 000000 0 1 0 0 003542 100000 07
181 ---- - ------ 0 0 0 0 003542 000000 01 WAIT GO OK
3 rreg 5 003720 0 1 0 0 003720 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 003612 0 1 0 0 003612 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000033 0 1 0 0 000033 000000 01 CHECK OK
3 rmem 0 104077 0 1 0 0 104077 000000 01 CHECK OK
3 rmem 0 000044 0 1 0 0 000044 000000 01 CHECK OK
3 rmem 0 104477 0 1 0 0 104477 000000 01 CHECK OK
3 wmem 0 000016 0 1 0 0 003612 000000 01
3 wmem 0 000000 0 1 0 0 003612 000000 01
3 wmem 0 000022 0 1 0 0 003612 000000 01
3 wmem 0 000000 0 1 0 0 003612 000000 01
3 wmem 0 000032 0 1 0 0 003612 000000 01
3 wmem 0 000000 0 1 0 0 003612 000000 01
3 wmem 0 000036 0 1 0 0 003612 000000 01
3 wmem 0 000000 0 1 0 0 003612 000000 01
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
5 wmem 0 000002 0 1 0 0 003612 000000 01
5 wmem 0 000001 0 1 0 0 003612 000000 01
3 wmem 0 011105 0 1 0 0 003612 000000 01
3 wmem 0 012105 0 1 0 0 003612 000000 01
3 wmem 0 014105 0 1 0 0 003612 000000 01
3 wmem 0 012122 0 1 0 0 003612 000000 01
3 wmem 0 112105 0 1 0 0 003612 000000 01
3 wmem 0 112721 0 1 0 0 003612 000000 01
3 wmem 0 000200 0 1 0 0 003612 000000 01
3 wmem 0 000000 0 1 0 0 003612 000000 01
3 wmem 0 000001 0 1 0 0 003612 000000 01
3 wmem 0 000300 0 1 0 0 003612 000000 01
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
2 wreg 1 004040 0 1 0 0 004040 000000 01
2 wreg 2 004060 0 1 0 0 004060 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 wreg 7 004000 0 1 0 0 004000 000000 01
9 step 0 000000 0 0 0 0 003612 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 rmem 0 004000 0 1 0 0 004000 000000 04 CHECK OK
3 rreg 1 004040 0 1 0 0 004040 000000 04 CHECK OK
3 rreg 5 000001 0 1 0 0 000001 000000 04 CHECK OK
9 step 0 000000 0 0 0 0 000001 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000021 0 1 0 0 000021 000000 04 CHECK OK
5 rmem 0 004002 0 1 0 0 004002 000000 04 CHECK OK
3 rreg 1 004042 0 1 0 0 004042 000000 04 CHECK OK
3 rreg 5 000001 0 1 0 0 000001 000000 04 CHECK OK
10 step 0 000000 0 0 0 0 000001 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000361 0 1 0 0 000361 000000 04 CHECK OK
5 rmem 0 004004 0 1 0 0 004004 000000 04 CHECK OK
3 rreg 1 004040 0 1 0 0 004040 000000 04 CHECK OK
3 rreg 5 000001 0 1 0 0 000001 000000 04 CHECK OK
10 step 0 000000 0 0 0 0 000001 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 011021 0 1 0 0 011021 000000 04 CHECK OK
5 rmem 0 004006 0 1 0 0 004006 000000 04 CHECK OK
3 rreg 1 004042 0 1 0 0 004042 000000 04 CHECK OK
3 rreg 2 004062 0 1 0 0 004062 000000 04 CHECK OK
9 step 0 000000 0 0 0 0 004062 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000011 0 1 0 0 000011 000000 04 CHECK OK
5 rmem 0 004010 0 1 0 0 004010 000000 04 CHECK OK
3 rreg 1 004043 0 1 0 0 004043 000000 04 CHECK OK
3 rreg 5 177700 0 1 0 0 177700 000000 04 CHECK OK
10 step 0 000000 0 0 0 0 177700 000000 04 WAIT STEP OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 004427 0 1 0 0 004427 000000 04 CHECK OK
5 rmem 0 004012 0 1 0 0 004012 000000 04 CHECK OK
3 rreg 1 004044 0 1 0 0 004044 000000 04 CHECK OK
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
2 wpsw 0 000000 0 1 0 0 000000 000000 04
2 cres 0 000000 0 1 0 0 004044 000000 00
2 wreg 7 004030 0 1 0 0 004030 000000 00
2 sta 0 000000 0 1 0 0 004044 100000 07
5 ---- - ------ 0 0 0 0 004044 000000 01 WAIT GO OK
3 rreg 7 004032 0 1 0 0 004032 000000 01 CHECK OK
3 rpsw 0 000000 0 1 0 0 000000 000000 01 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
3 wmem 0 010124 0 1 0 0 004032 000000 01
3 wmem 0 020124 0 1 0 0 004032 000000 01
3 wmem 0 020224 0 1 0 0 004032 000000 01
3 wmem 0 020124 0 1 0 0 004032 000000 01
3 wmem 0 005024 0 1 0 0 004032 000000 01
3 wmem 0 030124 0 1 0 0 004032 000000 01
3 wmem 0 030124 0 1 0 0 004032 000000 01
3 wmem 0 040124 0 1 0 0 004032 000000 01
3 wmem 0 050124 0 1 0 0 004032 000000 01
3 wmem 0 060124 0 1 0 0 004032 000000 01
3 wmem 0 160124 0 1 0 0 004032 000000 01
3 wmem 0 005124 0 1 0 0 004032 000000 01
3 wmem 0 005224 0 1 0 0 004032 000000 01
3 wmem 0 005324 0 1 0 0 004032 000000 01
3 wmem 0 005424 0 1 0 0 004032 000000 01
3 wmem 0 005724 0 1 0 0 004032 000000 01
3 wmem 0 006024 0 1 0 0 004032 000000 01
3 wmem 0 006024 0 1 0 0 004032 000000 01
3 wmem 0 006124 0 1 0 0 004032 000000 01
3 wmem 0 006224 0 1 0 0 004032 000000 01
3 wmem 0 006224 0 1 0 0 004032 000000 01
3 wmem 0 006324 0 1 0 0 004032 000000 01
3 wmem 0 006324 0 1 0 0 004032 000000 01
3 wmem 0 060124 0 1 0 0 004032 000000 01
3 wmem 0 005524 0 1 0 0 004032 000000 01
3 wmem 0 160124 0 1 0 0 004032 000000 01
3 wmem 0 005624 0 1 0 0 004032 000000 01
3 wmem 0 000324 0 1 0 0 004032 000000 01
3 wmem 0 006724 0 1 0 0 004032 000000 01
3 wmem 0 074124 0 1 0 0 004032 000000 01
3 wmem 0 006724 0 1 0 0 004032 000000 01
3 wmem 0 000000 0 1 0 0 004032 000000 01
3 wmem 0 004270 0 1 0 0 004032 000000 01
3 wmem 0 000000 0 1 0 0 004032 000000 01
3 wmem 0 016625 0 1 0 0 004032 000000 01
3 wmem 0 000002 0 1 0 0 004032 000000 01
3 wmem 0 000006 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 004711 0 1 0 0 004032 000000 01
3 wmem 0 004711 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 000011 0 1 0 0 004032 000000 01
3 wmem 0 000066 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 123456 0 1 0 0 004032 000000 01
3 wmem 0 100201 0 1 0 0 004032 000000 01
3 wmem 0 002201 0 1 0 0 004032 000000 01
3 wmem 0 100200 0 1 0 0 004032 000000 01
3 wmem 0 000200 0 1 0 0 004032 000000 01
3 wmem 0 100200 0 1 0 0 004032 000000 01
3 wmem 0 000200 0 1 0 0 004032 000000 01
3 wmem 0 100200 0 1 0 0 004032 000000 01
3 wmem 0 177000 0 1 0 0 004032 000000 01
3 wmem 0 000200 0 1 0 0 004032 000000 01
3 wmem 0 004701 0 1 0 0 004032 000000 01
3 wmem 0 000200 0 1 0 0 004032 000000 01
3 wmem 0 111000 0 1 0 0 004032 000000 01
3 wmem 0 111111 0 1 0 0 004032 000000 01
3 wmem 0 070707 0 1 0 0 004032 000000 01
3 wmem 0 111111 0 1 0 0 004032 000000 01
C Exec code 17 (basic instruction and cc test)
2 wreg 1 004711 0 1 0 0 004711 000000 01
2 wreg 2 123456 0 1 0 0 123456 000000 01
2 wreg 4 004300 0 1 0 0 004300 000000 01
2 wreg 5 004500 0 1 0 0 004500 000000 01
2 wreg 6 001374 0 1 0 0 001374 000000 01
3 wmem 0 004100 0 1 0 0 004032 000000 01
3 wmem 0 000020 0 1 0 0 004032 000000 01
2 cres 0 000000 0 1 0 0 004032 000000 00
2 wreg 7 004274 0 1 0 0 004274 000000 00
2 sta 0 000000 0 1 0 0 004032 100000 07
1084 ---- - ------ 0 0 0 0 004032 000000 01 WAIT GO OK
3 rreg 1 004711 0 1 0 0 004711 000000 01 CHECK OK
3 rreg 2 123456 0 1 0 0 123456 000000 01 CHECK OK
3 rreg 4 004376 0 1 0 0 004376 000000 01 CHECK OK
3 rreg 5 004576 0 1 0 0 004576 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 004200 0 1 0 0 004200 000000 01 CHECK OK
3 rmem 0 004711 0 1 0 0 004711 000000 01 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 01 CHECK OK
3 rmem 0 004711 0 1 0 0 004711 000000 01 CHECK OK
3 rmem 0 004711 0 1 0 0 004711 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000066 0 1 0 0 000066 000000 01 CHECK OK
3 rmem 0 123046 0 1 0 0 123046 000000 01 CHECK OK
3 rmem 0 127757 0 1 0 0 127757 000000 01 CHECK OK
3 rmem 0 130367 0 1 0 0 130367 000000 01 CHECK OK
3 rmem 0 116545 0 1 0 0 116545 000000 01 CHECK OK
3 rmem 0 054321 0 1 0 0 054321 000000 01 CHECK OK
3 rmem 0 123457 0 1 0 0 123457 000000 01 CHECK OK
3 rmem 0 123455 0 1 0 0 123455 000000 01 CHECK OK
3 rmem 0 054322 0 1 0 0 054322 000000 01 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 01 CHECK OK
3 rmem 0 040100 0 1 0 0 040100 000000 01 CHECK OK
3 rmem 0 101100 0 1 0 0 101100 000000 01 CHECK OK
3 rmem 0 000401 0 1 0 0 000401 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 140100 0 1 0 0 140100 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 003711 0 1 0 0 003711 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 177770 0 1 0 0 177770 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000222 0 1 0 0 000222 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 074016 0 1 0 0 074016 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000032 0 1 0 0 000032 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 004200 000000 00
3 wmem 0 000016 0 1 0 0 004200 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
C Setup code 20 [base 4700] (check CPUERR and error handling)
3 wmem 0 010025 0 1 0 0 004200 000000 00
3 wmem 0 010025 0 1 0 0 004200 000000 00
3 wmem 0 010025 0 1 0 0 004200 000000 00
3 wmem 0 000101 0 1 0 0 004200 000000 00
3 wmem 0 004701 0 1 0 0 004200 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
3 wmem 0 014321 0 1 0 0 004200 000000 00
3 wmem 0 024321 0 1 0 0 004200 000000 00
3 wmem 0 064321 0 1 0 0 004200 000000 00
3 wmem 0 010046 0 1 0 0 004200 000000 00
3 wmem 0 000004 0 1 0 0 004200 000000 00
3 wmem 0 000006 0 1 0 0 004200 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
3 wmem 0 000012 0 1 0 0 004200 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
C Exec code 20 (check CPUERR and error handling)
C Exec test 20.1 (odd address abort)
2 cres 0 000000 0 1 0 0 004200 000000 00
2 wpsw 0 000000 0 1 0 0 000000 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
3 wmem 0 000000 0 1 0 0 004200 000000 00
5 rmem 0 000000 0 1 0 0 000000 000000 00 CHECK OK
2 wreg 0 000011 0 1 0 0 000011 000000 00
2 wreg 5 004775 0 1 0 0 004775 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 004700 0 1 0 0 004700 000000 00
20 step 0 000000 0 0 0 0 004200 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 004702 0 1 0 0 004702 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 rmem 0 000100 0 1 0 0 000100 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
C Exec test 20.2 (non-existent memory abort)
5 wmem 0 177400 0 1 0 0 001374 000000 04
5 wmem 0 000001 0 1 0 0 001374 000000 04
5 wmem 0 000020 0 1 0 0 001374 000000 04
2 wreg 5 140000 0 1 0 0 140000 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004702 0 1 0 0 004702 000000 04
20 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000040 0 1 0 0 000040 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
5 wmem 0 001400 0 1 0 0 001374 000000 04
C Exec test 20.3 (I/O bus timeout abort)
2 wreg 5 160000 0 1 0 0 160000 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004704 0 1 0 0 004704 000000 04
22 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000020 0 1 0 0 000020 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
C Exec test 20.4 (address error abort after jmp r1)
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004706 0 1 0 0 004706 000000 04
18 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
C Exec test 20.5 (address error abort after jsr pc,r1)
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004710 0 1 0 0 004710 000000 04
18 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
C Exec test 20.6 (halt in user mode)
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004712 0 1 0 0 004712 000000 04
2 wpsw 0 170000 0 1 0 0 170000 000000 04
18 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 004714 0 1 0 0 004714 000000 04 CHECK OK
3 rmem 0 170000 0 1 0 0 170000 000000 04 CHECK OK
5 rmem 0 000200 0 1 0 0 000200 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
2 wpsw 0 000000 0 1 0 0 000000 000000 04
3 wmem 0 000252 0 1 0 0 001374 000000 04
3 wmem 0 000000 0 1 0 0 001374 000000 04
5 wmem 0 000001 0 1 0 0 001374 000000 04
5 wmem 0 077400 0 1 0 0 001374 000000 04
C Exec test 20.7 (non resident abort)
2 wreg 1 020000 0 1 0 0 020000 000000 04
2 wreg 3 000016 0 1 0 0 000016 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004714 0 1 0 0 004714 000000 04
22 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 1 020002 0 1 0 0 020002 000000 04 CHECK OK
3 rreg 3 000014 0 1 0 0 000014 000000 04 CHECK OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 100003 0 1 0 0 100003 000000 04 CHECK OK
5 rmem 0 010763 0 1 0 0 010763 000000 04 CHECK OK
5 rmem 0 004714 0 1 0 0 004714 000000 04 CHECK OK
5 wmem 0 000001 0 1 0 0 001374 000000 04
C Exec test 20.8 (segment length violation abort)
5 wmem 0 001406 0 1 0 0 001374 000000 04
2 wreg 1 020400 0 1 0 0 020400 000000 04
2 wreg 3 000016 0 1 0 0 000016 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004716 0 1 0 0 004716 000000 04
22 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 1 020402 0 1 0 0 020402 000000 04 CHECK OK
3 rreg 3 000014 0 1 0 0 000014 000000 04 CHECK OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 040003 0 1 0 0 040003 000000 04 CHECK OK
5 rmem 0 010763 0 1 0 0 010763 000000 04 CHECK OK
5 rmem 0 004716 0 1 0 0 004716 000000 04 CHECK OK
5 wmem 0 000001 0 1 0 0 001374 000000 04
C Exec test 20.9 (read-only abort)
5 wmem 0 077402 0 1 0 0 001374 000000 04
2 wreg 1 020000 0 1 0 0 020000 000000 04
2 wreg 3 000016 0 1 0 0 000016 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004720 0 1 0 0 004720 000000 04
22 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 1 020002 0 1 0 0 020002 000000 04 CHECK OK
3 rreg 3 000014 0 1 0 0 000014 000000 04 CHECK OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 020003 0 1 0 0 020003 000000 04 CHECK OK
5 rmem 0 010763 0 1 0 0 010763 000000 04 CHECK OK
5 rmem 0 004720 0 1 0 0 004720 000000 04 CHECK OK
5 wmem 0 077406 0 1 0 0 001374 000000 04
5 wmem 0 000000 0 1 0 0 001374 000000 04
5 wmem 0 001001 0 1 0 0 001374 000000 04
5 wmem 0 077404 0 1 0 0 001374 000000 04
C Exec test 20.10 (trap on write)
2 wreg 1 020000 0 1 0 0 020000 000000 04
2 wreg 3 000016 0 1 0 0 000016 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004714 0 1 0 0 004714 000000 04
22 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 1 020002 0 1 0 0 020002 000000 04 CHECK OK
3 rreg 3 000014 0 1 0 0 000014 000000 04 CHECK OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 000016 0 1 0 0 000016 000000 04 CHECK OK
3 wmem 0 000000 0 1 0 0 001374 000000 04
5 rmem 0 011001 0 1 0 0 011001 000000 04 CHECK OK
5 rmem 0 010763 0 1 0 0 010763 000000 04 CHECK OK
5 rmem 0 004714 0 1 0 0 004714 000000 04 CHECK OK
C Exec test 20.11 (2nd write, should not trap again)
2 wreg 1 020002 0 1 0 0 020002 000000 04
2 wreg 3 000016 0 1 0 0 000016 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 004714 0 1 0 0 004714 000000 04
11 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 1 020004 0 1 0 0 020004 000000 04 CHECK OK
3 rreg 3 000014 0 1 0 0 000014 000000 04 CHECK OK
3 rreg 7 004716 0 1 0 0 004716 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
3 rmem 0 000016 0 1 0 0 000016 000000 04 CHECK OK
3 wmem 0 000000 0 1 0 0 001400 000000 04
5 rmem 0 011003 0 1 0 0 011003 000000 04 CHECK OK
5 rmem 0 010763 0 1 0 0 010763 000000 04 CHECK OK
5 rmem 0 004714 0 1 0 0 004714 000000 04 CHECK OK
5 wmem 0 077406 0 1 0 0 001400 000000 04
5 wmem 0 000000 0 1 0 0 001400 000000 04
C Exec test 20.12 (red stack abort when pushing data to stack)
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 000340 0 1 0 0 000340 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
21 step 0 000000 0 0 0 0 001400 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 rmem 0 000004 0 1 0 0 000004 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000000 000000 04
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push)
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400)
2 wpsw 0 000017 0 1 0 0 000017 000000 04
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 000400 0 1 0 0 000400 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
20 step 0 000000 0 0 0 0 000000 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000372 0 1 0 0 000372 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 04 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 04 CHECK OK
5 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000372 000000 04
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402)
2 wpsw 0 000017 0 1 0 0 000017 000000 04
2 wreg 6 000402 0 1 0 0 000402 000000 04
2 wreg 7 004724 0 1 0 0 004724 000000 04
28 step 0 000000 0 0 0 0 000372 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000372 0 1 0 0 000372 000000 04 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004726 0 1 0 0 004726 000000 04 CHECK OK
3 rmem 0 000017 0 1 0 0 000017 000000 04 CHECK OK
5 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000372 000000 04
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001)
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 001001 0 1 0 0 001001 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
21 step 0 000000 0 0 0 0 000372 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 rmem 0 000104 0 1 0 0 000104 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000000 000000 04
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
5 wmem 0 177400 0 1 0 0 000000 000000 04
5 wmem 0 000001 0 1 0 0 000000 000000 04
5 wmem 0 000020 0 1 0 0 000000 000000 04
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 140004 0 1 0 0 140004 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
21 step 0 000000 0 0 0 0 000000 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 rmem 0 000044 0 1 0 0 000044 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000000 000000 04
5 wmem 0 000000 0 1 0 0 000000 000000 04
5 wmem 0 001400 0 1 0 0 000000 000000 04
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004)
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 160004 0 1 0 0 160004 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
23 step 0 000000 0 0 0 0 000000 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 rmem 0 000024 0 1 0 0 000024 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000000 000000 04
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
5 wmem 0 000001 0 1 0 0 000000 000000 04
5 wmem 0 077400 0 1 0 0 000000 000000 04
2 wreg 0 123456 0 1 0 0 123456 000000 04
2 wreg 6 020004 0 1 0 0 020004 000000 04
2 wreg 7 004722 0 1 0 0 004722 000000 04
21 step 0 000000 0 0 0 0 000000 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 004724 0 1 0 0 004724 000000 04 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 04 CHECK OK
5 rmem 0 000104 0 1 0 0 000104 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 000000 000000 04
5 wmem 0 077406 0 1 0 0 000000 000000 04
5 wmem 0 000000 0 1 0 0 000000 000000 04
5 wmem 0 000000 0 1 0 0 000000 000000 04
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D)
5 wmem 0 077406 0 1 0 0 000000 000000 04
5 wmem 0 077406 0 1 0 0 000000 000000 04
5 wmem 0 000053 0 1 0 0 000000 000000 04
5 wmem 0 000055 0 1 0 0 000000 000000 04
5 wmem 0 000001 0 1 0 0 000000 000000 04
5 wmem 0 000001 0 1 0 0 000000 000000 04
3 wmem 0 006610 0 1 0 0 000000 000000 04
3 wmem 0 106610 0 1 0 0 000000 000000 04
3 wmem 0 006606 0 1 0 0 000000 000000 04
3 wmem 0 006510 0 1 0 0 000000 000000 04
3 wmem 0 106510 0 1 0 0 000000 000000 04
3 wmem 0 006506 0 1 0 0 000000 000000 04
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D)
2 wpsw 0 030000 0 1 0 0 030000 000000 04
3 wmem 0 012300 0 1 0 0 000000 000000 04
3 wmem 0 001230 0 1 0 0 000000 000000 04
3 wmem 0 000666 0 1 0 0 000000 000000 04
2 wreg 0 000002 0 1 0 0 000002 000000 04
2 wreg 6 001372 0 1 0 0 001372 000000 04
2 wreg 7 004740 0 1 0 0 004740 000000 04
10 step 0 000000 0 0 0 0 000000 000000 04 WAIT STEP OK
3 rreg 7 004742 0 1 0 0 004742 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 012300 0 1 0 0 012300 000000 04 CHECK OK
10 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 004744 0 1 0 0 004744 000000 04 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 04 CHECK OK
3 rmem 0 001230 0 1 0 0 001230 000000 04 CHECK OK
9 step 0 000000 0 0 0 0 001376 000000 04 WAIT STEP OK
3 rreg 7 004746 0 1 0 0 004746 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
2 wpsw 0 170000 0 1 0 0 170000 000000 04
3 rreg 6 000666 0 1 0 0 000666 000000 04 CHECK OK
2 wpsw 0 030000 0 1 0 0 030000 000000 04
3 wmem 0 000000 0 1 0 0 000666 000000 04
3 wmem 0 000000 0 1 0 0 000666 000000 04
3 wmem 0 000000 0 1 0 0 000666 000000 04
11 step 0 000000 0 0 0 0 000666 000000 04 WAIT STEP OK
3 rreg 7 004750 0 1 0 0 004750 000000 04 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 04 CHECK OK
3 rmem 0 012300 0 1 0 0 012300 000000 04 CHECK OK
11 step 0 000000 0 0 0 0 001376 000000 04 WAIT STEP OK
3 rreg 7 004752 0 1 0 0 004752 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 001230 0 1 0 0 001230 000000 04 CHECK OK
10 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 004754 0 1 0 0 004754 000000 04 CHECK OK
3 rreg 6 001372 0 1 0 0 001372 000000 04 CHECK OK
3 rmem 0 000666 0 1 0 0 000666 000000 04 CHECK OK
3 wmem 0 000000 0 1 0 0 001372 000000 04
3 wmem 0 000000 0 1 0 0 001372 000000 04
2 wpsw 0 000000 0 1 0 0 000000 000000 04
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D)
5 wmem 0 000002 0 1 0 0 001372 000000 04
5 wmem 0 000006 0 1 0 0 001372 000000 04
5 wmem 0 000053 0 1 0 0 001372 000000 04
5 wmem 0 000055 0 1 0 0 001372 000000 04
5 wmem 0 000001 0 1 0 0 001372 000000 04
5 wmem 0 000001 0 1 0 0 001372 000000 04
3 wmem 0 012746 0 1 0 0 001372 000000 04
3 wmem 0 174000 0 1 0 0 001372 000000 04
3 wmem 0 012746 0 1 0 0 001372 000000 04
3 wmem 0 000000 0 1 0 0 001372 000000 04
3 wmem 0 000002 0 1 0 0 001372 000000 04
3 wmem 0 005020 0 1 0 0 001372 000000 04
3 wmem 0 000340 0 1 0 0 001372 000000 04
3 wmem 0 011600 0 1 0 0 001372 000000 04
3 wmem 0 006560 0 1 0 0 001372 000000 04
3 wmem 0 177776 0 1 0 0 001372 000000 04
3 wmem 0 000000 0 1 0 0 001372 000000 04
3 wmem 0 005040 0 1 0 0 001372 000000 04
3 wmem 0 000340 0 1 0 0 001372 000000 04
3 wmem 0 005337 0 1 0 0 001372 000000 04
3 wmem 0 005256 0 1 0 0 001372 000000 04
3 wmem 0 001001 0 1 0 0 001372 000000 04
3 wmem 0 000000 0 1 0 0 001372 000000 04
3 wmem 0 013700 0 1 0 0 001372 000000 04
3 wmem 0 177572 0 1 0 0 001372 000000 04
3 wmem 0 042700 0 1 0 0 001372 000000 04
3 wmem 0 177741 0 1 0 0 001372 000000 04
3 wmem 0 062700 0 1 0 0 001372 000000 04
3 wmem 0 177600 0 1 0 0 001372 000000 04
3 wmem 0 105260 0 1 0 0 001372 000000 04
3 wmem 0 000001 0 1 0 0 001372 000000 04
3 wmem 0 010025 0 1 0 0 001372 000000 04
3 wmem 0 012025 0 1 0 0 001372 000000 04
3 wmem 0 013700 0 1 0 0 001372 000000 04
3 wmem 0 177574 0 1 0 0 001372 000000 04
3 wmem 0 010025 0 1 0 0 001372 000000 04
3 wmem 0 012701 0 1 0 0 001372 000000 04
3 wmem 0 000002 0 1 0 0 001372 000000 04
3 wmem 0 052737 0 1 0 0 001372 000000 04
3 wmem 0 004000 0 1 0 0 001372 000000 04
3 wmem 0 177776 0 1 0 0 001372 000000 04
3 wmem 0 005046 0 1 0 0 001372 000000 04
3 wmem 0 106506 0 1 0 0 001372 000000 04
3 wmem 0 010546 0 1 0 0 001372 000000 04
3 wmem 0 010446 0 1 0 0 001372 000000 04
3 wmem 0 010346 0 1 0 0 001372 000000 04
3 wmem 0 010246 0 1 0 0 001372 000000 04
3 wmem 0 010146 0 1 0 0 001372 000000 04
3 wmem 0 010046 0 1 0 0 001372 000000 04
3 wmem 0 042737 0 1 0 0 001372 000000 04
3 wmem 0 004000 0 1 0 0 001372 000000 04
3 wmem 0 177776 0 1 0 0 001372 000000 04
3 wmem 0 010002 0 1 0 0 001372 000000 04
3 wmem 0 110003 0 1 0 0 001372 000000 04
3 wmem 0 042702 0 1 0 0 001372 000000 04
3 wmem 0 177770 0 1 0 0 001372 000000 04
3 wmem 0 006302 0 1 0 0 001372 000000 04
3 wmem 0 060602 0 1 0 0 001372 000000 04
3 wmem 0 006203 0 1 0 0 001372 000000 04
3 wmem 0 006203 0 1 0 0 001372 000000 04
3 wmem 0 006203 0 1 0 0 001372 000000 04
3 wmem 0 160312 0 1 0 0 001372 000000 04
3 wmem 0 000300 0 1 0 0 001372 000000 04
3 wmem 0 077114 0 1 0 0 001372 000000 04
3 wmem 0 052737 0 1 0 0 001372 000000 04
3 wmem 0 004000 0 1 0 0 001372 000000 04
3 wmem 0 177776 0 1 0 0 001372 000000 04
3 wmem 0 012600 0 1 0 0 001372 000000 04
3 wmem 0 012601 0 1 0 0 001372 000000 04
3 wmem 0 012602 0 1 0 0 001372 000000 04
3 wmem 0 012603 0 1 0 0 001372 000000 04
3 wmem 0 012604 0 1 0 0 001372 000000 04
3 wmem 0 012605 0 1 0 0 001372 000000 04
3 wmem 0 106606 0 1 0 0 001372 000000 04
3 wmem 0 005726 0 1 0 0 001372 000000 04
3 wmem 0 042737 0 1 0 0 001372 000000 04
3 wmem 0 004000 0 1 0 0 001372 000000 04
3 wmem 0 177776 0 1 0 0 001372 000000 04
3 wmem 0 013700 0 1 0 0 001372 000000 04
3 wmem 0 177576 0 1 0 0 001372 000000 04
3 wmem 0 010025 0 1 0 0 001372 000000 04
3 wmem 0 010016 0 1 0 0 001372 000000 04
3 wmem 0 042737 0 1 0 0 001372 000000 04
3 wmem 0 160000 0 1 0 0 001372 000000 04
3 wmem 0 177572 0 1 0 0 001372 000000 04
3 wmem 0 000002 0 1 0 0 001372 000000 04
3 wmem 0 000000 0 1 0 0 001372 000000 04
3 wmem 0 000003 0 1 0 0 001372 000000 04
3 wmem 0 012706 0 1 0 0 001372 000000 04
3 wmem 0 000100 0 1 0 0 001372 000000 04
3 wmem 0 005000 0 1 0 0 001372 000000 04
3 wmem 0 012701 0 1 0 0 001372 000000 04
3 wmem 0 000074 0 1 0 0 001372 000000 04
3 wmem 0 062021 0 1 0 0 001372 000000 04
3 wmem 0 000137 0 1 0 0 001372 000000 04
3 wmem 0 000074 0 1 0 0 001372 000000 04
3 wmem 0 062021 0 1 0 0 001372 000000 04
3 wmem 0 062021 0 1 0 0 001372 000000 04
3 wmem 0 062021 0 1 0 0 001372 000000 04
3 wmem 0 104417 0 1 0 0 001372 000000 04
3 wmem 0 002001 0 1 0 0 001372 000000 04
3 wmem 0 002002 0 1 0 0 001372 000000 04
3 wmem 0 002003 0 1 0 0 001372 000000 04
3 wmem 0 002004 0 1 0 0 001372 000000 04
3 wmem 0 000300 0 1 0 0 001372 000000 04
3 wmem 0 000300 0 1 0 0 001372 000000 04
3 wmem 0 000300 0 1 0 0 001372 000000 04
3 wmem 0 000300 0 1 0 0 001372 000000 04
C Exec code 22 (MMU ; run user mode code with I/D)
2 wreg 5 005260 0 1 0 0 005260 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 005000 0 1 0 0 005000 000000 04
2 sta 0 000000 0 1 0 0 001372 100000 07
802 ---- - ------ 0 0 0 0 001372 000000 01 WAIT GO OK
3 rreg 6 001372 0 1 0 0 001372 000000 01 CHECK OK
3 rreg 7 005030 0 1 0 0 005030 000000 01 CHECK OK
3 rmem 0 104417 0 1 0 0 104417 000000 01 CHECK OK
3 rmem 0 000104 0 1 0 0 000104 000000 01 CHECK OK
3 rmem 0 174000 0 1 0 0 174000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 177620 0 1 0 0 177620 000000 01 CHECK OK
3 rmem 0 000406 0 1 0 0 000406 000000 01 CHECK OK
3 rmem 0 010420 0 1 0 0 010420 000000 01 CHECK OK
3 rmem 0 000076 0 1 0 0 000076 000000 01 CHECK OK
3 rmem 0 177600 0 1 0 0 177600 000000 01 CHECK OK
3 rmem 0 000402 0 1 0 0 000402 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 002301 0 1 0 0 002301 000000 01 CHECK OK
3 rmem 0 002302 0 1 0 0 002302 000000 01 CHECK OK
3 rmem 0 002303 0 1 0 0 002303 000000 01 CHECK OK
3 rmem 0 002304 0 1 0 0 002304 000000 01 CHECK OK
3 wmem 0 000036 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 000252 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
2 wpsw 0 000000 0 1 0 0 000000 000000 01
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch)
3 wmem 0 012012 0 1 0 0 005030 000000 01
3 wmem 0 004737 0 1 0 0 005030 000000 01
3 wmem 0 006000 0 1 0 0 005030 000000 01
3 wmem 0 077104 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 000230 0 1 0 0 005030 000000 01
3 wmem 0 005720 0 1 0 0 005030 000000 01
3 wmem 0 004737 0 1 0 0 005030 000000 01
3 wmem 0 006000 0 1 0 0 005030 000000 01
3 wmem 0 077104 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 000230 0 1 0 0 005030 000000 01
3 wmem 0 022020 0 1 0 0 005030 000000 01
3 wmem 0 004737 0 1 0 0 005030 000000 01
3 wmem 0 006000 0 1 0 0 005030 000000 01
3 wmem 0 077104 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 011203 0 1 0 0 005030 000000 01
3 wmem 0 012704 0 1 0 0 005030 000000 01
3 wmem 0 177774 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 001003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000004 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 001403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000010 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 002003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000020 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 002403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000040 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 003003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000100 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 003403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000200 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 100003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 000400 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 100403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 001000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 101003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 002000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 101403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 004000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 102003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 010000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 102403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 020000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 103003 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 040000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 103403 0 1 0 0 005030 000000 01
3 wmem 0 042704 0 1 0 0 005030 000000 01
3 wmem 0 100000 0 1 0 0 005030 000000 01
3 wmem 0 010312 0 1 0 0 005030 000000 01
3 wmem 0 010325 0 1 0 0 005030 000000 01
3 wmem 0 010425 0 1 0 0 005030 000000 01
3 wmem 0 000207 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 000002 0 1 0 0 005030 000000 01
3 wmem 0 000004 0 1 0 0 005030 000000 01
3 wmem 0 000010 0 1 0 0 005030 000000 01
3 wmem 0 177777 0 1 0 0 005030 000000 01
3 wmem 0 000000 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 000002 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 000002 0 1 0 0 005030 000000 01
3 wmem 0 000001 0 1 0 0 005030 000000 01
3 wmem 0 177777 0 1 0 0 005030 000000 01
3 wmem 0 000002 0 1 0 0 005030 000000 01
3 wmem 0 000002 0 1 0 0 005030 000000 01
3 wmem 0 177777 0 1 0 0 005030 000000 01
3 wmem 0 100000 0 1 0 0 005030 000000 01
3 wmem 0 077777 0 1 0 0 005030 000000 01
3 wmem 0 077777 0 1 0 0 005030 000000 01
3 wmem 0 100000 0 1 0 0 005030 000000 01
C Exec code 23 (test cmp and conditional branch)
C Exec test 23.1 (explict cc setting)
2 wreg 0 006200 0 1 0 0 006200 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 5 006300 0 1 0 0 006300 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 005030 000000 00
2 wreg 7 005700 0 1 0 0 005700 000000 00
2 sta 0 000000 0 1 0 0 005030 100000 07
964 ---- - ------ 0 0 0 0 005030 000000 01 WAIT GO OK
3 rreg 0 006212 0 1 0 0 006212 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 5 006324 0 1 0 0 006324 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 005712 0 1 0 0 005712 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 052524 0 1 0 0 052524 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 114524 0 1 0 0 114524 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 062644 0 1 0 0 062644 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 054630 0 1 0 0 054630 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 053244 0 1 0 0 053244 000000 01 CHECK OK
C Exec test 23.2 (tst testing)
2 wreg 0 006220 0 1 0 0 006220 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 5 006330 0 1 0 0 006330 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 005712 000000 00
2 wreg 7 005720 0 1 0 0 005720 000000 00
2 sta 0 000000 0 1 0 0 005712 100000 07
572 ---- - ------ 0 0 0 0 005712 000000 01 WAIT GO OK
3 rreg 0 006226 0 1 0 0 006226 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 5 006344 0 1 0 0 006344 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 005734 0 1 0 0 005734 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 053244 0 1 0 0 053244 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 054630 0 1 0 0 054630 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 052524 0 1 0 0 052524 000000 01 CHECK OK
C Exec test 23.3 (cmp testing)
2 wreg 0 006230 0 1 0 0 006230 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 5 006344 0 1 0 0 006344 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 005734 000000 00
2 wreg 7 005740 0 1 0 0 005740 000000 00
2 sta 0 000000 0 1 0 0 005734 100000 07
1338 ---- - ------ 0 0 0 0 005734 000000 01 WAIT GO OK
3 rreg 0 006264 0 1 0 0 006264 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 5 006400 0 1 0 0 006400 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 005754 0 1 0 0 005754 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 115244 0 1 0 0 115244 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 054630 0 1 0 0 054630 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 052524 0 1 0 0 052524 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 053244 0 1 0 0 053244 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 114524 0 1 0 0 114524 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 062644 0 1 0 0 062644 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 125124 0 1 0 0 125124 000000 01 CHECK OK
C Setup code 24 [base 6400] (test MARK instruction)
3 wmem 0 010546 0 1 0 0 005754 000000 01
3 wmem 0 012746 0 1 0 0 005754 000000 01
3 wmem 0 000101 0 1 0 0 005754 000000 01
3 wmem 0 012746 0 1 0 0 005754 000000 01
3 wmem 0 000102 0 1 0 0 005754 000000 01
3 wmem 0 012746 0 1 0 0 005754 000000 01
3 wmem 0 000103 0 1 0 0 005754 000000 01
3 wmem 0 012746 0 1 0 0 005754 000000 01
3 wmem 0 006403 0 1 0 0 005754 000000 01
3 wmem 0 010605 0 1 0 0 005754 000000 01
3 wmem 0 004737 0 1 0 0 005754 000000 01
3 wmem 0 006440 0 1 0 0 005754 000000 01
3 wmem 0 000000 0 1 0 0 005754 000000 01
3 wmem 0 016520 0 1 0 0 005754 000000 01
3 wmem 0 000006 0 1 0 0 005754 000000 01
3 wmem 0 016520 0 1 0 0 005754 000000 01
3 wmem 0 000004 0 1 0 0 005754 000000 01
3 wmem 0 016520 0 1 0 0 005754 000000 01
3 wmem 0 000002 0 1 0 0 005754 000000 01
3 wmem 0 000205 0 1 0 0 005754 000000 01
C Exec code 24 (test MARK instruction)
2 wreg 0 006470 0 1 0 0 006470 000000 01
2 wreg 5 123456 0 1 0 0 123456 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 005754 000000 00
2 wreg 7 006400 0 1 0 0 006400 000000 00
2 sta 0 000000 0 1 0 0 005754 100000 07
95 ---- - ------ 0 0 0 0 005754 000000 01 WAIT GO OK
3 rreg 0 006476 0 1 0 0 006476 000000 01 CHECK OK
3 rreg 5 123456 0 1 0 0 123456 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 006432 0 1 0 0 006432 000000 01 CHECK OK
3 rmem 0 006430 0 1 0 0 006430 000000 01 CHECK OK
3 rmem 0 006403 0 1 0 0 006403 000000 01 CHECK OK
3 rmem 0 000103 0 1 0 0 000103 000000 01 CHECK OK
3 rmem 0 000102 0 1 0 0 000102 000000 01 CHECK OK
3 rmem 0 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 01 CHECK OK
3 rmem 0 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rmem 0 000102 0 1 0 0 000102 000000 01 CHECK OK
3 rmem 0 000103 0 1 0 0 000103 000000 01 CHECK OK
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test)
3 wmem 0 110124 0 1 0 0 006432 000000 01
3 wmem 0 120124 0 1 0 0 006432 000000 01
3 wmem 0 120224 0 1 0 0 006432 000000 01
3 wmem 0 120124 0 1 0 0 006432 000000 01
3 wmem 0 105024 0 1 0 0 006432 000000 01
3 wmem 0 130124 0 1 0 0 006432 000000 01
3 wmem 0 130124 0 1 0 0 006432 000000 01
3 wmem 0 140124 0 1 0 0 006432 000000 01
3 wmem 0 150124 0 1 0 0 006432 000000 01
3 wmem 0 105124 0 1 0 0 006432 000000 01
3 wmem 0 105224 0 1 0 0 006432 000000 01
3 wmem 0 105324 0 1 0 0 006432 000000 01
3 wmem 0 105424 0 1 0 0 006432 000000 01
3 wmem 0 105724 0 1 0 0 006432 000000 01
3 wmem 0 106024 0 1 0 0 006432 000000 01
3 wmem 0 106024 0 1 0 0 006432 000000 01
3 wmem 0 106124 0 1 0 0 006432 000000 01
3 wmem 0 106224 0 1 0 0 006432 000000 01
3 wmem 0 106224 0 1 0 0 006432 000000 01
3 wmem 0 106324 0 1 0 0 006432 000000 01
3 wmem 0 106324 0 1 0 0 006432 000000 01
3 wmem 0 000000 0 1 0 0 006432 000000 01
3 wmem 0 006560 0 1 0 0 006432 000000 01
3 wmem 0 000000 0 1 0 0 006432 000000 01
3 wmem 0 016625 0 1 0 0 006432 000000 01
3 wmem 0 000002 0 1 0 0 006432 000000 01
3 wmem 0 000006 0 1 0 0 006432 000000 01
3 wmem 0 155733 0 1 0 0 006432 000000 01
3 wmem 0 051511 0 1 0 0 006432 000000 01
3 wmem 0 044333 0 1 0 0 006432 000000 01
3 wmem 0 155444 0 1 0 0 006432 000000 01
3 wmem 0 150511 0 1 0 0 006432 000000 01
3 wmem 0 150721 0 1 0 0 006432 000000 01
3 wmem 0 150721 0 1 0 0 006432 000000 01
3 wmem 0 010601 0 1 0 0 006432 000000 01
3 wmem 0 010210 0 1 0 0 006432 000000 01
3 wmem 0 010220 0 1 0 0 006432 000000 01
3 wmem 0 000220 0 1 0 0 006432 000000 01
C Exec code 25 (basic byte instruction and cc test)
2 wreg 1 000123 0 1 0 0 000123 000000 01
2 wreg 2 000321 0 1 0 0 000321 000000 01
2 wreg 4 006600 0 1 0 0 006600 000000 01
2 wreg 5 006626 0 1 0 0 006626 000000 01
2 wreg 6 001374 0 1 0 0 001374 000000 01
3 wmem 0 006500 0 1 0 0 006432 000000 01
3 wmem 0 000020 0 1 0 0 006432 000000 01
2 cres 0 000000 0 1 0 0 006432 000000 00
2 wreg 7 006564 0 1 0 0 006564 000000 00
2 sta 0 000000 0 1 0 0 006432 100000 07
738 ---- - ------ 0 0 0 0 006432 000000 01 WAIT GO OK
3 rreg 1 000123 0 1 0 0 000123 000000 01 CHECK OK
3 rreg 2 000321 0 1 0 0 000321 000000 01 CHECK OK
3 rreg 4 006625 0 1 0 0 006625 000000 01 CHECK OK
3 rreg 5 006700 0 1 0 0 006700 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 006554 0 1 0 0 006554 000000 01 CHECK OK
3 rmem 0 155523 0 1 0 0 155523 000000 01 CHECK OK
3 rmem 0 051511 0 1 0 0 051511 000000 01 CHECK OK
3 rmem 0 044000 0 1 0 0 044000 000000 01 CHECK OK
3 rmem 0 104044 0 1 0 0 104044 000000 01 CHECK OK
3 rmem 0 027133 0 1 0 0 027133 000000 01 CHECK OK
3 rmem 0 150322 0 1 0 0 150322 000000 01 CHECK OK
3 rmem 0 150457 0 1 0 0 150457 000000 01 CHECK OK
3 rmem 0 104100 0 1 0 0 104100 000000 01 CHECK OK
3 rmem 0 004021 0 1 0 0 004021 000000 01 CHECK OK
3 rmem 0 020310 0 1 0 0 020310 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000024 0 1 0 0 000024 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000030 0 1 0 0 000030 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000031 0 1 0 0 000031 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000032 0 1 0 0 000032 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000016 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
C Setup code 26 [base 6700; use 67-70] (address modes torture tests)
3 wmem 0 012020 0 1 0 0 006554 000000 00
3 wmem 0 062020 0 1 0 0 006554 000000 00
3 wmem 0 014141 0 1 0 0 006554 000000 00
3 wmem 0 064141 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 016767 0 1 0 0 006554 000000 00
3 wmem 0 000014 0 1 0 0 006554 000000 00
3 wmem 0 000014 0 1 0 0 006554 000000 00
3 wmem 0 066767 0 1 0 0 006554 000000 00
3 wmem 0 000012 0 1 0 0 006554 000000 00
3 wmem 0 000012 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 006740 0 1 0 0 006554 000000 00
3 wmem 0 006742 0 1 0 0 006554 000000 00
3 wmem 0 000011 0 1 0 0 006554 000000 00
3 wmem 0 006746 0 1 0 0 006554 000000 00
3 wmem 0 012727 0 1 0 0 006554 000000 00
3 wmem 0 000001 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 062727 0 1 0 0 006554 000000 00
3 wmem 0 000001 0 1 0 0 006554 000000 00
3 wmem 0 000002 0 1 0 0 006554 000000 00
3 wmem 0 016767 0 1 0 0 006554 000000 00
3 wmem 0 177764 0 1 0 0 006554 000000 00
3 wmem 0 000002 0 1 0 0 006554 000000 00
3 wmem 0 062700 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 005200 0 1 0 0 006554 000000 00
3 wmem 0 010001 0 1 0 0 006554 000000 00
3 wmem 0 010702 0 1 0 0 006554 000000 00
3 wmem 0 005007 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 005203 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000137 0 1 0 0 006554 000000 00
3 wmem 0 007014 0 1 0 0 006554 000000 00
3 wmem 0 012707 0 1 0 0 006554 000000 00
3 wmem 0 007032 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 062707 0 1 0 0 006554 000000 00
3 wmem 0 000002 0 1 0 0 006554 000000 00
3 wmem 0 005201 0 1 0 0 006554 000000 00
3 wmem 0 005201 0 1 0 0 006554 000000 00
3 wmem 0 005201 0 1 0 0 006554 000000 00
3 wmem 0 000000 0 1 0 0 006554 000000 00
3 wmem 0 000111 0 1 0 0 006554 000000 00
3 wmem 0 000222 0 1 0 0 006554 000000 00
3 wmem 0 000333 0 1 0 0 006554 000000 00
3 wmem 0 000444 0 1 0 0 006554 000000 00
3 wmem 0 000111 0 1 0 0 006554 000000 00
3 wmem 0 000222 0 1 0 0 006554 000000 00
3 wmem 0 000333 0 1 0 0 006554 000000 00
3 wmem 0 000444 0 1 0 0 006554 000000 00
C Exec code 26 (address modes torture tests)
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect):
2 wreg 0 007060 0 1 0 0 007060 000000 00
2 wreg 1 007100 0 1 0 0 007100 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 cres 0 000000 0 1 0 0 006554 000000 00
2 wreg 7 006700 0 1 0 0 006700 000000 00
2 sta 0 000000 0 1 0 0 006554 100000 07
41 ---- - ------ 0 0 0 0 006554 000000 01 WAIT GO OK
3 rreg 0 007070 0 1 0 0 007070 000000 01 CHECK OK
3 rreg 1 007070 0 1 0 0 007070 000000 01 CHECK OK
3 rreg 7 006712 0 1 0 0 006712 000000 01 CHECK OK
3 rmem 0 000111 0 1 0 0 000111 000000 01 CHECK OK
3 rmem 0 000111 0 1 0 0 000111 000000 01 CHECK OK
3 rmem 0 000333 0 1 0 0 000333 000000 01 CHECK OK
3 rmem 0 000777 0 1 0 0 000777 000000 01 CHECK OK
3 rmem 0 000333 0 1 0 0 000333 000000 01 CHECK OK
3 rmem 0 000222 0 1 0 0 000222 000000 01 CHECK OK
3 rmem 0 000444 0 1 0 0 000444 000000 01 CHECK OK
3 rmem 0 000444 0 1 0 0 000444 000000 01 CHECK OK
C Exec test 26.2 (test indexed mode with pc (mode 67)):
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 006712 000000 00
2 wreg 7 006720 0 1 0 0 006720 000000 00
2 sta 0 000000 0 1 0 0 006712 100000 07
29 ---- - ------ 0 0 0 0 006712 000000 01 WAIT GO OK
3 rreg 7 006736 0 1 0 0 006736 000000 01 CHECK OK
3 rmem 0 006740 0 1 0 0 006740 000000 01 CHECK OK
3 rmem 0 006740 0 1 0 0 006740 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 006757 0 1 0 0 006757 000000 01 CHECK OK
C Exec test 26.3 (test (pc)+ as dst):
2 wreg 0 000111 0 1 0 0 000111 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 006736 000000 00
2 wreg 7 006750 0 1 0 0 006750 000000 00
2 sta 0 000000 0 1 0 0 006736 100000 07
37 ---- - ------ 0 0 0 0 006736 000000 01 WAIT GO OK
3 rreg 0 000112 0 1 0 0 000112 000000 01 CHECK OK
3 rreg 7 007000 0 1 0 0 007000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 26.4 (test pc as dst in clr):
2 wreg 0 000100 0 1 0 0 000100 000000 01
2 wreg 1 000110 0 1 0 0 000110 000000 01
2 wreg 2 000120 0 1 0 0 000120 000000 01
2 wreg 3 000130 0 1 0 0 000130 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007000 000000 00
2 wreg 7 007000 0 1 0 0 007000 000000 00
2 sta 0 000000 0 1 0 0 007000 100000 07
24 ---- - ------ 0 0 0 0 007000 000000 01 WAIT GO OK
3 rreg 0 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rreg 1 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rreg 2 007006 0 1 0 0 007006 000000 01 CHECK OK
3 rreg 3 000131 0 1 0 0 000131 000000 01 CHECK OK
3 rreg 7 007020 0 1 0 0 007020 000000 01 CHECK OK
3 wmem 0 000000 0 1 0 0 007020 000000 01
3 wmem 0 000000 0 1 0 0 007020 000000 01
C Exec test 26.5 (test pc as dst in mov and add):
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007020 000000 00
2 wreg 7 007020 0 1 0 0 007020 000000 00
2 sta 0 000000 0 1 0 0 007020 100000 07
23 ---- - ------ 0 0 0 0 007020 000000 01 WAIT GO OK
3 rreg 1 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rreg 7 007046 0 1 0 0 007046 000000 01 CHECK OK
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction)
3 wmem 0 000230 0 1 0 0 007046 000000 01
3 wmem 0 012004 0 1 0 0 007046 000000 01
3 wmem 0 072420 0 1 0 0 007046 000000 01
3 wmem 0 011321 0 1 0 0 007046 000000 01
3 wmem 0 010421 0 1 0 0 007046 000000 01
3 wmem 0 077205 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000230 0 1 0 0 007046 000000 01
3 wmem 0 012004 0 1 0 0 007046 000000 01
3 wmem 0 012005 0 1 0 0 007046 000000 01
3 wmem 0 073420 0 1 0 0 007046 000000 01
3 wmem 0 011321 0 1 0 0 007046 000000 01
3 wmem 0 010421 0 1 0 0 007046 000000 01
3 wmem 0 010521 0 1 0 0 007046 000000 01
3 wmem 0 077207 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000230 0 1 0 0 007046 000000 01
3 wmem 0 012005 0 1 0 0 007046 000000 01
3 wmem 0 073520 0 1 0 0 007046 000000 01
3 wmem 0 011321 0 1 0 0 007046 000000 01
3 wmem 0 010521 0 1 0 0 007046 000000 01
3 wmem 0 077205 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000001 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177777 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000007 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000010 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000011 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177771 0 1 0 0 007046 000000 01
3 wmem 0 100000 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177770 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 100000 0 1 0 0 007046 000000 01
3 wmem 0 177772 0 1 0 0 007046 000000 01
3 wmem 0 040000 0 1 0 0 007046 000000 01
3 wmem 0 000001 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000001 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177777 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000007 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000010 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000011 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000027 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000030 0 1 0 0 007046 000000 01
3 wmem 0 000000 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000031 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177773 0 1 0 0 007046 000000 01
3 wmem 0 000020 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177770 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 000001 0 1 0 0 007046 000000 01
3 wmem 0 000200 0 1 0 0 007046 000000 01
3 wmem 0 177777 0 1 0 0 007046 000000 01
3 wmem 0 000201 0 1 0 0 007046 000000 01
3 wmem 0 177777 0 1 0 0 007046 000000 01
C Exec code 27 (test ASH/ASHC instruction)
C Exec test 27.1 (test ash)
2 wreg 0 007200 0 1 0 0 007200 000000 01
2 wreg 1 007500 0 1 0 0 007500 000000 01
2 wreg 2 000014 0 1 0 0 000014 000000 01
2 wreg 3 177776 0 1 0 0 177776 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007046 000000 00
2 wreg 7 007100 0 1 0 0 007100 000000 00
2 sta 0 000000 0 1 0 0 007046 100000 07
416 ---- - ------ 0 0 0 0 007046 000000 01 WAIT GO OK
3 rreg 0 007260 0 1 0 0 007260 000000 01 CHECK OK
3 rreg 1 007560 0 1 0 0 007560 000000 01 CHECK OK
3 rreg 7 007116 0 1 0 0 007116 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177000 0 1 0 0 177000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
C Exec test 27.2 (test ashc even)
2 wreg 0 007300 0 1 0 0 007300 000000 01
2 wreg 1 007600 0 1 0 0 007600 000000 01
2 wreg 2 000012 0 1 0 0 000012 000000 01
2 wreg 3 177776 0 1 0 0 177776 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007116 000000 00
2 wreg 7 007120 0 1 0 0 007120 000000 00
2 sta 0 000000 0 1 0 0 007116 100000 07
539 ---- - ------ 0 0 0 0 007116 000000 01 WAIT GO OK
3 rreg 0 007374 0 1 0 0 007374 000000 01 CHECK OK
3 rreg 1 007674 0 1 0 0 007674 000000 01 CHECK OK
3 rreg 7 007142 0 1 0 0 007142 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 004000 0 1 0 0 004000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 010000 0 1 0 0 010000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020001 0 1 0 0 020001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100004 0 1 0 0 100004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 010000 0 1 0 0 010000 000000 01 CHECK OK
C Exec test 27.3 (test ashc odd)
2 wreg 0 007440 0 1 0 0 007440 000000 01
2 wreg 1 007740 0 1 0 0 007740 000000 01
2 wreg 2 000003 0 1 0 0 000003 000000 01
2 wreg 3 177776 0 1 0 0 177776 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007142 000000 00
2 wreg 7 007150 0 1 0 0 007150 000000 00
2 sta 0 000000 0 1 0 0 007142 100000 07
107 ---- - ------ 0 0 0 0 007142 000000 01 WAIT GO OK
3 rreg 0 007454 0 1 0 0 007454 000000 01 CHECK OK
3 rreg 1 007754 0 1 0 0 007754 000000 01 CHECK OK
3 rreg 7 007166 0 1 0 0 007166 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 100100 0 1 0 0 100100 000000 01 CHECK OK
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
3 wmem 0 000230 0 1 0 0 007166 000000 01
3 wmem 0 012004 0 1 0 0 007166 000000 01
3 wmem 0 070420 0 1 0 0 007166 000000 01
3 wmem 0 011321 0 1 0 0 007166 000000 01
3 wmem 0 010421 0 1 0 0 007166 000000 01
3 wmem 0 010521 0 1 0 0 007166 000000 01
3 wmem 0 077206 0 1 0 0 007166 000000 01
3 wmem 0 000000 0 1 0 0 007166 000000 01
3 wmem 0 000230 0 1 0 0 007166 000000 01
3 wmem 0 012005 0 1 0 0 007166 000000 01
3 wmem 0 070520 0 1 0 0 007166 000000 01
3 wmem 0 010521 0 1 0 0 007166 000000 01
3 wmem 0 060403 0 1 0 0 007166 000000 01
3 wmem 0 077205 0 1 0 0 007166 000000 01
3 wmem 0 000000 0 1 0 0 007166 000000 01
3 wmem 0 074456 0 1 0 0 007166 000000 01
3 wmem 0 022532 0 1 0 0 007166 000000 01
3 wmem 0 044076 0 1 0 0 007166 000000 01
3 wmem 0 121027 0 1 0 0 007166 000000 01
3 wmem 0 147373 0 1 0 0 007166 000000 01
3 wmem 0 004535 0 1 0 0 007166 000000 01
3 wmem 0 127763 0 1 0 0 007166 000000 01
3 wmem 0 121316 0 1 0 0 007166 000000 01
3 wmem 0 000151 0 1 0 0 007166 000000 01
3 wmem 0 000306 0 1 0 0 007166 000000 01
3 wmem 0 000351 0 1 0 0 007166 000000 01
3 wmem 0 177642 0 1 0 0 007166 000000 01
3 wmem 0 000272 0 1 0 0 007166 000000 01
3 wmem 0 177463 0 1 0 0 007166 000000 01
3 wmem 0 000000 0 1 0 0 007166 000000 01
3 wmem 0 000272 0 1 0 0 007166 000000 01
C Exec code 30 (test MUL instruction)
C Exec test 30.1 (test mul even)
2 wreg 0 010240 0 1 0 0 010240 000000 01
2 wreg 1 010300 0 1 0 0 010300 000000 01
2 wreg 2 000010 0 1 0 0 000010 000000 01
2 wreg 3 177776 0 1 0 0 177776 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 007166 000000 00
2 wreg 7 010200 0 1 0 0 010200 000000 00
2 sta 0 000000 0 1 0 0 007166 100000 07
296 ---- - ------ 0 0 0 0 007166 000000 01 WAIT GO OK
3 rreg 0 010300 0 1 0 0 010300 000000 01 CHECK OK
3 rreg 1 010360 0 1 0 0 010360 000000 01 CHECK OK
3 rreg 7 010220 0 1 0 0 010220 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 010656 0 1 0 0 010656 000000 01 CHECK OK
3 rmem 0 040054 0 1 0 0 040054 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 162577 0 1 0 0 162577 000000 01 CHECK OK
3 rmem 0 134622 0 1 0 0 134622 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177065 0 1 0 0 177065 000000 01 CHECK OK
3 rmem 0 002057 0 1 0 0 002057 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 016444 0 1 0 0 016444 000000 01 CHECK OK
3 rmem 0 055612 0 1 0 0 055612 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 050466 0 1 0 0 050466 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 125162 0 1 0 0 125162 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 065416 0 1 0 0 065416 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 30.2 (test mul odd)
2 wreg 0 010240 0 1 0 0 010240 000000 01
2 wreg 1 010360 0 1 0 0 010360 000000 01
2 wreg 2 000010 0 1 0 0 000010 000000 01
2 wreg 3 000000 0 1 0 0 000000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 010220 000000 00
2 wreg 7 010220 0 1 0 0 010220 000000 00
2 sta 0 000000 0 1 0 0 010220 100000 07
200 ---- - ------ 0 0 0 0 010220 000000 01 WAIT GO OK
3 rreg 0 010300 0 1 0 0 010300 000000 01 CHECK OK
3 rreg 1 010400 0 1 0 0 010400 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 7 010236 0 1 0 0 010236 000000 01 CHECK OK
3 rmem 0 040054 0 1 0 0 040054 000000 01 CHECK OK
3 rmem 0 134622 0 1 0 0 134622 000000 01 CHECK OK
3 rmem 0 002057 0 1 0 0 002057 000000 01 CHECK OK
3 rmem 0 055612 0 1 0 0 055612 000000 01 CHECK OK
3 rmem 0 050466 0 1 0 0 050466 000000 01 CHECK OK
3 rmem 0 125162 0 1 0 0 125162 000000 01 CHECK OK
3 rmem 0 065416 0 1 0 0 065416 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
3 wmem 0 012004 0 1 0 0 010236 000000 01
3 wmem 0 012005 0 1 0 0 010236 000000 01
3 wmem 0 071420 0 1 0 0 010236 000000 01
3 wmem 0 011321 0 1 0 0 010236 000000 01
3 wmem 0 010421 0 1 0 0 010236 000000 01
3 wmem 0 010521 0 1 0 0 010236 000000 01
3 wmem 0 077207 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 012146 0 1 0 0 010236 000000 01
3 wmem 0 016002 0 1 0 0 010236 000000 01
3 wmem 0 000004 0 1 0 0 010236 000000 01
3 wmem 0 070221 0 1 0 0 010236 000000 01
3 wmem 0 061103 0 1 0 0 010236 000000 01
3 wmem 0 005502 0 1 0 0 010236 000000 01
3 wmem 0 005721 0 1 0 0 010236 000000 01
3 wmem 0 006704 0 1 0 0 010236 000000 01
3 wmem 0 060402 0 1 0 0 010236 000000 01
3 wmem 0 166003 0 1 0 0 010236 000000 01
3 wmem 0 000002 0 1 0 0 010236 000000 01
3 wmem 0 005602 0 1 0 0 010236 000000 01
3 wmem 0 161002 0 1 0 0 010236 000000 01
3 wmem 0 001002 0 1 0 0 010236 000000 01
3 wmem 0 005703 0 1 0 0 010236 000000 01
3 wmem 0 001404 0 1 0 0 010236 000000 01
3 wmem 0 032726 0 1 0 0 010236 000000 01
3 wmem 0 000003 0 1 0 0 010236 000000 01
3 wmem 0 001001 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 062700 0 1 0 0 010236 000000 01
3 wmem 0 000006 0 1 0 0 010236 000000 01
3 wmem 0 077527 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 000042 0 1 0 0 010236 000000 01
3 wmem 0 000005 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 000042 0 1 0 0 010236 000000 01
3 wmem 0 177773 0 1 0 0 010236 000000 01
3 wmem 0 177777 0 1 0 0 010236 000000 01
3 wmem 0 177736 0 1 0 0 010236 000000 01
3 wmem 0 000005 0 1 0 0 010236 000000 01
3 wmem 0 177777 0 1 0 0 010236 000000 01
3 wmem 0 177736 0 1 0 0 010236 000000 01
3 wmem 0 177773 0 1 0 0 010236 000000 01
3 wmem 0 001551 0 1 0 0 010236 000000 01
3 wmem 0 047663 0 1 0 0 010236 000000 01
3 wmem 0 014151 0 1 0 0 010236 000000 01
3 wmem 0 174241 0 1 0 0 010236 000000 01
3 wmem 0 021264 0 1 0 0 010236 000000 01
3 wmem 0 012112 0 1 0 0 010236 000000 01
3 wmem 0 157705 0 1 0 0 010236 000000 01
3 wmem 0 064403 0 1 0 0 010236 000000 01
3 wmem 0 131031 0 1 0 0 010236 000000 01
3 wmem 0 016444 0 1 0 0 010236 000000 01
3 wmem 0 102602 0 1 0 0 010236 000000 01
3 wmem 0 127763 0 1 0 0 010236 000000 01
3 wmem 0 177064 0 1 0 0 010236 000000 01
3 wmem 0 154174 0 1 0 0 010236 000000 01
3 wmem 0 147373 0 1 0 0 010236 000000 01
3 wmem 0 171577 0 1 0 0 010236 000000 01
3 wmem 0 067035 0 1 0 0 010236 000000 01
3 wmem 0 054134 0 1 0 0 010236 000000 01
3 wmem 0 002421 0 1 0 0 010236 000000 01
3 wmem 0 150761 0 1 0 0 010236 000000 01
3 wmem 0 024743 0 1 0 0 010236 000000 01
3 wmem 0 001520 0 1 0 0 010236 000000 01
3 wmem 0 142467 0 1 0 0 010236 000000 01
3 wmem 0 171044 0 1 0 0 010236 000000 01
3 wmem 0 001520 0 1 0 0 010236 000000 01
3 wmem 0 142467 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 021706 0 1 0 0 010236 000000 01
3 wmem 0 177777 0 1 0 0 010236 000000 01
3 wmem 0 100000 0 1 0 0 010236 000000 01
3 wmem 0 000001 0 1 0 0 010236 000000 01
3 wmem 0 177777 0 1 0 0 010236 000000 01
3 wmem 0 100000 0 1 0 0 010236 000000 01
3 wmem 0 177777 0 1 0 0 010236 000000 01
3 wmem 0 037777 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
3 wmem 0 037777 0 1 0 0 010236 000000 01
3 wmem 0 100000 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
3 wmem 0 140000 0 1 0 0 010236 000000 01
3 wmem 0 100001 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
3 wmem 0 140000 0 1 0 0 010236 000000 01
3 wmem 0 100000 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
3 wmem 0 040000 0 1 0 0 010236 000000 01
3 wmem 0 000000 0 1 0 0 010236 000000 01
3 wmem 0 077777 0 1 0 0 010236 000000 01
C Exec code 31 (test DIV instruction, also ADC,SXT)
C Exec test 31.1 (test div)
2 wreg 0 010500 0 1 0 0 010500 000000 01
2 wreg 1 010700 0 1 0 0 010700 000000 01
2 wreg 2 000025 0 1 0 0 000025 000000 01
2 wreg 3 177776 0 1 0 0 177776 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 010236 000000 00
2 wpsw 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 010400 0 1 0 0 010400 000000 00
2 sta 0 000000 0 1 0 0 010236 100000 07
1158 ---- - ------ 0 0 0 0 010236 000000 01 WAIT GO OK
3 rreg 0 010676 0 1 0 0 010676 000000 01 CHECK OK
3 rreg 1 011076 0 1 0 0 011076 000000 01 CHECK OK
3 rreg 7 010420 0 1 0 0 010420 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177772 0 1 0 0 177772 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177772 0 1 0 0 177772 000000 01 CHECK OK
3 rmem 0 177774 0 1 0 0 177774 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 177774 0 1 0 0 177774 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 021706 0 1 0 0 021706 000000 01 CHECK OK
3 rmem 0 011575 0 1 0 0 011575 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 121401 0 1 0 0 121401 000000 01 CHECK OK
3 rmem 0 170152 0 1 0 0 170152 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 064750 0 1 0 0 064750 000000 01 CHECK OK
3 rmem 0 140533 0 1 0 0 140533 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 121316 0 1 0 0 121316 000000 01 CHECK OK
3 rmem 0 024770 0 1 0 0 024770 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 004535 0 1 0 0 004535 000000 01 CHECK OK
3 rmem 0 152115 0 1 0 0 152115 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 155710 0 1 0 0 155710 000000 01 CHECK OK
3 rmem 0 131075 0 1 0 0 131075 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 017373 0 1 0 0 017373 000000 01 CHECK OK
3 rmem 0 023140 0 1 0 0 023140 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 141303 0 1 0 0 141303 000000 01 CHECK OK
3 rmem 0 005713 0 1 0 0 005713 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 001520 0 1 0 0 001520 000000 01 CHECK OK
3 rmem 0 142467 0 1 0 0 142467 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 037777 0 1 0 0 037777 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 100002 0 1 0 0 100002 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 31.2 (test mul after div)
2 wreg 0 010500 0 1 0 0 010500 000000 01
2 wreg 1 010700 0 1 0 0 010700 000000 01
2 wreg 5 000016 0 1 0 0 000016 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 010420 000000 00
2 wreg 7 010420 0 1 0 0 010420 000000 00
2 sta 0 000000 0 1 0 0 010420 100000 07
1004 ---- - ------ 0 0 0 0 010420 000000 01 WAIT GO OK
3 rreg 0 010624 0 1 0 0 010624 000000 01 CHECK OK
3 rreg 1 011024 0 1 0 0 011024 000000 01 CHECK OK
3 rreg 2 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 5 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 7 010500 0 1 0 0 010500 000000 01 CHECK OK
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
3 wmem 0 000237 0 1 0 0 010500 000000 01
3 wmem 0 011425 0 1 0 0 010500 000000 01
3 wmem 0 012713 0 1 0 0 010500 000000 01
3 wmem 0 001000 0 1 0 0 010500 000000 01
3 wmem 0 011325 0 1 0 0 010500 000000 01
3 wmem 0 112763 0 1 0 0 010500 000000 01
3 wmem 0 000012 0 1 0 0 010500 000000 01
3 wmem 0 000001 0 1 0 0 010500 000000 01
3 wmem 0 011325 0 1 0 0 010500 000000 01
3 wmem 0 000232 0 1 0 0 010500 000000 01
3 wmem 0 000240 0 1 0 0 010500 000000 01
3 wmem 0 000230 0 1 0 0 010500 000000 01
3 wmem 0 000240 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 011134 0 1 0 0 010500 000000 01
3 wmem 0 000340 0 1 0 0 010500 000000 01
3 wmem 0 011300 0 1 0 0 010500 000000 01
3 wmem 0 010625 0 1 0 0 010500 000000 01
3 wmem 0 010025 0 1 0 0 010500 000000 01
3 wmem 0 110014 0 1 0 0 010500 000000 01
3 wmem 0 042700 0 1 0 0 010500 000000 01
3 wmem 0 177761 0 1 0 0 010500 000000 01
3 wmem 0 010001 0 1 0 0 010500 000000 01
3 wmem 0 006201 0 1 0 0 010500 000000 01
3 wmem 0 012702 0 1 0 0 010500 000000 01
3 wmem 0 000400 0 1 0 0 010500 000000 01
3 wmem 0 072201 0 1 0 0 010500 000000 01
3 wmem 0 040213 0 1 0 0 010500 000000 01
3 wmem 0 010246 0 1 0 0 010500 000000 01
3 wmem 0 056013 0 1 0 0 010500 000000 01
3 wmem 0 011200 0 1 0 0 010500 000000 01
3 wmem 0 000240 0 1 0 0 010500 000000 01
3 wmem 0 012625 0 1 0 0 010500 000000 01
3 wmem 0 000002 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 100000 0 1 0 0 010500 000000 01
3 wmem 0 022000 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 000000 0 1 0 0 010500 000000 01
3 wmem 0 050000 0 1 0 0 010500 000000 01
C Exec code 32 (PIRQ test)
2 wreg 3 177772 0 1 0 0 177772 000000 01
2 wreg 4 177776 0 1 0 0 177776 000000 01
2 wreg 5 011220 0 1 0 0 011220 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 010500 000000 00
2 wreg 7 011100 0 1 0 0 011100 000000 00
2 sta 0 000000 0 1 0 0 010500 100000 07
821 ---- - ------ 0 0 0 0 010500 000000 01 WAIT GO OK
3 rreg 5 011300 0 1 0 0 011300 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rreg 7 011134 0 1 0 0 011134 000000 01 CHECK OK
3 rpsw 0 000000 0 1 0 0 000000 000000 01 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000340 0 1 0 0 000340 000000 01 CHECK OK
3 rmem 0 001042 0 1 0 0 001042 000000 01 CHECK OK
3 rmem 0 005146 0 1 0 0 005146 000000 01 CHECK OK
3 rmem 0 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 005146 0 1 0 0 005146 000000 01 CHECK OK
3 rmem 0 001366 0 1 0 0 001366 000000 01 CHECK OK
3 rmem 0 101356 0 1 0 0 101356 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 001366 0 1 0 0 001366 000000 01 CHECK OK
3 rmem 0 051314 0 1 0 0 051314 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 001366 0 1 0 0 001366 000000 01 CHECK OK
3 rmem 0 011210 0 1 0 0 011210 000000 01 CHECK OK
3 rmem 0 001360 0 1 0 0 001360 000000 01 CHECK OK
3 rmem 0 023252 0 1 0 0 023252 000000 01 CHECK OK
3 rmem 0 020000 0 1 0 0 020000 000000 01 CHECK OK
3 rmem 0 010000 0 1 0 0 010000 000000 01 CHECK OK
3 rmem 0 004000 0 1 0 0 004000 000000 01 CHECK OK
3 rmem 0 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 003104 0 1 0 0 003104 000000 01 CHECK OK
3 rmem 0 002000 0 1 0 0 002000 000000 01 CHECK OK
3 rmem 0 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 001042 0 1 0 0 001042 000000 01 CHECK OK
3 rmem 0 001000 0 1 0 0 001000 000000 01 CHECK OK
3 wmem 0 000242 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
3 wmem 0 006020 0 1 0 0 011134 000000 01
3 wmem 0 005520 0 1 0 0 011134 000000 01
3 wmem 0 006120 0 1 0 0 011134 000000 01
3 wmem 0 077104 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 006020 0 1 0 0 011134 000000 01
3 wmem 0 005620 0 1 0 0 011134 000000 01
3 wmem 0 006120 0 1 0 0 011134 000000 01
3 wmem 0 077104 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 006020 0 1 0 0 011134 000000 01
3 wmem 0 105520 0 1 0 0 011134 000000 01
3 wmem 0 106120 0 1 0 0 011134 000000 01
3 wmem 0 077104 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 006020 0 1 0 0 011134 000000 01
3 wmem 0 105620 0 1 0 0 011134 000000 01
3 wmem 0 106120 0 1 0 0 011134 000000 01
3 wmem 0 077104 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 177776 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 177776 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 177777 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000002 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000002 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000376 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000376 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000377 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
3 wmem 0 000002 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000002 0 1 0 0 011134 000000 01
3 wmem 0 000001 0 1 0 0 011134 000000 01
3 wmem 0 000000 0 1 0 0 011134 000000 01
C Exec code 33 (adc and sbc test)
C Exec test 33.1 (adc)
2 wreg 0 011300 0 1 0 0 011300 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 011134 000000 00
2 wreg 7 011200 0 1 0 0 011200 000000 00
2 sta 0 000000 0 1 0 0 011134 100000 07
82 ---- - ------ 0 0 0 0 011134 000000 01 WAIT GO OK
3 rreg 0 011322 0 1 0 0 011322 000000 01 CHECK OK
3 rreg 7 011212 0 1 0 0 011212 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 33.2 (sbc)
2 wreg 0 011324 0 1 0 0 011324 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 011212 000000 00
2 wreg 7 011220 0 1 0 0 011220 000000 00
2 sta 0 000000 0 1 0 0 011212 100000 07
82 ---- - ------ 0 0 0 0 011212 000000 01 WAIT GO OK
3 rreg 0 011346 0 1 0 0 011346 000000 01 CHECK OK
3 rreg 7 011232 0 1 0 0 011232 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 33.3 (adcb)
2 wreg 0 011350 0 1 0 0 011350 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 011232 000000 00
2 wreg 7 011240 0 1 0 0 011240 000000 00
2 sta 0 000000 0 1 0 0 011232 100000 07
82 ---- - ------ 0 0 0 0 011232 000000 01 WAIT GO OK
3 rreg 0 011364 0 1 0 0 011364 000000 01 CHECK OK
3 rreg 7 011252 0 1 0 0 011252 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
C Exec test 33.4 (sbcb)
2 wreg 0 011364 0 1 0 0 011364 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 011252 000000 00
2 wreg 7 011260 0 1 0 0 011260 000000 00
2 sta 0 000000 0 1 0 0 011252 100000 07
82 ---- - ------ 0 0 0 0 011252 000000 01 WAIT GO OK
3 rreg 0 011400 0 1 0 0 011400 000000 01 CHECK OK
3 rreg 7 011272 0 1 0 0 011272 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000777 0 1 0 0 000777 000000 01 CHECK OK
C Setup code 34 [base 11400; use 114-115] (11/34 self test code)
3 wmem 0 005000 0 1 0 0 011272 000000 01
3 wmem 0 005200 0 1 0 0 011272 000000 01
3 wmem 0 005100 0 1 0 0 011272 000000 01
3 wmem 0 006200 0 1 0 0 011272 000000 01
3 wmem 0 006300 0 1 0 0 011272 000000 01
3 wmem 0 006000 0 1 0 0 011272 000000 01
3 wmem 0 005700 0 1 0 0 011272 000000 01
3 wmem 0 005400 0 1 0 0 011272 000000 01
3 wmem 0 005300 0 1 0 0 011272 000000 01
3 wmem 0 005600 0 1 0 0 011272 000000 01
3 wmem 0 006100 0 1 0 0 011272 000000 01
3 wmem 0 005500 0 1 0 0 011272 000000 01
3 wmem 0 000300 0 1 0 0 011272 000000 01
3 wmem 0 001401 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 012702 0 1 0 0 011272 000000 01
3 wmem 0 011560 0 1 0 0 011272 000000 01
3 wmem 0 011203 0 1 0 0 011272 000000 01
3 wmem 0 022203 0 1 0 0 011272 000000 01
3 wmem 0 001401 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 063203 0 1 0 0 011272 000000 01
3 wmem 0 165203 0 1 0 0 011272 000000 01
3 wmem 0 044203 0 1 0 0 011272 000000 01
3 wmem 0 056203 0 1 0 0 011272 000000 01
3 wmem 0 000012 0 1 0 0 011272 000000 01
3 wmem 0 037203 0 1 0 0 011272 000000 01
3 wmem 0 000012 0 1 0 0 011272 000000 01
3 wmem 0 001001 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 010701 0 1 0 0 011272 000000 01
3 wmem 0 000121 0 1 0 0 011272 000000 01
3 wmem 0 012701 0 1 0 0 011272 000000 01
3 wmem 0 011510 0 1 0 0 011272 000000 01
3 wmem 0 000131 0 1 0 0 011272 000000 01
3 wmem 0 000111 0 1 0 0 011272 000000 01
3 wmem 0 011506 0 1 0 0 011272 000000 01
3 wmem 0 105737 0 1 0 0 011272 000000 01
3 wmem 0 011564 0 1 0 0 011272 000000 01
3 wmem 0 001401 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 010204 0 1 0 0 011272 000000 01
3 wmem 0 022424 0 1 0 0 011272 000000 01
3 wmem 0 105724 0 1 0 0 011272 000000 01
3 wmem 0 001401 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 105714 0 1 0 0 011272 000000 01
3 wmem 0 100402 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 000000 0 1 0 0 011272 000000 01
3 wmem 0 011560 0 1 0 0 011272 000000 01
3 wmem 0 011560 0 1 0 0 011272 000000 01
3 wmem 0 100000 0 1 0 0 011272 000000 01
3 wmem 0 177777 0 1 0 0 011272 000000 01
3 wmem 0 011566 0 1 0 0 011272 000000 01
3 wmem 0 011566 0 1 0 0 011272 000000 01
3 wmem 0 000700 0 1 0 0 011272 000000 01
3 wmem 0 000701 0 1 0 0 011272 000000 01
C Exec code 34 (11/34 self test code)
2 cres 0 000000 0 1 0 0 011272 000000 00
2 wreg 7 011400 0 1 0 0 011400 000000 00
2 sta 0 000000 0 1 0 0 011272 100000 07
160 ---- - ------ 0 0 0 0 011272 000000 01 WAIT GO OK
3 rreg 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 1 011512 0 1 0 0 011512 000000 01 CHECK OK
3 rreg 2 011560 0 1 0 0 011560 000000 01 CHECK OK
3 rreg 3 011566 0 1 0 0 011566 000000 01 CHECK OK
3 rreg 4 011565 0 1 0 0 011565 000000 01 CHECK OK
3 rreg 7 011546 0 1 0 0 011546 000000 01 CHECK OK
C Setup code 35 [base 11600; use 116-121] (11/70 self test code)
3 wmem 0 005006 0 1 0 0 011546 000000 01
3 wmem 0 100404 0 1 0 0 011546 000000 01
3 wmem 0 102403 0 1 0 0 011546 000000 01
3 wmem 0 101002 0 1 0 0 011546 000000 01
3 wmem 0 002401 0 1 0 0 011546 000000 01
3 wmem 0 101401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 005306 0 1 0 0 011546 000000 01
3 wmem 0 100003 0 1 0 0 011546 000000 01
3 wmem 0 001402 0 1 0 0 011546 000000 01
3 wmem 0 002001 0 1 0 0 011546 000000 01
3 wmem 0 003401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 006006 0 1 0 0 011546 000000 01
3 wmem 0 102002 0 1 0 0 011546 000000 01
3 wmem 0 103001 0 1 0 0 011546 000000 01
3 wmem 0 001001 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 012706 0 1 0 0 011546 000000 01
3 wmem 0 125252 0 1 0 0 011546 000000 01
3 wmem 0 010600 0 1 0 0 011546 000000 01
3 wmem 0 010001 0 1 0 0 011546 000000 01
3 wmem 0 010102 0 1 0 0 011546 000000 01
3 wmem 0 010203 0 1 0 0 011546 000000 01
3 wmem 0 010304 0 1 0 0 011546 000000 01
3 wmem 0 010405 0 1 0 0 011546 000000 01
3 wmem 0 160501 0 1 0 0 011546 000000 01
3 wmem 0 002401 0 1 0 0 011546 000000 01
3 wmem 0 001401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 006102 0 1 0 0 011546 000000 01
3 wmem 0 103001 0 1 0 0 011546 000000 01
3 wmem 0 002401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 060203 0 1 0 0 011546 000000 01
3 wmem 0 005203 0 1 0 0 011546 000000 01
3 wmem 0 005103 0 1 0 0 011546 000000 01
3 wmem 0 060301 0 1 0 0 011546 000000 01
3 wmem 0 103401 0 1 0 0 011546 000000 01
3 wmem 0 003401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 006004 0 1 0 0 011546 000000 01
3 wmem 0 050403 0 1 0 0 011546 000000 01
3 wmem 0 060503 0 1 0 0 011546 000000 01
3 wmem 0 005203 0 1 0 0 011546 000000 01
3 wmem 0 103402 0 1 0 0 011546 000000 01
3 wmem 0 005301 0 1 0 0 011546 000000 01
3 wmem 0 002401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 005100 0 1 0 0 011546 000000 01
3 wmem 0 101401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 040001 0 1 0 0 011546 000000 01
3 wmem 0 060101 0 1 0 0 011546 000000 01
3 wmem 0 003001 0 1 0 0 011546 000000 01
3 wmem 0 003401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 000301 0 1 0 0 011546 000000 01
3 wmem 0 020127 0 1 0 0 011546 000000 01
3 wmem 0 052125 0 1 0 0 011546 000000 01
3 wmem 0 001004 0 1 0 0 011546 000000 01
3 wmem 0 030405 0 1 0 0 011546 000000 01
3 wmem 0 003002 0 1 0 0 011546 000000 01
3 wmem 0 005105 0 1 0 0 011546 000000 01
3 wmem 0 001001 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 112700 0 1 0 0 011546 000000 01
3 wmem 0 177401 0 1 0 0 011546 000000 01
3 wmem 0 100001 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 077002 0 1 0 0 011546 000000 01
3 wmem 0 000261 0 1 0 0 011546 000000 01
3 wmem 0 006100 0 1 0 0 011546 000000 01
3 wmem 0 006100 0 1 0 0 011546 000000 01
3 wmem 0 006100 0 1 0 0 011546 000000 01
3 wmem 0 010001 0 1 0 0 011546 000000 01
3 wmem 0 005401 0 1 0 0 011546 000000 01
3 wmem 0 005201 0 1 0 0 011546 000000 01
3 wmem 0 077002 0 1 0 0 011546 000000 01
3 wmem 0 005700 0 1 0 0 011546 000000 01
3 wmem 0 001002 0 1 0 0 011546 000000 01
3 wmem 0 005701 0 1 0 0 011546 000000 01
3 wmem 0 001401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 012706 0 1 0 0 011546 000000 01
3 wmem 0 000776 0 1 0 0 011546 000000 01
3 wmem 0 004767 0 1 0 0 011546 000000 01
3 wmem 0 000002 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 022716 0 1 0 0 011546 000000 01
3 wmem 0 012060 0 1 0 0 011546 000000 01
3 wmem 0 001401 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 012716 0 1 0 0 011546 000000 01
3 wmem 0 012102 0 1 0 0 011546 000000 01
3 wmem 0 000207 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 005046 0 1 0 0 011546 000000 01
3 wmem 0 012746 0 1 0 0 011546 000000 01
3 wmem 0 012114 0 1 0 0 011546 000000 01
3 wmem 0 000002 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 000137 0 1 0 0 011546 000000 01
3 wmem 0 012122 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 012705 0 1 0 0 011546 000000 01
3 wmem 0 160000 0 1 0 0 011546 000000 01
3 wmem 0 005037 0 1 0 0 011546 000000 01
3 wmem 0 000006 0 1 0 0 011546 000000 01
3 wmem 0 012737 0 1 0 0 011546 000000 01
3 wmem 0 012150 0 1 0 0 011546 000000 01
3 wmem 0 000004 0 1 0 0 011546 000000 01
3 wmem 0 012706 0 1 0 0 011546 000000 01
3 wmem 0 000776 0 1 0 0 011546 000000 01
3 wmem 0 005715 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
3 wmem 0 000000 0 1 0 0 011546 000000 01
C Exec code 35 (11/70 self test code)
2 cres 0 000000 0 1 0 0 011546 000000 00
2 wreg 7 011600 0 1 0 0 011600 000000 00
2 sta 0 000000 0 1 0 0 011546 100000 07
333 ---- - ------ 0 0 0 0 011546 000000 01 WAIT GO OK
3 rreg 7 012152 0 1 0 0 012152 000000 01 CHECK OK
3 wmem 0 000006 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
C Setup code 36 [base 12200] (systematic CMP test)
3 wmem 0 000230 0 1 0 0 012152 000000 01
3 wmem 0 012400 0 1 0 0 012152 000000 01
3 wmem 0 012401 0 1 0 0 012152 000000 01
3 wmem 0 020001 0 1 0 0 012152 000000 01
3 wmem 0 011225 0 1 0 0 012152 000000 01
3 wmem 0 077305 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
C Exec code 36 (systematic CMP test)
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 000000 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 177777 0 1 0 0 012152 000000 01
3 wmem 0 000001 0 1 0 0 012152 000000 01
3 wmem 0 077777 0 1 0 0 012152 000000 01
3 wmem 0 100000 0 1 0 0 012152 000000 01
3 wmem 0 100000 0 1 0 0 012152 000000 01
3 wmem 0 077777 0 1 0 0 012152 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000013 0 1 0 0 000013 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 012152 000000 00
2 wreg 7 012200 0 1 0 0 012200 000000 00
2 sta 0 000000 0 1 0 0 012152 100000 07
294 ---- - ------ 0 0 0 0 012152 000000 01 WAIT GO OK
3 rreg 7 012216 0 1 0 0 012216 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036054 0 1 0 0 036054 000000 01 CHECK OK
3 rreg 5 037026 0 1 0 0 037026 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
C Setup code 37 [base 12300] (systematic DIV test)
3 wmem 0 000230 0 1 0 0 037026 000000 01
3 wmem 0 012400 0 1 0 0 037026 000000 01
3 wmem 0 012401 0 1 0 0 037026 000000 01
3 wmem 0 071024 0 1 0 0 037026 000000 01
3 wmem 0 011225 0 1 0 0 037026 000000 01
3 wmem 0 010025 0 1 0 0 037026 000000 01
3 wmem 0 010125 0 1 0 0 037026 000000 01
3 wmem 0 077307 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
C Exec code 37 (systematic DIV test)
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000004 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000004 0 1 0 0 037026 000000 01
3 wmem 0 000002 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000006 0 1 0 0 037026 000000 01
3 wmem 0 000002 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000004 0 1 0 0 037026 000000 01
3 wmem 0 177776 0 1 0 0 037026 000000 01
3 wmem 0 000002 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000002 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 177776 0 1 0 0 037026 000000 01
3 wmem 0 100000 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 177776 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177773 0 1 0 0 037026 000000 01
3 wmem 0 000002 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177773 0 1 0 0 037026 000000 01
3 wmem 0 177776 0 1 0 0 037026 000000 01
3 wmem 0 177776 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 040000 0 1 0 0 037026 000000 01
3 wmem 0 000100 0 1 0 0 037026 000000 01
3 wmem 0 000200 0 1 0 0 037026 000000 01
3 wmem 0 177601 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000000 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 000001 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
3 wmem 0 177777 0 1 0 0 037026 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000023 0 1 0 0 000023 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037026 000000 00
2 wreg 7 012300 0 1 0 0 012300 000000 00
2 sta 0 000000 0 1 0 0 037026 100000 07
942 ---- - ------ 0 0 0 0 037026 000000 01 WAIT GO OK
3 rreg 7 012322 0 1 0 0 012322 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036162 0 1 0 0 036162 000000 01 CHECK OK
3 rreg 5 037162 0 1 0 0 037162 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177770 0 1 0 0 177770 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 007642 0 1 0 0 037162 000000 01
3 wmem 0 007643 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 000137 0 1 0 0 037162 000000 01
3 wmem 0 177543 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 007643 0 1 0 0 037162 000000 01
3 wmem 0 007643 0 1 0 0 037162 000000 01
3 wmem 0 100000 0 1 0 0 037162 000000 01
3 wmem 0 004376 0 1 0 0 037162 000000 01
3 wmem 0 010021 0 1 0 0 037162 000000 01
3 wmem 0 177700 0 1 0 0 037162 000000 01
3 wmem 0 170033 0 1 0 0 037162 000000 01
3 wmem 0 010021 0 1 0 0 037162 000000 01
3 wmem 0 177700 0 1 0 0 037162 000000 01
3 wmem 0 170033 0 1 0 0 037162 000000 01
3 wmem 0 167757 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 045716 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 000002 0 1 0 0 037162 000000 01
3 wmem 0 177770 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 177776 0 1 0 0 037162 000000 01
3 wmem 0 000010 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 177777 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 000002 0 1 0 0 037162 000000 01
3 wmem 0 000001 0 1 0 0 037162 000000 01
3 wmem 0 000000 0 1 0 0 037162 000000 01
3 wmem 0 000003 0 1 0 0 037162 000000 01
3 wmem 0 000023 0 1 0 0 037162 000000 01
3 wmem 0 016054 0 1 0 0 037162 000000 01
3 wmem 0 016537 0 1 0 0 037162 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000021 0 1 0 0 000021 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037162 000000 00
2 wreg 7 012300 0 1 0 0 012300 000000 00
2 sta 0 000000 0 1 0 0 037162 100000 07
928 ---- - ------ 0 0 0 0 037162 000000 01 WAIT GO OK
3 rreg 7 012322 0 1 0 0 012322 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036146 0 1 0 0 036146 000000 01 CHECK OK
3 rreg 5 037146 0 1 0 0 037146 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 007642 0 1 0 0 007642 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000137 0 1 0 0 000137 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 004376 0 1 0 0 004376 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 176024 0 1 0 0 176024 000000 01 CHECK OK
3 rmem 0 171307 0 1 0 0 171307 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001754 0 1 0 0 001754 000000 01 CHECK OK
3 rmem 0 171307 0 1 0 0 171307 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 045716 0 1 0 0 045716 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 052525 0 1 0 0 052525 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000246 0 1 0 0 000246 000000 01 CHECK OK
3 rmem 0 010222 0 1 0 0 010222 000000 01 CHECK OK
C Setup code 40 [base 12400] (systematic ASH test)
3 wmem 0 000230 0 1 0 0 037146 000000 01
3 wmem 0 016400 0 1 0 0 037146 000000 01
3 wmem 0 000002 0 1 0 0 037146 000000 01
3 wmem 0 011412 0 1 0 0 037146 000000 01
3 wmem 0 072064 0 1 0 0 037146 000000 01
3 wmem 0 000004 0 1 0 0 037146 000000 01
3 wmem 0 011265 0 1 0 0 037146 000000 01
3 wmem 0 000002 0 1 0 0 037146 000000 01
3 wmem 0 010015 0 1 0 0 037146 000000 01
3 wmem 0 062704 0 1 0 0 037146 000000 01
3 wmem 0 000006 0 1 0 0 037146 000000 01
3 wmem 0 062705 0 1 0 0 037146 000000 01
3 wmem 0 000004 0 1 0 0 037146 000000 01
3 wmem 0 077315 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
C Exec code 40 (systematic ASH test)
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 100001 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 040001 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 040001 0 1 0 0 037146 000000 01
3 wmem 0 177700 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000077 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000077 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000002 0 1 0 0 037146 000000 01
3 wmem 0 000077 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000077 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000003 0 1 0 0 037146 000000 01
3 wmem 0 000076 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000076 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000062 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000061 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000060 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000042 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000041 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 000040 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 040000 0 1 0 0 037146 000000 01
3 wmem 0 100037 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000077 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000076 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000075 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000062 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000061 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000060 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000057 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000056 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000041 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 000040 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100002 0 1 0 0 037146 000000 01
3 wmem 0 040037 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000007 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000016 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000020 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000021 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000036 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000037 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000040 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 010037 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 100001 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000001 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000002 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000016 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000017 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000020 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140001 0 1 0 0 037146 000000 01
3 wmem 0 000021 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140002 0 1 0 0 037146 000000 01
3 wmem 0 000035 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140002 0 1 0 0 037146 000000 01
3 wmem 0 000036 0 1 0 0 037146 000000 01
3 wmem 0 000000 0 1 0 0 037146 000000 01
3 wmem 0 140002 0 1 0 0 037146 000000 01
3 wmem 0 000037 0 1 0 0 037146 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000062 0 1 0 0 000062 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037146 000000 00
2 wreg 7 012400 0 1 0 0 012400 000000 00
2 sta 0 000000 0 1 0 0 037146 100000 07
3466 ---- - ------ 0 0 0 0 037146 000000 01 WAIT GO OK
3 rreg 7 012436 0 1 0 0 012436 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036454 0 1 0 0 036454 000000 01 CHECK OK
3 rreg 5 037310 0 1 0 0 037310 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 040001 0 1 0 0 040001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040001 0 1 0 0 040001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 140001 0 1 0 0 140001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 160000 0 1 0 0 160000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 170000 0 1 0 0 170000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 100002 0 1 0 0 100002 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
C Setup code 41 [base 12500] (systematic ASHC even test)
3 wmem 0 000230 0 1 0 0 037310 000000 01
3 wmem 0 016400 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 016401 0 1 0 0 037310 000000 01
3 wmem 0 000004 0 1 0 0 037310 000000 01
3 wmem 0 011412 0 1 0 0 037310 000000 01
3 wmem 0 073064 0 1 0 0 037310 000000 01
3 wmem 0 000006 0 1 0 0 037310 000000 01
3 wmem 0 011265 0 1 0 0 037310 000000 01
3 wmem 0 000004 0 1 0 0 037310 000000 01
3 wmem 0 010015 0 1 0 0 037310 000000 01
3 wmem 0 010165 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 062704 0 1 0 0 037310 000000 01
3 wmem 0 000010 0 1 0 0 037310 000000 01
3 wmem 0 062705 0 1 0 0 037310 000000 01
3 wmem 0 000006 0 1 0 0 037310 000000 01
3 wmem 0 077321 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
C Exec code 41 (systematic ASHC even test)
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177700 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000060 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000042 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000041 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000040 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177737 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177737 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100020 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177776 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 000077 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000060 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000060 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000042 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000041 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000040 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177737 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000017 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 100000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 040000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000003 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177701 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177735 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177736 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 177737 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 020037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 000001 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 000002 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 000036 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 000037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177776 0 1 0 0 037310 000000 01
3 wmem 0 000037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177774 0 1 0 0 037310 000000 01
3 wmem 0 000037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177701 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 001037 0 1 0 0 037310 000000 01
3 wmem 0 000000 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 177777 0 1 0 0 037310 000000 01
3 wmem 0 001036 0 1 0 0 037310 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000057 0 1 0 0 000057 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037310 000000 00
2 wreg 7 012500 0 1 0 0 012500 000000 00
2 sta 0 000000 0 1 0 0 037310 100000 07
4031 ---- - ------ 0 0 0 0 037310 000000 01 WAIT GO OK
3 rreg 7 012546 0 1 0 0 012546 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036570 0 1 0 0 036570 000000 01 CHECK OK
3 rreg 5 037432 0 1 0 0 037432 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 020000 0 1 0 0 020000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020000 0 1 0 0 020000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 140010 0 1 0 0 140010 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020000 0 1 0 0 020000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177774 0 1 0 0 177774 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
C Setup code 42 [base 12600] (systematic ASHC odd test)
3 wmem 0 000230 0 1 0 0 037432 000000 01
3 wmem 0 016401 0 1 0 0 037432 000000 01
3 wmem 0 000002 0 1 0 0 037432 000000 01
3 wmem 0 011412 0 1 0 0 037432 000000 01
3 wmem 0 073164 0 1 0 0 037432 000000 01
3 wmem 0 000004 0 1 0 0 037432 000000 01
3 wmem 0 011265 0 1 0 0 037432 000000 01
3 wmem 0 000002 0 1 0 0 037432 000000 01
3 wmem 0 010115 0 1 0 0 037432 000000 01
3 wmem 0 062704 0 1 0 0 037432 000000 01
3 wmem 0 000006 0 1 0 0 037432 000000 01
3 wmem 0 062705 0 1 0 0 037432 000000 01
3 wmem 0 000004 0 1 0 0 037432 000000 01
3 wmem 0 077315 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
C Exec code 42 (systematic ASHC odd test)
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 100001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 040001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 040001 0 1 0 0 037432 000000 01
3 wmem 0 177700 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000077 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000077 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000002 0 1 0 0 037432 000000 01
3 wmem 0 000077 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000077 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000003 0 1 0 0 037432 000000 01
3 wmem 0 000076 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000076 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 000060 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 000043 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 000042 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 000041 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 000040 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 040000 0 1 0 0 037432 000000 01
3 wmem 0 100037 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 020000 0 1 0 0 037432 000000 01
3 wmem 0 000043 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 020000 0 1 0 0 037432 000000 01
3 wmem 0 000042 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 020000 0 1 0 0 037432 000000 01
3 wmem 0 000041 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000077 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000076 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000075 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000061 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000060 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000057 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000056 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000055 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000042 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000041 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 000040 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100002 0 1 0 0 037432 000000 01
3 wmem 0 040037 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000007 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000016 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000020 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000021 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000036 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000037 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000040 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 010037 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 100001 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000001 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000002 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000016 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000017 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000020 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000021 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000022 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140001 0 1 0 0 037432 000000 01
3 wmem 0 000023 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140002 0 1 0 0 037432 000000 01
3 wmem 0 000035 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140002 0 1 0 0 037432 000000 01
3 wmem 0 000036 0 1 0 0 037432 000000 01
3 wmem 0 000000 0 1 0 0 037432 000000 01
3 wmem 0 140002 0 1 0 0 037432 000000 01
3 wmem 0 000037 0 1 0 0 037432 000000 01
2 wreg 2 177776 0 1 0 0 177776 000000 01
2 wreg 3 000067 0 1 0 0 000067 000000 01
2 wreg 4 036000 0 1 0 0 036000 000000 01
2 wreg 5 037000 0 1 0 0 037000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037432 000000 00
2 wreg 7 012600 0 1 0 0 012600 000000 00
2 sta 0 000000 0 1 0 0 037432 100000 07
4013 ---- - ------ 0 0 0 0 037432 000000 01 WAIT GO OK
3 rreg 7 012636 0 1 0 0 012636 000000 01 CHECK OK
3 rreg 3 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rreg 4 036512 0 1 0 0 036512 000000 01 CHECK OK
3 rreg 5 037334 0 1 0 0 037334 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 040001 0 1 0 0 040001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040001 0 1 0 0 040001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 040001 0 1 0 0 040001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 120000 0 1 0 0 120000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 050000 0 1 0 0 050000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100002 0 1 0 0 100002 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 140001 0 1 0 0 140001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 160000 0 1 0 0 160000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 170000 0 1 0 0 170000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 100002 0 1 0 0 100002 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
C Setup code 43 [base 12700] (Begemot MARK instruction test)
3 wmem 0 012705 0 1 0 0 037334 000000 01
3 wmem 0 077077 0 1 0 0 037334 000000 01
3 wmem 0 010546 0 1 0 0 037334 000000 01
3 wmem 0 012746 0 1 0 0 037334 000000 01
3 wmem 0 000012 0 1 0 0 037334 000000 01
3 wmem 0 012746 0 1 0 0 037334 000000 01
3 wmem 0 000023 0 1 0 0 037334 000000 01
3 wmem 0 012746 0 1 0 0 037334 000000 01
3 wmem 0 006402 0 1 0 0 037334 000000 01
3 wmem 0 010605 0 1 0 0 037334 000000 01
3 wmem 0 004737 0 1 0 0 037334 000000 01
3 wmem 0 012770 0 1 0 0 037334 000000 01
3 wmem 0 000240 0 1 0 0 037334 000000 01
3 wmem 0 000000 0 1 0 0 037334 000000 01
3 wmem 0 010546 0 1 0 0 037334 000000 01
3 wmem 0 162706 0 1 0 0 037334 000000 01
3 wmem 0 000176 0 1 0 0 037334 000000 01
3 wmem 0 012746 0 1 0 0 037334 000000 01
3 wmem 0 006477 0 1 0 0 037334 000000 01
3 wmem 0 010605 0 1 0 0 037334 000000 01
3 wmem 0 004737 0 1 0 0 037334 000000 01
3 wmem 0 012770 0 1 0 0 037334 000000 01
3 wmem 0 000240 0 1 0 0 037334 000000 01
3 wmem 0 000000 0 1 0 0 037334 000000 01
3 wmem 0 000205 0 1 0 0 037334 000000 01
C Exec code 43 (Begemot MARK test)
C Exec test 43.1 (basics)
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 037334 000000 00
2 wreg 7 012700 0 1 0 0 012700 000000 00
2 sta 0 000000 0 1 0 0 037334 100000 07
69 ---- - ------ 0 0 0 0 037334 000000 01 WAIT GO OK
3 rreg 7 012734 0 1 0 0 012734 000000 01 CHECK OK
3 rreg 5 077077 0 1 0 0 077077 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
3 rmem 0 012730 0 1 0 0 012730 000000 01 CHECK OK
3 rmem 0 006402 0 1 0 0 006402 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 077077 0 1 0 0 077077 000000 01 CHECK OK
C Exec test 43.2 (MARK with max. # of args)
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 001400 000000 00
2 wreg 7 012740 0 1 0 0 012740 000000 00
2 sta 0 000000 0 1 0 0 001400 100000 07
53 ---- - ------ 0 0 0 0 001400 000000 01 WAIT GO OK
3 rreg 7 012764 0 1 0 0 012764 000000 01 CHECK OK
3 rreg 5 077077 0 1 0 0 077077 000000 01 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 01 CHECK OK
C Setup code 44 [base 13000] (Implementation variations)
3 wmem 0 010424 0 1 0 0 001400 000000 01
3 wmem 0 010444 0 1 0 0 001400 000000 01
3 wmem 0 010764 0 1 0 0 001400 000000 01
3 wmem 0 000002 0 1 0 0 001400 000000 01
3 wmem 0 000124 0 1 0 0 001400 000000 01
3 wmem 0 000104 0 1 0 0 001400 000000 01
3 wmem 0 000304 0 1 0 0 001400 000000 01
3 wmem 0 005214 0 1 0 0 001400 000000 01
3 wmem 0 000006 0 1 0 0 001400 000000 01
3 wmem 0 000000 0 1 0 0 001400 000000 01
3 wmem 0 000002 0 1 0 0 001400 000000 01
3 wmem 0 000000 0 1 0 0 001400 000000 01
3 wmem 0 010011 0 1 0 0 001400 000000 01
3 wmem 0 010046 0 1 0 0 001400 000000 01
3 wmem 0 000114 0 1 0 0 001400 000000 01
3 wmem 0 010021 0 1 0 0 001400 000000 01
3 wmem 0 012100 0 1 0 0 001400 000000 01
3 wmem 0 005221 0 1 0 0 001400 000000 01
3 wmem 0 106621 0 1 0 0 001400 000000 01
3 wmem 0 106506 0 1 0 0 001400 000000 01
3 wmem 0 106606 0 1 0 0 001400 000000 01
3 wmem 0 000003 0 1 0 0 001400 000000 01
3 wmem 0 000240 0 1 0 0 001400 000000 01
3 wmem 0 000000 0 1 0 0 001400 000000 01
C Exec code 44 (Implementation variations)
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source
2 cres 0 000000 0 1 0 0 001400 000000 00
2 wpsw 0 000000 0 1 0 0 000000 000000 00
2 wreg 4 001600 0 1 0 0 001600 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013000 0 1 0 0 013000 000000 00
8 step 0 000000 0 0 0 0 001400 000000 04 WAIT STEP OK
3 rreg 7 013002 0 1 0 0 013002 000000 04 CHECK OK
3 rreg 4 001602 0 1 0 0 001602 000000 04 CHECK OK
3 rmem 0 001600 0 1 0 0 001600 000000 04 CHECK OK
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source
2 wreg 4 001600 0 1 0 0 001600 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013002 0 1 0 0 013002 000000 04
9 step 0 000000 0 0 0 0 001602 000000 04 WAIT STEP OK
3 rreg 7 013004 0 1 0 0 013004 000000 04 CHECK OK
3 rreg 4 001576 0 1 0 0 001576 000000 04 CHECK OK
3 rmem 0 001600 0 1 0 0 001600 000000 04 CHECK OK
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
2 wreg 4 001600 0 1 0 0 001600 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013004 0 1 0 0 013004 000000 04
10 step 0 000000 0 0 0 0 001576 000000 04 WAIT STEP OK
3 rreg 7 013010 0 1 0 0 013010 000000 04 CHECK OK
3 rmem 0 013006 0 1 0 0 013006 000000 04 CHECK OK
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20}
2 wreg 4 013074 0 1 0 0 013074 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013010 0 1 0 0 013010 000000 04
8 step 0 000000 0 0 0 0 013010 000000 04 WAIT STEP OK
3 rreg 7 013074 0 1 0 0 013074 000000 04 CHECK OK
3 rreg 4 013076 0 1 0 0 013076 000000 04 CHECK OK
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others}
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated
5 wmem 0 000000 0 1 0 0 013076 000000 04
2 wreg 4 000000 0 1 0 0 000000 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013012 0 1 0 0 013012 000000 04
18 step 0 000000 0 0 0 0 013076 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
C test 44.6: SWAB does not change V {15,20} or clears V {all others}
2 wreg 4 000300 0 1 0 0 000300 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013014 0 1 0 0 013014 000000 04
2 wpsw 0 000017 0 1 0 0 000017 000000 04
7 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 013016 0 1 0 0 013016 000000 04 CHECK OK
3 rreg 4 140000 0 1 0 0 140000 000000 04 CHECK OK
3 rpsw 0 000004 0 1 0 0 000004 000000 04 CHECK OK
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
2 wreg 4 177700 0 1 0 0 177700 000000 04
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013016 0 1 0 0 013016 000000 04
22 step 0 000000 0 0 0 0 140000 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
5 rmem 0 000020 0 1 0 0 000020 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11}
3 wmem 0 013070 0 1 0 0 001374 000000 04
3 wmem 0 000020 0 1 0 0 001374 000000 04
2 wreg 6 001374 0 1 0 0 001374 000000 04
2 wreg 7 013020 0 1 0 0 013020 000000 04
2 sta 0 000000 0 1 0 0 001374 100000 07
28 ---- - ------ 0 0 0 0 001374 000000 01 WAIT GO OK
3 rreg 7 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 013072 0 1 0 0 013072 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 001374 000000 00
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11}
3 wmem 0 013070 0 1 0 0 001374 000000 00
3 wmem 0 000020 0 1 0 0 001374 000000 00
2 wreg 6 001374 0 1 0 0 001374 000000 00
2 wreg 7 013024 0 1 0 0 013024 000000 00
2 sta 0 000000 0 1 0 0 001374 100000 07
24 ---- - ------ 0 0 0 0 001374 000000 01 WAIT GO OK
3 rreg 7 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 013070 0 1 0 0 013070 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 001374 000000 00
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit
2 wreg 0 000030 0 1 0 0 000030 000000 00
2 wreg 1 177776 0 1 0 0 177776 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013030 0 1 0 0 013030 000000 00
10 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 013032 0 1 0 0 013032 000000 04 CHECK OK
3 rpsw 0 000010 0 1 0 0 000010 000000 04 CHECK OK
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35}
2 wreg 6 001401 0 1 0 0 001401 000000 04
2 wreg 7 013032 0 1 0 0 013032 000000 04
21 step 0 000000 0 0 0 0 013032 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 013034 0 1 0 0 013034 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 000000 000000 00
3 wmem 0 000000 0 1 0 0 000000 000000 00
3 wmem 0 000000 0 1 0 0 000000 000000 00
5 wmem 0 077400 0 1 0 0 000000 000000 00
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
2 cres 0 000000 0 1 0 0 000000 000000 00
5 wmem 0 000001 0 1 0 0 000000 000000 00
2 wreg 4 100000 0 1 0 0 100000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013034 0 1 0 0 013034 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
22 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 000254 0 1 0 0 000254 000000 01 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 01 CHECK OK
3 rmem 0 100002 0 1 0 0 100002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 001374 000000 00
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstw chain (mov r0,(r1)+)
5 wmem 0 000001 0 1 0 0 001374 000000 00
2 wreg 1 100000 0 1 0 0 100000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013036 0 1 0 0 013036 000000 00
19 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rreg 1 100002 0 1 0 0 100002 000000 04 CHECK OK
5 rmem 0 100011 0 1 0 0 100011 000000 04 CHECK OK
5 rmem 0 000021 0 1 0 0 000021 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 100002 000000 00
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for srcr chain (mov (r1)+,r0)
5 wmem 0 000001 0 1 0 0 100002 000000 00
2 wreg 1 100000 0 1 0 0 100000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013040 0 1 0 0 013040 000000 00
19 step 0 000000 0 0 0 0 100002 000000 04 WAIT STEP OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rreg 1 100002 0 1 0 0 100002 000000 04 CHECK OK
5 rmem 0 100011 0 1 0 0 100011 000000 04 CHECK OK
5 rmem 0 000021 0 1 0 0 000021 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 100002 000000 00
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstr chain (inc (r1)+)
5 wmem 0 000001 0 1 0 0 100002 000000 00
2 wreg 1 100000 0 1 0 0 100000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013042 0 1 0 0 013042 000000 00
19 step 0 000000 0 0 0 0 100002 000000 04 WAIT STEP OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rreg 1 100002 0 1 0 0 100002 000000 04 CHECK OK
5 rmem 0 100011 0 1 0 0 100011 000000 04 CHECK OK
5 rmem 0 000021 0 1 0 0 000021 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 100002 000000 00
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dsta chain (mtpd (r1)+)
5 wmem 0 000001 0 1 0 0 100002 000000 00
2 wreg 1 100000 0 1 0 0 100000 000000 00
2 wreg 6 001376 0 1 0 0 001376 000000 00
2 wreg 7 013044 0 1 0 0 013044 000000 00
3 wmem 0 123456 0 1 0 0 100002 000000 00
22 step 0 000000 0 0 0 0 100002 000000 04 WAIT STEP OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rreg 1 100002 0 1 0 0 100002 000000 04 CHECK OK
5 rmem 0 100011 0 1 0 0 100011 000000 04 CHECK OK
5 rmem 0 010426 0 1 0 0 010426 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 100002 000000 00
5 wmem 0 077406 0 1 0 0 100002 000000 00
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
5 wmem 0 000001 0 1 0 0 100002 000000 00
2 wreg 1 001400 0 1 0 0 001400 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wpsw 0 100000 0 1 0 0 100000 000000 00
2 wreg 7 013042 0 1 0 0 013042 000000 00
16 step 0 000000 0 0 0 0 100002 000000 04 WAIT STEP OK
3 rreg 7 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rreg 1 001400 0 1 0 0 001400 000000 04 CHECK OK
5 rmem 0 140101 0 1 0 0 140101 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 rmem 0 013042 0 1 0 0 013042 000000 04 CHECK OK
3 rmem 0 013044 0 1 0 0 013044 000000 04 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 001400 000000 00
C test 44.43: user mode HALT: trap 4 {70} or 10 {others}
5 wmem 0 000000 0 1 0 0 001400 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wpsw 0 170000 0 1 0 0 170000 000000 00
2 wreg 7 013022 0 1 0 0 013022 000000 00
18 step 0 000000 0 0 0 0 001400 000000 04 WAIT STEP OK
3 rreg 7 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
3 rmem 0 013024 0 1 0 0 013024 000000 04 CHECK OK
3 rmem 0 170000 0 1 0 0 170000 000000 04 CHECK OK
5 rmem 0 000200 0 1 0 0 000200 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 001374 000000 00
C test 44.44: PDR bit<0> implemented {70} or not {others}
5 wmem 0 077401 0 1 0 0 001374 000000 00
5 rmem 0 077401 0 1 0 0 077401 000000 00 CHECK OK
5 wmem 0 077406 0 1 0 0 001374 000000 00
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others}
5 wmem 0 077404 0 1 0 0 001374 000000 00
5 wmem 0 077404 0 1 0 0 001374 000000 00
5 rmem 0 077404 0 1 0 0 077404 000000 00 CHECK OK
5 rmem 0 077404 0 1 0 0 077404 000000 00 CHECK OK
5 wmem 0 000001 0 1 0 0 001374 000000 00
2 wreg 0 123456 0 1 0 0 123456 000000 00
2 wreg 1 030000 0 1 0 0 030000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013030 0 1 0 0 013030 000000 00
8 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 013032 0 1 0 0 013032 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 04 CHECK OK
3 wmem 0 000000 0 1 0 0 001400 000000 04
5 rmem 0 077604 0 1 0 0 077604 000000 04 CHECK OK
5 rmem 0 077704 0 1 0 0 077704 000000 04 CHECK OK
5 wmem 0 077406 0 1 0 0 001400 000000 04
5 wmem 0 077406 0 1 0 0 001400 000000 04
2 cres 0 000000 0 1 0 0 001400 000000 00
C test 44.46: Full PAR implemented {44,70,J11} or not {others}
5 wmem 0 177777 0 1 0 0 001400 000000 00
5 rmem 0 177777 0 1 0 0 177777 000000 00 CHECK OK
5 wmem 0 001000 0 1 0 0 001400 000000 00
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
5 wmem 0 001000 0 1 0 0 001400 000000 00
5 rmem 0 001000 0 1 0 0 001000 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 001400 000000 00
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
5 wmem 0 000007 0 1 0 0 001400 000000 00
5 rmem 0 000007 0 1 0 0 000007 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 001400 000000 00
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
5 wmem 0 000060 0 1 0 0 001400 000000 00
5 rmem 0 000060 0 1 0 0 000060 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 001400 000000 00
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
5 wmem 0 000010 0 1 0 0 001400 000000 00
5 rmem 0 000000 0 1 0 0 000000 000000 00 CHECK OK
5 wmem 0 000000 0 1 0 0 001400 000000 00
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
C here W11 behaves like {others}, fetches are not tracked in SSR2
C Also: instruction complete flag set in SSR0 after bpt.
5 wmem 0 000001 0 1 0 0 001400 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013052 0 1 0 0 013052 000000 00
17 step 0 000000 0 0 0 0 001400 000000 04 WAIT STEP OK
3 rreg 7 000016 0 1 0 0 000016 000000 04 CHECK OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 rmem 0 013052 0 1 0 0 013052 000000 04 CHECK OK
7 step 0 000000 0 0 0 0 000016 000000 01 WAIT STEP OK
3 rreg 7 000020 0 1 0 0 000020 000000 01 CHECK OK
5 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
5 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
5 rmem 0 000016 0 1 0 0 000016 000000 01 CHECK OK
2 cres 0 000000 0 1 0 0 000020 000000 00
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11}
2 wreg 0 000001 0 1 0 0 000001 000000 00
2 wreg 1 000101 0 1 0 0 000101 000000 00
2 wreg 2 000201 0 1 0 0 000201 000000 00
2 wreg 3 000301 0 1 0 0 000301 000000 00
2 wreg 4 000401 0 1 0 0 000401 000000 00
2 wreg 5 000501 0 1 0 0 000501 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 000701 0 1 0 0 000701 000000 00
2 wpsw 0 004000 0 1 0 0 004000 000000 00
2 wreg 0 010001 0 1 0 0 010001 000000 00
2 wreg 1 010101 0 1 0 0 010101 000000 00
2 wreg 2 010201 0 1 0 0 010201 000000 00
2 wreg 3 010301 0 1 0 0 010301 000000 00
2 wreg 4 010401 0 1 0 0 010401 000000 00
2 wreg 5 010501 0 1 0 0 010501 000000 00
2 wpsw 0 044000 0 1 0 0 044000 000000 00
2 wreg 6 010601 0 1 0 0 010601 000000 00
2 wpsw 0 144000 0 1 0 0 144000 000000 00
2 wreg 6 110601 0 1 0 0 110601 000000 00
C 52a: MFPS for pmode=10
2 wpsw 0 020000 0 1 0 0 020000 000000 00
2 wreg 7 013046 0 1 0 0 013046 000000 00
10 step 0 000000 0 0 0 0 000020 000000 04 WAIT STEP OK
3 rreg 7 013050 0 1 0 0 013050 000000 04 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 04 CHECK OK
3 rmem 0 013046 0 1 0 0 013046 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 001376 000000 00
C 52a: MTPS for pmode=10
3 wmem 0 123446 0 1 0 0 001376 000000 00
2 wpsw 0 020000 0 1 0 0 020000 000000 00
2 wreg 7 013050 0 1 0 0 013050 000000 00
9 step 0 000000 0 0 0 0 001376 000000 04 WAIT STEP OK
3 rreg 7 013052 0 1 0 0 013052 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
3 rreg 0 000001 0 1 0 0 000001 000000 04 CHECK OK
3 rreg 1 000101 0 1 0 0 000101 000000 04 CHECK OK
3 rreg 2 000201 0 1 0 0 000201 000000 04 CHECK OK
3 rreg 3 000301 0 1 0 0 000301 000000 04 CHECK OK
3 rreg 4 000401 0 1 0 0 000401 000000 04 CHECK OK
3 rreg 5 000501 0 1 0 0 000501 000000 04 CHECK OK
2 wpsw 0 004000 0 1 0 0 004000 000000 04
3 rreg 0 010001 0 1 0 0 010001 000000 04 CHECK OK
3 rreg 1 010101 0 1 0 0 010101 000000 04 CHECK OK
3 rreg 2 010201 0 1 0 0 010201 000000 04 CHECK OK
3 rreg 3 010301 0 1 0 0 010301 000000 04 CHECK OK
3 rreg 4 010401 0 1 0 0 010401 000000 04 CHECK OK
3 rreg 5 010501 0 1 0 0 010501 000000 04 CHECK OK
2 wpsw 0 044000 0 1 0 0 044000 000000 04
3 rreg 6 010601 0 1 0 0 010601 000000 04 CHECK OK
2 wpsw 0 144000 0 1 0 0 144000 000000 04
3 rreg 6 110601 0 1 0 0 110601 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 110601 000000 00
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop
3 wmem 0 106621 0 1 0 0 110601 000000 00
3 wmem 0 106521 0 1 0 0 110601 000000 00
3 wmem 0 004721 0 1 0 0 110601 000000 00
3 wmem 0 000000 0 1 0 0 110601 000000 00
3 wmem 0 000207 0 1 0 0 110601 000000 00
C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
C test 45.1: mtpd (r1)+
2 cres 0 000000 0 1 0 0 110601 000000 00
5 wmem 0 000001 0 1 0 0 110601 000000 00
3 wmem 0 123456 0 1 0 0 110601 000000 00
2 wreg 1 030000 0 1 0 0 030000 000000 00
2 wreg 6 001376 0 1 0 0 001376 000000 00
2 wreg 7 013100 0 1 0 0 013100 000000 00
11 step 0 000000 0 0 0 0 110601 000000 04 WAIT STEP OK
3 rreg 7 013102 0 1 0 0 013102 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
3 rreg 1 030002 0 1 0 0 030002 000000 04 CHECK OK
5 rmem 0 000003 0 1 0 0 000003 000000 04 CHECK OK
5 rmem 0 010426 0 1 0 0 010426 000000 04 CHECK OK
5 rmem 0 013100 0 1 0 0 013100 000000 04 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 030002 000000 00
C test 45.2: mfpd (r1)+
5 wmem 0 000001 0 1 0 0 030002 000000 00
2 wreg 1 030000 0 1 0 0 030000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013102 0 1 0 0 013102 000000 00
12 step 0 000000 0 0 0 0 030002 000000 04 WAIT STEP OK
3 rreg 7 013104 0 1 0 0 013104 000000 04 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 04 CHECK OK
3 rreg 1 030002 0 1 0 0 030002 000000 04 CHECK OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 173021 0 1 0 0 173021 000000 04 CHECK OK
5 rmem 0 013102 0 1 0 0 013102 000000 04 CHECK OK
3 rmem 0 123456 0 1 0 0 123456 000000 04 CHECK OK
3 wmem 0 000000 0 1 0 0 030002 000000 04
2 cres 0 000000 0 1 0 0 030002 000000 00
C test 45.3: jsr pc,(r1)+ and rts pc
5 wmem 0 000001 0 1 0 0 030002 000000 00
2 wreg 1 013110 0 1 0 0 013110 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013104 0 1 0 0 013104 000000 00
12 step 0 000000 0 0 0 0 030002 000000 04 WAIT STEP OK
3 rreg 7 013110 0 1 0 0 013110 000000 04 CHECK OK
3 rreg 6 001376 0 1 0 0 001376 000000 04 CHECK OK
3 rreg 1 013112 0 1 0 0 013112 000000 04 CHECK OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 173021 0 1 0 0 173021 000000 04 CHECK OK
5 rmem 0 013104 0 1 0 0 013104 000000 04 CHECK OK
3 rmem 0 013106 0 1 0 0 013106 000000 04 CHECK OK
9 step 0 000000 0 0 0 0 013112 000000 04 WAIT STEP OK
3 rreg 7 013106 0 1 0 0 013106 000000 04 CHECK OK
3 rreg 6 001400 0 1 0 0 001400 000000 04 CHECK OK
5 rmem 0 000001 0 1 0 0 000001 000000 04 CHECK OK
5 rmem 0 000026 0 1 0 0 000026 000000 04 CHECK OK
5 rmem 0 013110 0 1 0 0 013110 000000 04 CHECK OK
2 cres 0 000000 0 1 0 0 001400 000000 00
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)
3 wmem 0 000230 0 1 0 0 001400 000000 00
3 wmem 0 012205 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 011023 0 1 0 0 001400 000000 00
3 wmem 0 010523 0 1 0 0 001400 000000 00
3 wmem 0 077106 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000230 0 1 0 0 001400 000000 00
3 wmem 0 012215 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 011023 0 1 0 0 001400 000000 00
3 wmem 0 011523 0 1 0 0 001400 000000 00
3 wmem 0 077106 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000230 0 1 0 0 001400 000000 00
3 wmem 0 012204 0 1 0 0 001400 000000 00
3 wmem 0 012205 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 011023 0 1 0 0 001400 000000 00
3 wmem 0 010523 0 1 0 0 001400 000000 00
3 wmem 0 077107 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000230 0 1 0 0 001400 000000 00
3 wmem 0 012214 0 1 0 0 001400 000000 00
3 wmem 0 012215 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 011023 0 1 0 0 001400 000000 00
3 wmem 0 011523 0 1 0 0 001400 000000 00
3 wmem 0 077107 0 1 0 0 001400 000000 00
3 wmem 0 000000 0 1 0 0 001400 000000 00
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word)
C Exec test 46.1wr: COM - reg
3 wmem 0 000000 0 1 0 0 001400 000000 00
3 wmem 0 000001 0 1 0 0 001400 000000 00
3 wmem 0 077777 0 1 0 0 001400 000000 00
3 wmem 0 100000 0 1 0 0 001400 000000 00
3 wmem 0 177777 0 1 0 0 001400 000000 00
3 wmem 0 000241 0 1 0 0 001400 000000 00
3 wmem 0 005105 0 1 0 0 001400 000000 00
2 wreg 0 177776 0 1 0 0 177776 000000 00
2 wreg 1 000005 0 1 0 0 000005 000000 00
2 wreg 2 036000 0 1 0 0 036000 000000 00
2 wreg 3 037000 0 1 0 0 037000 000000 00
2 wreg 4 000000 0 1 0 0 000000 000000 00
2 wreg 5 000000 0 1 0 0 000000 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 cres 0 000000 0 1 0 0 001400 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 001400 100000 07
158 ---- - ------ 0 0 0 0 001400 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.1wm: COM - mem
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005115 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013220 0 1 0 0 013220 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
203 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013240 0 1 0 0 013240 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.2wrc0: INC - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.2wrc1: INC - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.3wrc0: DEC - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
C Exec test 46.3wrc1: DEC - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
C Exec test 46.4wr: NEG - reg
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 46.5wrc0: ADC - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005505 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
C Exec test 46.5wrc1: ADC - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005505 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.6wrc0: SBC - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 005605 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
C Exec test 46.6wrc1: SBC - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005605 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
C Exec test 46.7wr: TST - reg
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005705 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
C Exec test 46.7wm: TST - mem
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 005715 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013220 0 1 0 0 013220 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
193 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013240 0 1 0 0 013240 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
C Exec test 46.8wrc0: ROR - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 000100 0 1 0 0 000000 000000 01
3 wmem 0 000101 0 1 0 0 000000 000000 01
3 wmem 0 040100 0 1 0 0 000000 000000 01
3 wmem 0 100100 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 006005 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040000 0 1 0 0 040000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020040 0 1 0 0 020040 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 040040 0 1 0 0 040040 000000 01 CHECK OK
C Exec test 46.8wrc1: ROR - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 006005 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100040 0 1 0 0 100040 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100040 0 1 0 0 100040 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 120040 0 1 0 0 120040 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140040 0 1 0 0 140040 000000 01 CHECK OK
C Exec test 46.9wrc0: ROL - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 006105 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000202 0 1 0 0 000202 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100200 0 1 0 0 100200 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
C Exec test 46.9wrc1: ROL - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 006105 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000203 0 1 0 0 000203 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100201 0 1 0 0 100201 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
C Exec test 46.10wrc0: ASR - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 006205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020040 0 1 0 0 020040 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140040 0 1 0 0 140040 000000 01 CHECK OK
C Exec test 46.10wrc1: ASR - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 006205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140000 0 1 0 0 140000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 020040 0 1 0 0 020040 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 140040 0 1 0 0 140040 000000 01 CHECK OK
C Exec test 46.11wrc0: ASL - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 006305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000202 0 1 0 0 000202 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100200 0 1 0 0 100200 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
C Exec test 46.11wrc1: ASL - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 006305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000202 0 1 0 0 000202 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100200 0 1 0 0 100200 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
C Exec test 46.12wrc0: MOV - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 010405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
113 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
C Exec test 46.12wrc1: MOV - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 010405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
113 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
C Exec test 46.12mc0: MOV - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 011415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
146 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
C Exec test 46.13wrc0: BIT - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000011 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000011 0 1 0 0 000000 000000 01
3 wmem 0 000110 0 1 0 0 000000 000000 01
3 wmem 0 000011 0 1 0 0 000000 000000 01
3 wmem 0 001100 0 1 0 0 000000 000000 01
3 wmem 0 110000 0 1 0 0 000000 000000 01
3 wmem 0 011000 0 1 0 0 000000 000000 01
3 wmem 0 110000 0 1 0 0 000000 000000 01
3 wmem 0 110000 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 030405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000110 0 1 0 0 000110 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 011000 0 1 0 0 011000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 110000 0 1 0 0 110000 000000 01 CHECK OK
C Exec test 46.13wrc1: BIT - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 030405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000110 0 1 0 0 000110 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 011000 0 1 0 0 011000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 110000 0 1 0 0 110000 000000 01 CHECK OK
C Exec test 46.13wmc0: BIT - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 031415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
284 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000110 0 1 0 0 000110 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 011000 0 1 0 0 011000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 110000 0 1 0 0 110000 000000 01 CHECK OK
C Exec test 46.14wrc0: BIC - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 040405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001000 0 1 0 0 001000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.14wrc1: BIC - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 040405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 001000 0 1 0 0 001000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.14wrc0: BIC - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 041415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
296 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001100 0 1 0 0 001100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001000 0 1 0 0 001000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.15wrc0: BIS - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 050405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000111 0 1 0 0 000111 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001111 0 1 0 0 001111 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 111000 0 1 0 0 111000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 110000 0 1 0 0 110000 000000 01 CHECK OK
C Exec test 46.15wrc1: BIS - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 050405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000111 0 1 0 0 000111 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 001111 0 1 0 0 001111 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 111000 0 1 0 0 111000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 110000 0 1 0 0 110000 000000 01 CHECK OK
C Exec test 46.16wrc0: XOR - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 074405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 001111 0 1 0 0 001111 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 101000 0 1 0 0 101000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.16wrc1: XOR - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 074405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000101 0 1 0 0 000101 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 001111 0 1 0 0 001111 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 101000 0 1 0 0 101000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.17wr: CMP - reg
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 077776 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 077777 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 100001 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 177777 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 020405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000023 0 1 0 0 000023 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
673 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
C Exec test 46.18r: ADD - reg
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 060405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000023 0 1 0 0 000023 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
673 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 177775 0 1 0 0 177775 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
C Exec test 46.19r: SUB - reg
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 160405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000023 0 1 0 0 000023 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
673 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 077776 0 1 0 0 077776 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 077777 0 1 0 0 077777 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177777 0 1 0 0 177777 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177776 0 1 0 0 177776 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.20r: SWAP - reg
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000400 0 1 0 0 000000 000000 01
3 wmem 0 100000 0 1 0 0 000000 000000 01
3 wmem 0 000401 0 1 0 0 000000 000000 01
3 wmem 0 000600 0 1 0 0 000000 000000 01
3 wmem 0 100001 0 1 0 0 000000 000000 01
3 wmem 0 100200 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 000305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000011 0 1 0 0 000011 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
278 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000400 0 1 0 0 000400 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 100000 0 1 0 0 100000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000401 0 1 0 0 000401 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 100001 0 1 0 0 100001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000600 0 1 0 0 000600 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 100200 0 1 0 0 100200 000000 01 CHECK OK
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte)
C Exec test 46.1br: COMB - reg
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105105 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.1bm: COMB - mem
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105115 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013220 0 1 0 0 013220 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
203 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013240 0 1 0 0 013240 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.2brc0: INCB - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.2brc1: INCB - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.3brc0: DECB - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000176 0 1 0 0 000176 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
C Exec test 46.3brc1: DECB - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000176 0 1 0 0 000176 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
C Exec test 46.4br: NEGB - reg
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
C Exec test 46.5brc0: ADCB - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105505 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
C Exec test 46.5brc1: ADCB - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105505 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000201 0 1 0 0 000201 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.6brc0: SBCB - reg,C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 105605 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
C Exec test 46.6brc1: SBCB - reg,C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105605 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000176 0 1 0 0 000176 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000376 0 1 0 0 000376 000000 01 CHECK OK
C Exec test 46.7br: TSTB - reg
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105705 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
158 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
C Exec test 46.7bm: TSTB - mem
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 105715 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000005 0 1 0 0 000005 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013220 0 1 0 0 013220 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
193 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013240 0 1 0 0 013240 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
C Exec test 46.8brc0: RORB - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000010 0 1 0 0 000000 000000 01
3 wmem 0 000011 0 1 0 0 000000 000000 01
3 wmem 0 000110 0 1 0 0 000000 000000 01
3 wmem 0 000210 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 106005 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000100 0 1 0 0 000100 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000044 0 1 0 0 000044 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000104 0 1 0 0 000104 000000 01 CHECK OK
C Exec test 46.8brc1: RORB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 106005 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000204 0 1 0 0 000204 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000204 0 1 0 0 000204 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000244 0 1 0 0 000244 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000304 0 1 0 0 000304 000000 01 CHECK OK
C Exec test 46.9brc0: ROLB - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 106105 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000220 0 1 0 0 000220 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
C Exec test 46.9brc1: ROLB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 106105 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000023 0 1 0 0 000023 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000221 0 1 0 0 000221 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000021 0 1 0 0 000021 000000 01 CHECK OK
C Exec test 46.10brc0: ASRB - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 106205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000044 0 1 0 0 000044 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000304 0 1 0 0 000304 000000 01 CHECK OK
C Exec test 46.10brc1: ASRB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 106205 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000044 0 1 0 0 000044 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000304 0 1 0 0 000304 000000 01 CHECK OK
C Exec test 46.11brc0: ASLB - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 106305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000220 0 1 0 0 000220 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
C Exec test 46.11brc1: ASLB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 106305 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000007 0 1 0 0 000007 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013200 0 1 0 0 013200 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013220 0 1 0 0 013220 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 01 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 01 CHECK OK
3 rmem 0 000220 0 1 0 0 000220 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000020 0 1 0 0 000020 000000 01 CHECK OK
C Exec test 46.12brc0: MOVB - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 110405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
113 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 177600 0 1 0 0 177600 000000 01 CHECK OK
C Exec test 46.12brc1: MOVB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 110405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
113 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 177600 0 1 0 0 177600 000000 01 CHECK OK
C Exec test 46.12bmc0: MOVB - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 111415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000003 0 1 0 0 000003 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
146 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
C Exec test 46.13brc0: BITB - reg, C=0
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000003 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000003 0 1 0 0 000000 000000 01
3 wmem 0 000006 0 1 0 0 000000 000000 01
3 wmem 0 000003 0 1 0 0 000000 000000 01
3 wmem 0 000014 0 1 0 0 000000 000000 01
3 wmem 0 000300 0 1 0 0 000000 000000 01
3 wmem 0 000140 0 1 0 0 000000 000000 01
3 wmem 0 000300 0 1 0 0 000000 000000 01
3 wmem 0 000300 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 130405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000140 0 1 0 0 000140 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
C Exec test 46.13brc1: BITB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 130405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000140 0 1 0 0 000140 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
C Exec test 46.13bmc0: BITB - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 131415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
284 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000006 0 1 0 0 000006 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000140 0 1 0 0 000140 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
C Exec test 46.14brc0: BICB - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 140405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.14brc1: BICB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 140405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.14bmrc0: BICB - mem, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 141415 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 001400 0 1 0 0 001400 000000 01
2 wreg 5 001402 0 1 0 0 001402 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013270 0 1 0 0 013270 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
296 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013312 0 1 0 0 013312 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000014 0 1 0 0 000014 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000040 0 1 0 0 000040 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 46.15brc0: BISB - reg, C=0
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 150405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000017 0 1 0 0 000017 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000340 0 1 0 0 000340 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
C Exec test 46.15brc1: BISB - reg, C=1
3 wmem 0 000261 0 1 0 0 000000 000000 01
3 wmem 0 150405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000006 0 1 0 0 000006 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
218 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000005 0 1 0 0 000005 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000007 0 1 0 0 000007 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000017 0 1 0 0 000017 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000340 0 1 0 0 000340 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000300 0 1 0 0 000300 000000 01 CHECK OK
C Exec test 46.17br: CMPB - reg
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000176 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000177 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000201 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000200 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000001 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000377 0 1 0 0 000000 000000 01
3 wmem 0 000241 0 1 0 0 000000 000000 01
3 wmem 0 120405 0 1 0 0 000000 000000 01
2 wreg 0 177776 0 1 0 0 177776 000000 01
2 wreg 1 000023 0 1 0 0 000023 000000 01
2 wreg 2 036000 0 1 0 0 036000 000000 01
2 wreg 3 037000 0 1 0 0 037000 000000 01
2 wreg 4 000000 0 1 0 0 000000 000000 01
2 wreg 5 000000 0 1 0 0 000000 000000 01
2 wreg 6 001400 0 1 0 0 001400 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013240 0 1 0 0 013240 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
673 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013262 0 1 0 0 013262 000000 01 CHECK OK
3 rreg 1 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000002 0 1 0 0 000002 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000011 0 1 0 0 000011 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000010 0 1 0 0 000010 000000 01 CHECK OK
3 rmem 0 000177 0 1 0 0 000177 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000013 0 1 0 0 000013 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
3 rmem 0 000200 0 1 0 0 000200 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
3 rmem 0 000004 0 1 0 0 000004 000000 01 CHECK OK
3 rmem 0 000377 0 1 0 0 000377 000000 01 CHECK OK
C Setup code 47 [base 13400] (pipeline torture tests)
3 wmem 0 000077 0 1 0 0 000000 000000 01
3 wmem 0 016727 0 1 0 0 000000 000000 01
3 wmem 0 177772 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 016737 0 1 0 0 000000 000000 01
3 wmem 0 177770 0 1 0 0 000000 000000 01
3 wmem 0 013400 0 1 0 0 000000 000000 01
3 wmem 0 005200 0 1 0 0 000000 000000 01
3 wmem 0 010317 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 005200 0 1 0 0 000000 000000 01
3 wmem 0 010447 0 1 0 0 000000 000000 01
3 wmem 0 005200 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 012717 0 1 0 0 000000 000000 01
3 wmem 0 000240 0 1 0 0 000000 000000 01
3 wmem 0 000111 0 1 0 0 000000 000000 01
3 wmem 0 012717 0 1 0 0 000000 000000 01
3 wmem 0 000240 0 1 0 0 000000 000000 01
3 wmem 0 000111 0 1 0 0 000000 000000 01
3 wmem 0 012717 0 1 0 0 000000 000000 01
3 wmem 0 000240 0 1 0 0 000000 000000 01
3 wmem 0 000111 0 1 0 0 000000 000000 01
3 wmem 0 012717 0 1 0 0 000000 000000 01
3 wmem 0 000240 0 1 0 0 000000 000000 01
3 wmem 0 000111 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
3 wmem 0 000000 0 1 0 0 000000 000000 01
C Exec code 47 (pipeline torture tests)
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)):
2 wreg 0 000000 0 1 0 0 000000 000000 01
2 wreg 1 000000 0 1 0 0 000000 000000 01
2 wreg 2 000000 0 1 0 0 000000 000000 01
2 wreg 3 005201 0 1 0 0 005201 000000 01
2 wreg 4 005202 0 1 0 0 005202 000000 01
2 cres 0 000000 0 1 0 0 000000 000000 00
2 wreg 7 013402 0 1 0 0 013402 000000 00
2 sta 0 000000 0 1 0 0 000000 100000 07
46 ---- - ------ 0 0 0 0 000000 000000 01 WAIT GO OK
3 rreg 7 013434 0 1 0 0 013434 000000 01 CHECK OK
3 rreg 0 000003 0 1 0 0 000003 000000 01 CHECK OK
3 rreg 1 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rreg 2 000001 0 1 0 0 000001 000000 01 CHECK OK
3 rreg 3 005201 0 1 0 0 005201 000000 01 CHECK OK
3 rreg 4 005202 0 1 0 0 005202 000000 01 CHECK OK
3 rmem 0 177772 0 1 0 0 177772 000000 01 CHECK OK
3 rmem 0 016727 0 1 0 0 016727 000000 01 CHECK OK
3 rmem 0 177772 0 1 0 0 177772 000000 01 CHECK OK
3 rmem 0 000077 0 1 0 0 000077 000000 01 CHECK OK
3 rmem 0 016737 0 1 0 0 016737 000000 01 CHECK OK
3 rmem 0 177770 0 1 0 0 177770 000000 01 CHECK OK
3 rmem 0 013400 0 1 0 0 013400 000000 01 CHECK OK
3 rmem 0 005200 0 1 0 0 005200 000000 01 CHECK OK
3 rmem 0 010317 0 1 0 0 010317 000000 01 CHECK OK
3 rmem 0 005201 0 1 0 0 005201 000000 01 CHECK OK
3 rmem 0 005200 0 1 0 0 005200 000000 01 CHECK OK
3 rmem 0 005202 0 1 0 0 005202 000000 01 CHECK OK
3 rmem 0 005200 0 1 0 0 005200 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70)
2 wreg 1 013474 0 1 0 0 013474 000000 01
2 cres 0 000000 0 1 0 0 005202 000000 00
2 wreg 7 013440 0 1 0 0 013440 000000 00
2 sta 0 000000 0 1 0 0 005202 100000 07
49 ---- - ------ 0 0 0 0 005202 000000 01 WAIT GO OK
3 rreg 7 013472 0 1 0 0 013472 000000 01 CHECK OK
3 rmem 0 012717 0 1 0 0 012717 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 012717 0 1 0 0 012717 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 012717 0 1 0 0 012717 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 012717 0 1 0 0 012717 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 000240 0 1 0 0 000240 000000 01 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 01 CHECK OK
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10)
3 wmem 0 000007 0 1 0 0 013472 000000 01
3 wmem 0 000010 0 1 0 0 013472 000000 01
3 wmem 0 000077 0 1 0 0 013472 000000 01
3 wmem 0 000210 0 1 0 0 013472 000000 01
3 wmem 0 000227 0 1 0 0 013472 000000 01
3 wmem 0 007000 0 1 0 0 013472 000000 01
3 wmem 0 007777 0 1 0 0 013472 000000 01
3 wmem 0 075000 0 1 0 0 013472 000000 01
3 wmem 0 076777 0 1 0 0 013472 000000 01
3 wmem 0 106400 0 1 0 0 013472 000000 01
3 wmem 0 106477 0 1 0 0 013472 000000 01
3 wmem 0 106700 0 1 0 0 013472 000000 01
3 wmem 0 106777 0 1 0 0 013472 000000 01
3 wmem 0 107000 0 1 0 0 013472 000000 01
3 wmem 0 107777 0 1 0 0 013472 000000 01
3 wmem 0 170000 0 1 0 0 013472 000000 01
3 wmem 0 177777 0 1 0 0 013472 000000 01
C Exec code 50 (check that all reserved instructions trap to 10)
C Test odd address abort
2 cres 0 000000 0 1 0 0 013472 000000 00
2 wpsw 0 000000 0 1 0 0 000000 000000 00
3 wmem 0 000000 0 1 0 0 013472 000000 00
3 wmem 0 000000 0 1 0 0 013472 000000 00
2 wreg 6 001400 0 1 0 0 001400 000000 00
2 wreg 7 013500 0 1 0 0 013500 000000 00
17 step 0 000000 0 0 0 0 013472 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013502 0 1 0 0 013502 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013504 0 1 0 0 013504 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013506 0 1 0 0 013506 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013510 0 1 0 0 013510 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013512 0 1 0 0 013512 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013514 0 1 0 0 013514 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013516 0 1 0 0 013516 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013520 0 1 0 0 013520 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013522 0 1 0 0 013522 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013524 0 1 0 0 013524 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013526 0 1 0 0 013526 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013530 0 1 0 0 013530 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013532 0 1 0 0 013532 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013534 0 1 0 0 013534 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013536 0 1 0 0 013536 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
2 wreg 6 001400 0 1 0 0 001400 000000 04
2 wreg 7 013540 0 1 0 0 013540 000000 04
17 step 0 000000 0 0 0 0 001374 000000 04 WAIT STEP OK
3 rreg 7 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rreg 6 001374 0 1 0 0 001374 000000 04 CHECK OK
C Verify trap catchers integrity
3 rmem 0 000006 0 1 0 0 000006 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000012 0 1 0 0 000012 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000016 0 1 0 0 000016 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000022 0 1 0 0 000022 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000026 0 1 0 0 000026 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000032 0 1 0 0 000032 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000036 0 1 0 0 000036 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000242 0 1 0 0 000242 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000246 0 1 0 0 000246 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
3 rmem 0 000252 0 1 0 0 000252 000000 04 CHECK OK
3 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
C Verify setup MMU
5 rmem 0 000000 0 1 0 0 000000 000000 04 CHECK OK
5 rmem 0 000200 0 1 0 0 000200 000000 04 CHECK OK
5 rmem 0 000400 0 1 0 0 000400 000000 04 CHECK OK
5 rmem 0 000600 0 1 0 0 000600 000000 04 CHECK OK
5 rmem 0 001000 0 1 0 0 001000 000000 04 CHECK OK
5 rmem 0 001200 0 1 0 0 001200 000000 04 CHECK OK
5 rmem 0 001400 0 1 0 0 001400 000000 04 CHECK OK
5 rmem 0 177600 0 1 0 0 177600 000000 04 CHECK OK
5 wmem 0 000000 0 1 0 0 001374 000000 04
5 wmem 0 000200 0 1 0 0 001374 000000 04
5 wmem 0 000400 0 1 0 0 001374 000000 04
5 wmem 0 000600 0 1 0 0 001374 000000 04
5 wmem 0 001000 0 1 0 0 001374 000000 04
5 wmem 0 001200 0 1 0 0 001374 000000 04
5 wmem 0 001400 0 1 0 0 001374 000000 04
5 wmem 0 177600 0 1 0 0 001374 000000 04
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
5 rmem 0 077406 0 1 0 0 077406 000000 04 CHECK OK
1225355.0 ns 61258: DONE
real 0m7.026s user 0m7.024s sys 0m0.000s