if_dmc.h

Macros

DMCMTU            X
DMC_BACCI         X
DMC_BACCO         X
DMC_BASEI         X
DMC_CCOUNT        X
DMC_CNTLI         X
DMC_CNTLO         X
DMC_CNTMASK       X
DMC_FATAL         X
DMC_HDPLX         X
DMC_IEI           X
DMC_IEO           X
DMC_MAINT         X
DMC_MCLR          X
DMC_OUR           X
DMC_OUX           X
DMC_PERR          X
DMC_RDYI          X
DMC_RDYO          X
DMC_READ          X
DMC_RESUME        X
DMC_RQI           X
DMC_RUN           X
DMC_SEC           X
DMC_WRITE         X
DMC_XMEM          X
RDYSCAN           X
bsel0             X
bsel1             X
bsel2             X
bsel3             X
bsel4             X
bsel5             X
bsel6             X
bsel7             X
sel0              X
sel2              X
sel4              X
sel6              X

struct's

dmcdevice         X

   1: /*
   2:  * Copyright (c) 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)if_dmc.h	1.1 (2.10BSD Berkeley) 12/1/86
   7:  */
   8: 
   9: /*
  10:  * DMC-11 Interface
  11:  */
  12: 
  13: struct dmcdevice {
  14:     union {
  15:         char    b[8];
  16:         short   w[4];
  17:     } un;
  18: };
  19: 
  20: #define bsel0   un.b[0]
  21: #define bsel1   un.b[1]
  22: #define bsel2   un.b[2]
  23: #define bsel3   un.b[3]
  24: #define bsel4   un.b[4]
  25: #define bsel5   un.b[5]
  26: #define bsel6   un.b[6]
  27: #define bsel7   un.b[7]
  28: #define sel0    un.w[0]
  29: #define sel2    un.w[1]
  30: #define sel4    un.w[2]
  31: #define sel6    un.w[3]
  32: 
  33: #define DMCMTU  (2048)
  34: 
  35: #define RDYSCAN 16  /* loop delay for RDYI after RQI */
  36: 
  37: /* defines for bsel0 */
  38: #define DMC_BACCI   0
  39: #define DMC_CNTLI   1
  40: #define DMC_PERR    2
  41: #define DMC_BASEI   3
  42: #define DMC_WRITE   0       /* transmit block */
  43: #define DMC_READ    4       /* read block */
  44: #define DMC_RQI     0040        /* port request bit */
  45: #define DMC_IEI     0100        /* enable input interrupts */
  46: #define DMC_RDYI    0200        /* port ready */
  47: 
  48: /* defines for bsel1 */
  49: #define DMC_MCLR    0100        /* DMC11 Master Clear */
  50: #define DMC_RUN     0200        /* clock running */
  51: 
  52: /* defines for bsel2 */
  53: #define DMC_BACCO   0
  54: #define DMC_CNTLO   1
  55: #define DMC_OUX     0       /* transmit block */
  56: #define DMC_OUR     4       /* read block */
  57: #define DMC_IEO     0100        /* enable output interrupts */
  58: #define DMC_RDYO    0200        /* port available */
  59: 
  60: /* defines for CNTLI mode */
  61: #define DMC_HDPLX   02000       /* half duplex DDCMP operation */
  62: #define DMC_SEC     04000       /* half duplex secondary station */
  63: #define DMC_MAINT   00400       /* enter maintenance mode */
  64: 
  65: /* defines for BACCI/O and BASEI mode */
  66: #define DMC_XMEM    0140000     /* xmem bit position */
  67: #define DMC_CCOUNT  0037777     /* character count mask */
  68: #define DMC_RESUME  0002000     /* resume (BASEI only) */
  69: 
  70: /* defines for CNTLO */
  71: #define DMC_CNTMASK 01777
  72: #define DMC_FATAL   01620