1: / 2000/04/06 - make 'nofault' global so toyset.o can use it 2: / 1995/06/04 - devsw[] entries are 14. bytes, need a tape seek routine entry. 3: / 1995/06/02 - Modifications for split I/D to work. The vectors need to be 4: / in 'data' space. 5: / 1995/06/01 - Make copy of SSR3 so we can tell if split I/D is enabled. 6: / 1995/05/30 - devsw[] entries are 12. bytes now. 7: / 8: / Startup code for standalone utilities 9: / sms - mods to pass boot device and csr on to program 10: / 11: / Note that the bootstrap passes the cputype through in r0. 12: 13: PS = 177776 14: SSR3 = 172516 15: 16: .globl _main, __rtt, _devsw, _ADJcsr 17: 18: #ifdef SPLIT_ID 19: .data 20: #else 21: .text 22: #endif 23: ZERO: 24: jmp start 25: 26: / 27: / trap vectors 28: / 29: trap;340 / 004 - bus error 30: trap;341 / 010 - illegal instruction 31: trap;342 / 014 - BPT 32: trap;343 / 020 - IOT 33: trap;344 / 024 - POWER FAIL 34: trap;345 / 030 - EMT 35: start;346 / 034 - TRAP 36: .= ZERO + 400 37: .text 38: 39: start: 40: mov $340,*$PS 41: mov $trap,*$034 42: 43: / Save information which Boot has passed thru to us 44: 45: mov r0,_cputype / assume that the boot left this in r0 46: mov r1,_bootcsr / assume that boot left csr in r1 47: mov r3,_bootdev / and boot device major,minor in r3 48: 49: / Make a copy of SSR3. If this register does not exist it is probably better 50: / to trap now rather than later - the absence of this register means no split 51: / I/D space and the kernel won't run. 52: 53: mov *$SSR3,_ssr3copy 54: 55: mov $157772,sp / return address,psw at 157774&6 56: 57: / controller number is in bits 6&7 of r3 (_bootdev). major device number 58: / is in bits 8-15. what we need to do now is place the csr into 59: / the appropriate driver's csrlist which is indexed by controller number. 60: 61: ash $-5,r3 / r3 = controller# * 2 62: mov r3,r0 / controller number in bits 1,2 63: bic $!6,r0 / make a word index 64: ash $-3,r3 / major device # to bits 0-7 65: mov r3,r2 / save major for later 66: mul $14.,r3 / devsw[] members are 14. bytes each 67: mov _devsw+10(r3),r3 / get csrlist for driver 68: add r0,r3 / point to controller's entry 69: asr r0 / controller number in bits 0,1 70: mov r0,_bootctlr / set default controller number 71: 72: / the CSR passed from the ROMs is not necessarily the first address 73: / of a device! We therefore have to adjust the CSR so that the structure 74: / pointers in the drivers are origined at the base address rather than 75: / the ROM supplied address. The adjustment was not stored in devsw[] to 76: / save space (can get by with an array of bytes instead of words). 77: 78: movb _ADJcsr(r2),r2 / adjust (possibly) the CSR 79: mov _bootcsr,r1 80: sub r2,r1 81: 82: mov r1,(r3) / store controller's csr in table 83: jsr pc,_main 84: 85: / fix up stack to point at trap ps-pc pair located at top of memory 86: / so we can return to the bootstrap. 87: / 88: / the return protocol originally changed from 140000 because icheck was 89: / too large. icheck was reduced in size but the 157774 return protocol 90: / was retained to allow for slightly oversized programs. 91: 92: __rtt: 93: mov $157774,sp 94: rtt / we hope! 95: br . 96: 97: 98: .globl _trap 99: trap: 100: mov *$PS,-(sp) 101: tst nofault 102: bne 3f 103: mov r0,-(sp) 104: mov r1,-(sp) 105: 2: jsr pc,_trap 106: mov (sp)+,r1 107: mov (sp)+,r0 108: tst (sp)+ 109: rtt 110: 3: tst (sp)+ 111: mov nofault,(sp) 112: rtt 113: 114: .data 115: .globl nofault, _cputype, _bootcsr, _bootdev, _ssr3copy, _bootctlr 116: 117: nofault: .=.+2 / where to go on predicted trap 118: _cputype: .=.+2 / cpu type (currently 44, 70, 73) 119: _bootdev: .=.+2 / makedev(major,unit) for boot device 120: _bootcsr: .=.+2 / csr of boot controller 121: _bootctlr: .=.+2 / number of boot controller (bits 6 and 7 of minor) 122: _ssr3copy: .=.+2 / copy of SSR3