2.11BSD#431 - /usr/src/sys/pdpuba/dhureg.h

   1: /*
   2:  * Copyright (c) 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)dhureg.h	1.2 (2.11BSD) 1997/5/9
   7:  */
   8: 
   9: /*
  10:  * DHU-11 device register definitions.
  11:  */
  12: struct dhudevice {
  13:     union {
  14:         u_short csr;        /* control-status register */
  15:         struct {
  16:             char    csrl;   /* low byte for line select */
  17:             char    csrh;   /* high byte for tx line */
  18:         } cb;
  19:     } un1;
  20: #define dhucsr  un1.csr
  21: #define dhucsrl un1.cb.csrl
  22: #define dhucsrh un1.cb.csrh
  23:     union {
  24:         u_short rbuf;       /* recv.char/ds.change register (R) */
  25:         u_short timo;       /* delay between recv -> intr (W) */
  26:     } un2;
  27: #define dhurbuf un2.rbuf
  28: #define dhutimo un2.timo
  29:     u_short dhulpr;         /* line parameter register */
  30:     union {
  31:         char    fbyte[1];   /* fifo data byte (low byte only) (W) */
  32:         u_short fdata;      /* fifo data word (W) */
  33:         char    sbyte[2];   /* line status/fifo size (R) */
  34:     } un3;
  35: #define dhubyte un3.fbyte[0]
  36: #define dhufifo un3.fdata
  37: #define dhusize un3.sbyte[0]
  38: #define dhustat un3.sbyte[1]
  39:     u_short dhulcr;         /* line control register */
  40:     u_short dhubar1;        /* buffer address register 1 */
  41:     char    dhubar2;        /* buffer address register 2 */
  42:     char    dhulcr2;        /* xmit enable bit */
  43:     short   dhubcr;         /* buffer count register */
  44: };
  45: 
  46: /* Bits in dhucsr */
  47: #define DHU_CS_TIE  0x4000      /* transmit interrupt enable */
  48: #define DHU_CS_DFAIL    0x2000      /* diagnostic fail */
  49: #define DHU_CS_RI   0x0080      /* receiver interrupt */
  50: #define DHU_CS_RIE  0x0040      /* receiver interrupt enable */
  51: #define DHU_CS_MCLR 0x0020      /* master clear */
  52: #define DHU_CS_SST  0x0010      /* skip self test (with DHU_CS_MCLR) */
  53: #define DHU_CS_IAP  0x000f      /* indirect address pointer */
  54: 
  55: #define DHU_IE  (DHU_CS_TIE|DHU_CS_RIE)
  56: 
  57: /* map unit into iap register select */
  58: #define DHU_SELECT(unit)    ((unit) & DHU_CS_IAP)
  59: 
  60: /* Transmitter bits in high byte of dhucsr */
  61: #define DHU_CSH_TI  0x80        /* transmit interrupt */
  62: #define DHU_CSH_NXM 0x10        /* transmit dma err: non-exist-mem */
  63: #define DHU_CSH_TLN 0x0f        /* transmit line number */
  64: 
  65: /* map csrh line bits into line */
  66: #define DHU_TX_LINE(csrh)   ((csrh) & DHU_CSH_TLN)
  67: 
  68: /* Bits in dhurbuf */
  69: #define DHU_RB_VALID    0x8000      /* data valid */
  70: #define DHU_RB_STAT 0x7000      /* status bits */
  71: #define DHU_RB_DO   0x4000      /* data overrun */
  72: #define DHU_RB_FE   0x2000      /* framing error */
  73: #define DHU_RB_PE   0x1000      /* parity error */
  74: #define DHU_RB_RLN  0x0f00      /* receive line number */
  75: #define DHU_RB_RDS  0x00ff      /* receive data/status */
  76: #define DHU_RB_DIAG 0x0001      /* if DHU_RB_STAT -> diag vs modem */
  77: 
  78: /* map rbuf line bits into line */
  79: #define DHU_RX_LINE(rbuf)   (((rbuf) & DHU_RB_RLN) >> 8)
  80: 
  81: /* Bits in dhulpr */
  82: #define DHU_LP_TSPEED   0xf000
  83: #define DHU_LP_RSPEED   0x0f00
  84: #define DHU_LP_TWOSB    0x0080
  85: #define DHU_LP_EPAR 0x0040
  86: #define DHU_LP_PENABLE  0x0020
  87: #define DHU_LP_BITS8    0x0018
  88: #define DHU_LP_BITS7    0x0010
  89: #define DHU_LP_BITS6    0x0008
  90: 
  91: /* Bits in dhustat */
  92: #define DHU_ST_DSR  0x80        /* data set ready */
  93: #define DHU_ST_RI   0x20        /* ring indicator */
  94: #define DHU_ST_DCD  0x10        /* carrier detect */
  95: #define DHU_ST_CTS  0x08        /* clear to send */
  96: #define DHU_ST_DHU  0x01        /* always one on a dhu, zero on dhv */
  97: 
  98: /* Bits in dhulcr */
  99: #define DHU_LC_RTS  0x1000      /* request to send */
 100: #define DHU_LC_DTR  0x0200      /* data terminal ready */
 101: #define DHU_LC_MODEM    0x0100      /* modem control enable */
 102: #define DHU_LC_MAINT    0x00c0      /* maintenance mode */
 103: #define DHU_LC_FXOFF    0x0020      /* force xoff */
 104: #define DHU_LC_OAUTOF   0x0010      /* output auto flow */
 105: #define DHU_LC_BREAK    0x0008      /* break control */
 106: #define DHU_LC_RXEN 0x0004      /* receiver enable */
 107: #define DHU_LC_IAUTOF   0x0002      /* input auto flow */
 108: #define DHU_LC_TXABORT  0x0001      /* transmitter abort */
 109: 
 110: /* Bits in dhulcr2 */
 111: #define DHU_LC2_TXEN    0x80        /* transmitter enable */
 112: 
 113: /* Bits in dhubar2 */
 114: #define DHU_BA2_DMAGO   0x80        /* transmit dma start */
 115: #define DHU_BA2_XBA 0x03        /* top two bits of dma address */
 116: #define DHU_XBA_SHIFT   16      /* amount to shift xba bits */
 117: 
 118: /* Bits for dhumctl only:  stat bits are shifted up 16 */
 119: #define DHU_ON  (DHU_LC_DTR|DHU_LC_RTS|DHU_LC_MODEM)
 120: #define DHU_OFF DHU_LC_MODEM
 121: 
 122: #define DHU_DSR ((long)DHU_ST_DSR << 16)
 123: #define DHU_RNG ((long)DHU_ST_RI << 16)
 124: #define DHU_CAR ((long)DHU_ST_DCD << 16)
 125: #define DHU_CTS ((long)DHU_ST_CTS << 16)
 126: 
 127: #define DHU_RTS DHU_LC_RTS
 128: #define DHU_DTR DHU_LC_DTR
 129: #define DHU_BRK DHU_LC_BREAK
 130: #define DHU_LE  DHU_LC_MODEM

Defined struct's

Defined macros

Usage of this include