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W11 CPU core and support modules
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arty_dram_dummy.vhd
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1
-- $Id: arty_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2
-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: arty_dram_dummy - syn
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-- Description: arty target (base; serport loopback, dram project)
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--
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-- Dependencies: -
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-- To test: tb_arty_dram
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-- Target Devices: generic
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-- Tool versions: viv 2017.2; ghdl 0.34
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--
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-- Revision History:
15
-- Date Rev Version Comment
16
-- 2018-10-28 1063 1.0 Initial version (derived from arty_dummy)
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------------------------------------------------------------------------------
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19
library
ieee
;
20
use
ieee.std_logic_1164.
all
;
21
22
use
work.
slvtypes
.
all
;
23
24
entity
arty_dram_dummy
is
-- ARTY dummy (base+dram)
25
-- implements arty_dram_aif
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port
(
27
I_CLK100
:
in
slbit
;
-- 100 MHz board clock
28
I_RXD
:
in
slbit
;
-- receive data (board view)
29
O_TXD
:
out
slbit
;
-- transmit data (board view)
30
I_SWI
:
in
slv4
;
-- arty switches
31
I_BTN
:
in
slv4
;
-- arty buttons
32
O_LED
:
out
slv4
;
-- arty leds
33
O_RGBLED0
:
out
slv3
;
-- arty rgb-led 0
34
O_RGBLED1
:
out
slv3
;
-- arty rgb-led 1
35
O_RGBLED2
:
out
slv3
;
-- arty rgb-led 2
36
O_RGBLED3
:
out
slv3
;
-- arty rgb-led 3
37
A_VPWRN
:
in
slv4
;
-- arty pwrmon (neg)
38
A_VPWRP
:
in
slv4
;
-- arty pwrmon (pos)
39
DDR3_DQ
:
inout
slv16
;
-- dram: data in/out
40
DDR3_DQS_P
:
inout
slv2
;
-- dram: data strobe (diff-p)
41
DDR3_DQS_N
:
inout
slv2
;
-- dram: data strobe (diff-n)
42
DDR3_ADDR
:
out
slv14
;
-- dram: address
43
DDR3_BA
:
out
slv3
;
-- dram: bank address
44
DDR3_RAS_N
:
out
slbit
;
-- dram: row addr strobe (act.low)
45
DDR3_CAS_N
:
out
slbit
;
-- dram: column addr strobe (act.low)
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DDR3_WE_N
:
out
slbit
;
-- dram: write enable (act.low)
47
DDR3_RESET_N
:
out
slbit
;
-- dram: reset (act.low)
48
DDR3_CK_P
:
out
slv1
;
-- dram: clock (diff-p)
49
DDR3_CK_N
:
out
slv1
;
-- dram: clock (diff-n)
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DDR3_CKE
:
out
slv1
;
-- dram: clock enable
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DDR3_CS_N
:
out
slv1
;
-- dram: chip select (act.low)
52
DDR3_DM
:
out
slv2
;
-- dram: data input mask
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DDR3_ODT
:
out
slv1
-- dram: on-die termination
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)
;
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end
arty_dram_dummy
;
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architecture
syn
of
arty_dram_dummy
is
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begin
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O_TXD
<=
I_RXD
;
-- loop back serport
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O_LED
<=
I_SWI
;
-- mirror SWI on LED
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O_RGBLED0
<=
I_BTN
(
2
downto
0
)
;
-- mirror BTN on RGBLED0
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O_RGBLED1
<=
(
others
=
>
'
0
'
)
;
67
O_RGBLED2
<=
(
others
=
>
'
0
'
)
;
68
O_RGBLED3
<=
(
others
=
>
'
0
'
)
;
69
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DDR3_DQ
<=
(
others
=
>
'
Z
'
)
;
71
DDR3_DQS_P
<=
(
others
=
>
'
Z
'
)
;
72
DDR3_DQS_N
<=
(
others
=
>
'
Z
'
)
;
73
DDR3_ADDR
<=
(
others
=
>
'
0
'
)
;
74
DDR3_BA
<=
(
others
=
>
'
0
'
)
;
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DDR3_RAS_N
<=
'
1
'
;
76
DDR3_CAS_N
<=
'
1
'
;
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DDR3_WE_N
<=
'
1
'
;
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DDR3_RESET_N
<=
'
1
'
;
79
DDR3_CK_P
<=
(
others
=
>
'
0
'
)
;
80
DDR3_CK_N
<=
(
others
=
>
'
1
'
)
;
81
DDR3_CKE
<=
(
others
=
>
'
0
'
)
;
82
DDR3_CS_N
<=
(
others
=
>
'
1
'
)
;
83
DDR3_DM
<=
(
others
=
>
'
0
'
)
;
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DDR3_ODT
<=
(
others
=
>
'
0
'
)
;
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end
syn
;
arty_dram_dummy.syn
Definition:
arty_dram_dummy.vhd:57
arty_dram_dummy
Definition:
arty_dram_dummy.vhd:24
arty_dram_dummy.DDR3_CK_P
out DDR3_CK_P slv1
Definition:
arty_dram_dummy.vhd:48
arty_dram_dummy.I_SWI
in I_SWI slv4
Definition:
arty_dram_dummy.vhd:30
arty_dram_dummy.DDR3_DM
out DDR3_DM slv2
Definition:
arty_dram_dummy.vhd:52
arty_dram_dummy.O_TXD
out O_TXD slbit
Definition:
arty_dram_dummy.vhd:29
arty_dram_dummy.I_RXD
in I_RXD slbit
Definition:
arty_dram_dummy.vhd:28
arty_dram_dummy.A_VPWRN
in A_VPWRN slv4
Definition:
arty_dram_dummy.vhd:37
arty_dram_dummy.A_VPWRP
in A_VPWRP slv4
Definition:
arty_dram_dummy.vhd:38
arty_dram_dummy.DDR3_RESET_N
out DDR3_RESET_N slbit
Definition:
arty_dram_dummy.vhd:47
arty_dram_dummy.DDR3_BA
out DDR3_BA slv3
Definition:
arty_dram_dummy.vhd:43
arty_dram_dummy.DDR3_DQ
inout DDR3_DQ slv16
Definition:
arty_dram_dummy.vhd:39
arty_dram_dummy.I_BTN
in I_BTN slv4
Definition:
arty_dram_dummy.vhd:31
arty_dram_dummy.O_RGBLED3
out O_RGBLED3 slv3
Definition:
arty_dram_dummy.vhd:36
arty_dram_dummy.DDR3_WE_N
out DDR3_WE_N slbit
Definition:
arty_dram_dummy.vhd:46
arty_dram_dummy.DDR3_CKE
out DDR3_CKE slv1
Definition:
arty_dram_dummy.vhd:50
arty_dram_dummy.DDR3_ADDR
out DDR3_ADDR slv14
Definition:
arty_dram_dummy.vhd:42
arty_dram_dummy.DDR3_ODT
out DDR3_ODT slv1
Definition:
arty_dram_dummy.vhd:54
arty_dram_dummy.DDR3_CAS_N
out DDR3_CAS_N slbit
Definition:
arty_dram_dummy.vhd:45
arty_dram_dummy.DDR3_CK_N
out DDR3_CK_N slv1
Definition:
arty_dram_dummy.vhd:49
arty_dram_dummy.DDR3_DQS_P
inout DDR3_DQS_P slv2
Definition:
arty_dram_dummy.vhd:40
arty_dram_dummy.O_RGBLED0
out O_RGBLED0 slv3
Definition:
arty_dram_dummy.vhd:33
arty_dram_dummy.I_CLK100
in I_CLK100 slbit
Definition:
arty_dram_dummy.vhd:27
arty_dram_dummy.O_RGBLED2
out O_RGBLED2 slv3
Definition:
arty_dram_dummy.vhd:35
arty_dram_dummy.DDR3_DQS_N
inout DDR3_DQS_N slv2
Definition:
arty_dram_dummy.vhd:41
arty_dram_dummy.DDR3_RAS_N
out DDR3_RAS_N slbit
Definition:
arty_dram_dummy.vhd:44
arty_dram_dummy.DDR3_CS_N
out DDR3_CS_N slv1
Definition:
arty_dram_dummy.vhd:51
arty_dram_dummy.O_RGBLED1
out O_RGBLED1 slv3
Definition:
arty_dram_dummy.vhd:34
arty_dram_dummy.O_LED
out O_LED slv4
Definition:
arty_dram_dummy.vhd:32
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv14
std_logic_vector( 13 downto 0) slv14
Definition:
slvtypes.vhd:46
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition:
slvtypes.vhd:36
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition:
slvtypes.vhd:35
slvtypes.slv1
std_logic_vector( 0 downto 0) slv1
Definition:
slvtypes.vhd:33
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition:
slvtypes.vhd:34
bplib
arty
tb
arty_dram_dummy.vhd
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