w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
artylib.vhd
Go to the documentation of this file.
1-- $Id: artylib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: artylib
7-- Description: Digilent Arty components
8--
9-- Dependencies: -
10-- Tool versions: viv 2015.4; ghdl 0.33
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2018-10-29 1063 1.2 add arty_dram_aif
15-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
16-- 2016-01-31 726 1.0 Initial version
17------------------------------------------------------------------------------
18
19library ieee;
20use ieee.std_logic_1164.all;
21
22use work.slvtypes.all;
23
24package artylib is
25
26component arty_aif is -- ARTY, abstract iface, base
27 port (
28 I_CLK100 : in slbit; -- 100 MHz clock
29 I_RXD : in slbit; -- receive data (board view)
30 O_TXD : out slbit; -- transmit data (board view)
31 I_SWI : in slv4; -- arty switches
32 I_BTN : in slv4; -- arty buttons
33 O_LED : out slv4; -- arty leds
34 O_RGBLED0 : out slv3; -- arty rgb-led 0
35 O_RGBLED1 : out slv3; -- arty rgb-led 1
36 O_RGBLED2 : out slv3; -- arty rgb-led 2
37 O_RGBLED3 : out slv3; -- arty rgb-led 3
38 A_VPWRN : in slv4; -- arty pwrmon (neg)
39 A_VPWRP : in slv4 -- arty pwrmon (pos)
40 );
41end component;
42
43component arty_dram_aif is -- ARTY, abstract iface, base+dram
44 port (
45 I_CLK100 : in slbit; -- 100 MHz clock
46 I_RXD : in slbit; -- receive data (board view)
47 O_TXD : out slbit; -- transmit data (board view)
48 I_SWI : in slv4; -- arty switches
49 I_BTN : in slv4; -- arty buttons
50 O_LED : out slv4; -- arty leds
51 O_RGBLED0 : out slv3; -- arty rgb-led 0
52 O_RGBLED1 : out slv3; -- arty rgb-led 1
53 O_RGBLED2 : out slv3; -- arty rgb-led 2
54 O_RGBLED3 : out slv3; -- arty rgb-led 3
55 A_VPWRN : in slv4; -- arty pwrmon (neg)
56 A_VPWRP : in slv4; -- arty pwrmon (pos)
57 DDR3_DQ : inout slv16; -- dram: data in/out
58 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
59 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
60 DDR3_ADDR : out slv14; -- dram: address
61 DDR3_BA : out slv3; -- dram: bank address
62 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
63 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
64 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
65 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
66 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
67 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
68 DDR3_CKE : out slv1; -- dram: clock enable
69 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
70 DDR3_DM : out slv2; -- dram: data input mask
71 DDR3_ODT : out slv1 -- dram: on-die termination
72 );
73end component;
74
75end package artylib;