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W11 CPU core and support modules
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artys7lib.vhd
Go to the documentation of this file.
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-- $Id: artys7lib.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Package Name: artys7lib
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-- Description: Digilent Arty S7 components
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--
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-- Dependencies: -
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-- Tool versions: viv 2017.2-2018.2; ghdl 0.34-0.35
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-01-12 1105 1.1 add artys7_dram_aif
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-- 2018-08-05 1028 1.0 Initial version
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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package
artys7lib
is
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component
artys7_aif
is
-- ARTY S7, abstract iface, base
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port
(
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I_CLK100 :
in
slbit;
-- 100 MHz clock
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I_RXD :
in
slbit;
-- receive data (board view)
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O_TXD :
out
slbit;
-- transmit data (board view)
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I_SWI :
in
slv4;
-- artys7 switches
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I_BTN :
in
slv4;
-- artys7 buttons
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O_LED :
out
slv4;
-- artys7 leds
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O_RGBLED0 :
out
slv3;
-- artys7 rgb-led 0
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O_RGBLED1 :
out
slv3
-- artys7 rgb-led 1
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);
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end
component
;
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component
artys7_dram_aif
is
-- ARTY S7, abstract iface, base+dram
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port
(
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I_CLK100 :
in
slbit;
-- 100 MHz clock
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I_RXD :
in
slbit;
-- receive data (board view)
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O_TXD :
out
slbit;
-- transmit data (board view)
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I_SWI :
in
slv4;
-- artys7 switches
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I_BTN :
in
slv4;
-- artys7 buttons
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O_LED :
out
slv4;
-- artys7 leds
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O_RGBLED0 :
out
slv3;
-- artys7 rgb-led 0
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O_RGBLED1 :
out
slv3;
-- artys7 rgb-led 1
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DDR3_DQ :
inout
slv16;
-- dram: data in/out
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DDR3_DQS_P :
inout
slv2;
-- dram: data strobe (diff-p)
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DDR3_DQS_N :
inout
slv2;
-- dram: data strobe (diff-n)
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DDR3_ADDR :
out
slv14;
-- dram: address
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DDR3_BA :
out
slv3;
-- dram: bank address
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DDR3_RAS_N :
out
slbit;
-- dram: row addr strobe (act.low)
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DDR3_CAS_N :
out
slbit;
-- dram: column addr strobe (act.low)
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DDR3_WE_N :
out
slbit;
-- dram: write enable (act.low)
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DDR3_RESET_N :
out
slbit;
-- dram: reset (act.low)
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DDR3_CK_P :
out
slv1;
-- dram: clock (diff-p)
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DDR3_CK_N :
out
slv1;
-- dram: clock (diff-n)
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DDR3_CKE :
out
slv1;
-- dram: clock enable
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DDR3_CS_N :
out
slv1;
-- dram: chip select (act.low)
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DDR3_DM :
out
slv2;
-- dram: data input mask
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DDR3_ODT :
out
slv1
-- dram: on-die termination
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);
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end
component
;
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end
package
artys7lib
;
artys7lib
Definition:
artys7lib.vhd:23
slvtypes
Definition:
slvtypes.vhd:28
bplib
artys7
artys7lib.vhd
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