w11 - vhd 0.794
W11 CPU core and support modules
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artys7lib.vhd
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1-- $Id: artys7lib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: artys7lib
7-- Description: Digilent Arty S7 components
8--
9-- Dependencies: -
10-- Tool versions: viv 2017.2-2018.2; ghdl 0.34-0.35
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2019-01-12 1105 1.1 add artys7_dram_aif
15-- 2018-08-05 1028 1.0 Initial version
16------------------------------------------------------------------------------
17
18library ieee;
19use ieee.std_logic_1164.all;
20
21use work.slvtypes.all;
22
23package artys7lib is
24
25component artys7_aif is -- ARTY S7, abstract iface, base
26 port (
27 I_CLK100 : in slbit; -- 100 MHz clock
28 I_RXD : in slbit; -- receive data (board view)
29 O_TXD : out slbit; -- transmit data (board view)
30 I_SWI : in slv4; -- artys7 switches
31 I_BTN : in slv4; -- artys7 buttons
32 O_LED : out slv4; -- artys7 leds
33 O_RGBLED0 : out slv3; -- artys7 rgb-led 0
34 O_RGBLED1 : out slv3 -- artys7 rgb-led 1
35 );
36end component;
37
38component artys7_dram_aif is -- ARTY S7, abstract iface, base+dram
39 port (
40 I_CLK100 : in slbit; -- 100 MHz clock
41 I_RXD : in slbit; -- receive data (board view)
42 O_TXD : out slbit; -- transmit data (board view)
43 I_SWI : in slv4; -- artys7 switches
44 I_BTN : in slv4; -- artys7 buttons
45 O_LED : out slv4; -- artys7 leds
46 O_RGBLED0 : out slv3; -- artys7 rgb-led 0
47 O_RGBLED1 : out slv3; -- artys7 rgb-led 1
48 DDR3_DQ : inout slv16; -- dram: data in/out
49 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
50 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
51 DDR3_ADDR : out slv14; -- dram: address
52 DDR3_BA : out slv3; -- dram: bank address
53 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
54 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
55 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
56 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
57 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
58 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
59 DDR3_CKE : out slv1; -- dram: clock enable
60 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
61 DDR3_DM : out slv2; -- dram: data input mask
62 DDR3_ODT : out slv1 -- dram: on-die termination
63 );
64end component;
65
66end package artys7lib;