w11 - vhd 0.794
W11 CPU core and support modules
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byte2cdata.vhd
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1-- $Id: byte2cdata.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: byte2cdata - syn
7-- Description: Byte stream to 9 bit comma,data converter
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2014-10-17 596 2.0 re-write, commas now 2 byte sequences
17-- 2011-11-19 427 1.0.2 now numeric_std clean
18-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
19-- 2007-08-27 76 1.0 Initial version
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24use ieee.numeric_std.all;
25
26use work.slvtypes.all;
27use work.comlib.all;
28
29entity byte2cdata is -- byte stream -> 9bit comma,data
30 port (
31 CLK : in slbit; -- clock
32 RESET : in slbit; -- reset
33 DI : in slv8; -- input data
34 ENA : in slbit; -- input data enable
35 ERR : in slbit; -- input data error
36 BUSY : out slbit; -- input data busy
37 DO : out slv9; -- output data; bit 8 = comma flag
38 VAL : out slbit; -- output data valid
39 HOLD : in slbit -- output data hold
40 );
41end byte2cdata;
42
43
44architecture syn of byte2cdata is
45
46 type regs_type is record
47 data : slv9; -- data
48 dataval : slbit; -- data valid
49 edpend : slbit; -- edata pending
50 end record regs_type;
51
52 constant regs_init : regs_type := (
53 (others=>'0'), -- data
54 '0','0' -- dataval,edpend
55 );
56
57 signal R_REGS : regs_type := regs_init; -- state registers
58 signal N_REGS : regs_type := regs_init; -- next value state regs
59
60begin
61
62 proc_regs: process (CLK)
63 begin
64
65 if rising_edge(CLK) then
66 if RESET = '1' then
68 else
69 R_REGS <= N_REGS;
70 end if;
71 end if;
72
73 end process proc_regs;
74
75 proc_next: process (R_REGS, DI, ENA, ERR, HOLD)
76
77 variable r : regs_type := regs_init;
78 variable n : regs_type := regs_init;
79
80 variable idata : slv9 := (others=>'0');
81 variable iesc : slbit := '0';
82 variable ibusy : slbit := '0';
83
84 begin
85
86 r := R_REGS;
87 n := R_REGS;
88
89 -- data path logic
90 idata := '1' & "00000" & "100"; -- clobber
91 iesc := '0';
92
93 if r.edpend = '1' then
94 if DI(c_cdata_edf_pref) = c_cdata_ed_pref and
95 (not DI(c_cdata_edf_eci)) = DI(c_cdata_edf_ec) then
96 case DI(c_cdata_edf_ec) is
97 when c_cdata_ec_xon =>
98 idata := '0' & c_cdata_xon;
99 when c_cdata_ec_xoff =>
100 idata := '0' & c_cdata_xoff;
101 when c_cdata_ec_fill =>
102 idata := '0' & c_cdata_fill;
103 when c_cdata_ec_esc =>
104 idata := '0' & c_cdata_escape;
105 when others =>
106 idata := '1' & "00000" & DI(c_cdata_edf_ec);
107 end case;
108 end if;
109 else
110 idata := '0' & DI;
111 if DI = c_cdata_escape then
112 iesc := '1';
113 end if;
114 end if;
115
116 -- control path logic
117 ibusy := '1';
118 if HOLD = '0' then
119 ibusy := '0';
120 n.dataval := '0';
121 n.data := idata;
122 if ENA = '1' then
123 if r.edpend = '0' then
124 if iesc = '0' then
125 n.dataval := '1';
126 else
127 n.edpend := '1';
128 end if;
129 else
130 n.dataval := '1';
131 n.edpend := '0';
132 end if;
133 elsif ERR = '1' then
134 n.dataval := '1';
135 end if;
136 end if;
137
138 N_REGS <= n;
139
140 DO <= r.data;
141 VAL <= r.dataval;
142 BUSY <= ibusy;
143
144 end process proc_next;
145
146
147end syn;
regs_type := regs_init N_REGS
Definition: byte2cdata.vhd:58
regs_type :=(( others => '0'), '0', '0') regs_init
Definition: byte2cdata.vhd:52
regs_type := regs_init R_REGS
Definition: byte2cdata.vhd:57
in RESET slbit
Definition: byte2cdata.vhd:32
in ENA slbit
Definition: byte2cdata.vhd:34
out DO slv9
Definition: byte2cdata.vhd:37
out BUSY slbit
Definition: byte2cdata.vhd:36
in HOLD slbit
Definition: byte2cdata.vhd:40
in ERR slbit
Definition: byte2cdata.vhd:35
in CLK slbit
Definition: byte2cdata.vhd:31
in DI slv8
Definition: byte2cdata.vhd:33
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40