23use ieee.std_logic_1164.
all;
24use ieee.numeric_std.
all;
62 proc_regs:
process (
CLK)
65 if rising_edge(CLK) then
73 end process proc_regs;
80 variable idata : slv9 := (others=>'0');
81 variable iesc : slbit := '0';
82 variable ibusy : slbit := '0';
90 idata := '1' & "00000" & "100";
93 if r.edpend = '1' then
94 if DI(c_cdata_edf_pref) = c_cdata_ed_pref and
95 (not DI(c_cdata_edf_eci)) = DI(c_cdata_edf_ec) then
96 case DI(c_cdata_edf_ec) is
97 when c_cdata_ec_xon =>
98 idata := '0' & c_cdata_xon;
99 when c_cdata_ec_xoff =>
100 idata := '0' & c_cdata_xoff;
101 when c_cdata_ec_fill =>
102 idata := '0' & c_cdata_fill;
103 when c_cdata_ec_esc =>
104 idata := '0' & c_cdata_escape;
106 idata := '1' & "00000" & DI(c_cdata_edf_ec);
111 if DI = c_cdata_escape then
123 if r.edpend = '0' then
144 end process proc_next;
regs_type := regs_init N_REGS
regs_type :=(( others => '0'), '0', '0') regs_init
regs_type := regs_init R_REGS
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 7 downto 0) slv8