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W11 CPU core and support modules
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cdc_signal_s1.vhd
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1-- $Id: cdc_signal_s1.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: cdc_signal_s1 - syn
7-- Description: clock domain crossing for a signal, 2 stage
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
13-- Revision History:
14-- Date Rev Version Comment
15-- 2016-06-11 774 1.1 add INIT generic
16-- 2016-04-08 459 1.0 Initial version
17--
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22
23use work.slvtypes.all;
24
25entity cdc_signal_s1 is -- cdc for signal (2 stage)
26 generic (
27 INIT : slbit := '0'); -- initial state
28 port (
29 CLKO : in slbit; -- O|output clock
30 DI : in slbit; -- I|input data
31 DO : out slbit -- O|output data
32 );
33end entity cdc_signal_s1;
34
35
36architecture syn of cdc_signal_s1 is
37
38 signal R_DO_S0 : slbit := INIT;
39 signal R_DO_S1 : slbit := INIT;
40
41 attribute ASYNC_REG: string;
42
43 attribute ASYNC_REG of R_DO_S0 : signal is "true";
44 attribute ASYNC_REG of R_DO_S1 : signal is "true";
45
46begin
47
48 proc_regs: process (CLKO)
49 begin
50 if rising_edge(CLKO) then
51 R_DO_S0 <= DI; -- synch 0: CLKI->CLKO
52 R_DO_S1 <= R_DO_S0; -- synch 1: CLKO
53 end if;
54 end process proc_regs;
55
56 DO <= R_DO_S1;
57
58end syn;
slbit := INIT R_DO_S0
slbit := INIT R_DO_S1
in DI slbit
in CLKO slbit
INIT slbit := '0'
out DO slbit
std_logic slbit
Definition: slvtypes.vhd:30