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W11 CPU core and support modules
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cdc_signal_s1.vhd
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-- $Id: cdc_signal_s1.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: cdc_signal_s1 - syn
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-- Description: clock domain crossing for a signal, 2 stage
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-06-11 774 1.1 add INIT generic
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-- 2016-04-08 459 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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entity
cdc_signal_s1
is
-- cdc for signal (2 stage)
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generic
(
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INIT
:
slbit
:=
'
0
'
)
;
-- initial state
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port
(
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CLKO
:
in
slbit
;
-- O|output clock
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DI
:
in
slbit
;
-- I|input data
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DO
:
out
slbit
-- O|output data
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)
;
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end
entity
cdc_signal_s1
;
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architecture
syn
of
cdc_signal_s1
is
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signal
R_DO_S0
:
slbit
:=
INIT
;
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signal
R_DO_S1
:
slbit
:=
INIT
;
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attribute
ASYNC_REG
:
string
;
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attribute
ASYNC_REG
of
R_DO_S0
:
signal
is
"true"
;
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attribute
ASYNC_REG
of
R_DO_S1
:
signal
is
"true"
;
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begin
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proc_regs:
process
(
CLKO
)
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begin
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if
rising_edge
(
CLKO
)
then
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R_DO_S0
<=
DI
;
-- synch 0: CLKI->CLKO
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R_DO_S1
<=
R_DO_S0
;
-- synch 1: CLKO
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end
if
;
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end
process
proc_regs
;
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DO
<=
R_DO_S1
;
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end
syn;
cdc_signal_s1.syn
Definition:
cdc_signal_s1.vhd:36
cdc_signal_s1.syn.ASYNC_REG
string ASYNC_REG
Definition:
cdc_signal_s1.vhd:41
cdc_signal_s1.syn.R_DO_S0
slbit := INIT R_DO_S0
Definition:
cdc_signal_s1.vhd:38
cdc_signal_s1.syn.R_DO_S1
slbit := INIT R_DO_S1
Definition:
cdc_signal_s1.vhd:39
cdc_signal_s1
Definition:
cdc_signal_s1.vhd:25
cdc_signal_s1.DI
in DI slbit
Definition:
cdc_signal_s1.vhd:30
cdc_signal_s1.CLKO
in CLKO slbit
Definition:
cdc_signal_s1.vhd:29
cdc_signal_s1.INIT
INIT slbit := '0'
Definition:
cdc_signal_s1.vhd:27
cdc_signal_s1.DO
out DO slbit
Definition:
cdc_signal_s1.vhd:32
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
vlib
cdclib
cdc_signal_s1.vhd
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