syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLKO )

Subtypes
d_range	integer range DWIDTH - 1 downto 0

Signals
R_DO_S0	slv ( d_range ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " true "

Detailed Description

Definition at line 37 of file cdc_vector_s0.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLKO   )

Process

Definition at line 49 of file cdc_vector_s0.vhd.

Member Data Documentation

d_range

d_range integer range DWIDTH - 1 downto 0

Subtype

Definition at line 39 of file cdc_vector_s0.vhd.

R_DO_S0

R_DO_S0 slv ( d_range ) := ( others = > ' 0 ' )

Signal

Definition at line 41 of file cdc_vector_s0.vhd.

ASYNC_REG [1/2]

ASYNC_REG string

Attribute

Definition at line 43 of file cdc_vector_s0.vhd.

ASYNC_REG [2/2]

ASYNC_REG signal is " true "

Attribute

Definition at line 45 of file cdc_vector_s0.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/cdclib/cdc_vector_s0.vhd