w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
migui_arty Entity Reference
Inheritance diagram for migui_arty:
[legend]
Collaboration diagram for migui_arty:
[legend]

Entities

arch_migui_arty  architecture
 
sim  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
slvtypes  Package <slvtypes>
miglib  Package <miglib>
miglib_arty  Package <miglib_arty>

Ports

DDR3_DQ   inout   slv16
DDR3_DQS_P   inout   slv2
DDR3_DQS_N   inout   slv2
DDR3_ADDR   out   slv14
DDR3_BA   out   slv3
DDR3_RAS_N   out   slbit
DDR3_CAS_N   out   slbit
DDR3_WE_N   out   slbit
DDR3_RESET_N   out   slbit
DDR3_CK_P   out   slv1
DDR3_CK_N   out   slv1
DDR3_CKE   out   slv1
DDR3_CS_N   out   slv1
DDR3_DM   out   slv2
DDR3_ODT   out   slv1
APP_ADDR   in   slv ( mig_mawidth- 1 downto 0 )
APP_CMD   in   slv3
APP_EN   in   slbit
APP_WDF_DATA   in   slv ( mig_dwidth- 1 downto 0 )
APP_WDF_END   in   slbit
APP_WDF_MASK   in   slv ( mig_mwidth- 1 downto 0 )
APP_WDF_WREN   in   slbit
APP_RD_DATA   out   slv ( mig_dwidth- 1 downto 0 )
APP_RD_DATA_END   out   slbit
APP_RD_DATA_VALID   out   slbit
APP_RDY   out   slbit
APP_WDF_RDY   out   slbit
APP_SR_REQ   in   slbit
APP_REF_REQ   in   slbit
APP_ZQ_REQ   in   slbit
APP_SR_ACTIVE   out   slbit
APP_REF_ACK   out   slbit
APP_ZQ_ACK   out   slbit
UI_CLK   out   slbit
UI_CLK_SYNC_RST   out   slbit
INIT_CALIB_COMPLETE   out   slbit
SYS_CLK_I   in   slbit
CLK_REF_I   in   slbit
DEVICE_TEMP_I   in   slv12
SYS_RST   in   slbit
ddr3_dq   inout   std_logic_vector ( 15 downto 0 )
ddr3_dqs_p   inout   std_logic_vector ( 1 downto 0 )
ddr3_dqs_n   inout   std_logic_vector ( 1 downto 0 )
ddr3_addr   out   std_logic_vector ( 13 downto 0 )
ddr3_ba   out   std_logic_vector ( 2 downto 0 )
ddr3_ras_n   out   std_logic
ddr3_cas_n   out   std_logic
ddr3_we_n   out   std_logic
ddr3_reset_n   out   std_logic
ddr3_ck_p   out   std_logic_vector ( 0 downto 0 )
ddr3_ck_n   out   std_logic_vector ( 0 downto 0 )
ddr3_cke   out   std_logic_vector ( 0 downto 0 )
ddr3_cs_n   out   std_logic_vector ( 0 downto 0 )
ddr3_dm   out   std_logic_vector ( 1 downto 0 )
ddr3_odt   out   std_logic_vector ( 0 downto 0 )
app_addr   in   std_logic_vector ( 27 downto 0 )
app_cmd   in   std_logic_vector ( 2 downto 0 )
app_en   in   std_logic
app_wdf_data   in   std_logic_vector ( 127 downto 0 )
app_wdf_end   in   std_logic
app_wdf_mask   in   std_logic_vector ( 15 downto 0 )
app_wdf_wren   in   std_logic
app_rd_data   out   std_logic_vector ( 127 downto 0 )
app_rd_data_end   out   std_logic
app_rd_data_valid   out   std_logic
app_rdy   out   std_logic
app_wdf_rdy   out   std_logic
app_sr_req   in   std_logic
app_ref_req   in   std_logic
app_zq_req   in   std_logic
app_sr_active   out   std_logic
app_ref_ack   out   std_logic
app_zq_ack   out   std_logic
ui_clk   out   std_logic
ui_clk_sync_rst   out   std_logic
init_calib_complete   out   std_logic
sys_clk_i   in   std_logic
clk_ref_i   in   std_logic
device_temp_i   in   std_logic_vector ( 11 downto 0 )
device_temp   out   std_logic_vector ( 11 downto 0 )
sys_rst   in   std_logic

Detailed Description

Definition at line 29 of file migui_arty_gsim.vhd.

Member Data Documentation

◆ DDR3_DQ

DDR3_DQ inout slv16
Port

Definition at line 31 of file migui_arty_gsim.vhd.

◆ DDR3_DQS_P

DDR3_DQS_P inout slv2
Port

Definition at line 32 of file migui_arty_gsim.vhd.

◆ DDR3_DQS_N

DDR3_DQS_N inout slv2
Port

Definition at line 33 of file migui_arty_gsim.vhd.

◆ DDR3_ADDR

DDR3_ADDR out slv14
Port

Definition at line 34 of file migui_arty_gsim.vhd.

◆ DDR3_BA

DDR3_BA out slv3
Port

Definition at line 35 of file migui_arty_gsim.vhd.

◆ DDR3_RAS_N

DDR3_RAS_N out slbit
Port

Definition at line 36 of file migui_arty_gsim.vhd.

◆ DDR3_CAS_N

DDR3_CAS_N out slbit
Port

Definition at line 37 of file migui_arty_gsim.vhd.

◆ DDR3_WE_N

DDR3_WE_N out slbit
Port

Definition at line 38 of file migui_arty_gsim.vhd.

◆ DDR3_RESET_N

DDR3_RESET_N out slbit
Port

Definition at line 39 of file migui_arty_gsim.vhd.

◆ DDR3_CK_P

DDR3_CK_P out slv1
Port

Definition at line 40 of file migui_arty_gsim.vhd.

◆ DDR3_CK_N

DDR3_CK_N out slv1
Port

Definition at line 41 of file migui_arty_gsim.vhd.

◆ DDR3_CKE

DDR3_CKE out slv1
Port

Definition at line 42 of file migui_arty_gsim.vhd.

◆ DDR3_CS_N

DDR3_CS_N out slv1
Port

Definition at line 43 of file migui_arty_gsim.vhd.

◆ DDR3_DM

DDR3_DM out slv2
Port

Definition at line 44 of file migui_arty_gsim.vhd.

◆ DDR3_ODT

DDR3_ODT out slv1
Port

Definition at line 45 of file migui_arty_gsim.vhd.

◆ APP_ADDR

APP_ADDR in slv ( mig_mawidth- 1 downto 0 )
Port

Definition at line 46 of file migui_arty_gsim.vhd.

◆ APP_CMD

APP_CMD in slv3
Port

Definition at line 47 of file migui_arty_gsim.vhd.

◆ APP_EN

APP_EN in slbit
Port

Definition at line 48 of file migui_arty_gsim.vhd.

◆ APP_WDF_DATA

APP_WDF_DATA in slv ( mig_dwidth- 1 downto 0 )
Port

Definition at line 49 of file migui_arty_gsim.vhd.

◆ APP_WDF_END

APP_WDF_END in slbit
Port

Definition at line 50 of file migui_arty_gsim.vhd.

◆ APP_WDF_MASK

APP_WDF_MASK in slv ( mig_mwidth- 1 downto 0 )
Port

Definition at line 51 of file migui_arty_gsim.vhd.

◆ APP_WDF_WREN

APP_WDF_WREN in slbit
Port

Definition at line 52 of file migui_arty_gsim.vhd.

◆ APP_RD_DATA

APP_RD_DATA out slv ( mig_dwidth- 1 downto 0 )
Port

Definition at line 53 of file migui_arty_gsim.vhd.

◆ APP_RD_DATA_END

APP_RD_DATA_END out slbit
Port

Definition at line 54 of file migui_arty_gsim.vhd.

◆ APP_RD_DATA_VALID

APP_RD_DATA_VALID out slbit
Port

Definition at line 55 of file migui_arty_gsim.vhd.

◆ APP_RDY

APP_RDY out slbit
Port

Definition at line 56 of file migui_arty_gsim.vhd.

◆ APP_WDF_RDY

APP_WDF_RDY out slbit
Port

Definition at line 57 of file migui_arty_gsim.vhd.

◆ APP_SR_REQ

APP_SR_REQ in slbit
Port

Definition at line 58 of file migui_arty_gsim.vhd.

◆ APP_REF_REQ

APP_REF_REQ in slbit
Port

Definition at line 59 of file migui_arty_gsim.vhd.

◆ APP_ZQ_REQ

APP_ZQ_REQ in slbit
Port

Definition at line 60 of file migui_arty_gsim.vhd.

◆ APP_SR_ACTIVE

APP_SR_ACTIVE out slbit
Port

Definition at line 61 of file migui_arty_gsim.vhd.

◆ APP_REF_ACK

APP_REF_ACK out slbit
Port

Definition at line 62 of file migui_arty_gsim.vhd.

◆ APP_ZQ_ACK

APP_ZQ_ACK out slbit
Port

Definition at line 63 of file migui_arty_gsim.vhd.

◆ UI_CLK

UI_CLK out slbit
Port

Definition at line 64 of file migui_arty_gsim.vhd.

◆ UI_CLK_SYNC_RST

UI_CLK_SYNC_RST out slbit
Port

Definition at line 65 of file migui_arty_gsim.vhd.

◆ INIT_CALIB_COMPLETE

INIT_CALIB_COMPLETE out slbit
Port

Definition at line 66 of file migui_arty_gsim.vhd.

◆ SYS_CLK_I

SYS_CLK_I in slbit
Port

Definition at line 67 of file migui_arty_gsim.vhd.

◆ CLK_REF_I

CLK_REF_I in slbit
Port

Definition at line 68 of file migui_arty_gsim.vhd.

◆ DEVICE_TEMP_I

DEVICE_TEMP_I in slv12
Port

Definition at line 69 of file migui_arty_gsim.vhd.

◆ SYS_RST

SYS_RST in slbit
Port

Definition at line 71 of file migui_arty_gsim.vhd.

◆ ieee

ieee
Library

Definition at line 21 of file migui_arty_gsim.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 22 of file migui_arty_gsim.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 23 of file migui_arty_gsim.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 25 of file migui_arty_gsim.vhd.

◆ miglib

miglib
use clause

Definition at line 26 of file migui_arty_gsim.vhd.

◆ miglib_arty

miglib_arty
use clause

Definition at line 27 of file migui_arty_gsim.vhd.

◆ ddr3_dq

ddr3_dq inout std_logic_vector ( 15 downto 0 )
Port

Definition at line 74 of file migui_arty.vhd.

◆ ddr3_dqs_p

ddr3_dqs_p inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 75 of file migui_arty.vhd.

◆ ddr3_dqs_n

ddr3_dqs_n inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 76 of file migui_arty.vhd.

◆ ddr3_addr

ddr3_addr out std_logic_vector ( 13 downto 0 )
Port

Definition at line 78 of file migui_arty.vhd.

◆ ddr3_ba

ddr3_ba out std_logic_vector ( 2 downto 0 )
Port

Definition at line 79 of file migui_arty.vhd.

◆ ddr3_ras_n

ddr3_ras_n out std_logic
Port

Definition at line 80 of file migui_arty.vhd.

◆ ddr3_cas_n

ddr3_cas_n out std_logic
Port

Definition at line 81 of file migui_arty.vhd.

◆ ddr3_we_n

ddr3_we_n out std_logic
Port

Definition at line 82 of file migui_arty.vhd.

◆ ddr3_reset_n

ddr3_reset_n out std_logic
Port

Definition at line 83 of file migui_arty.vhd.

◆ ddr3_ck_p

ddr3_ck_p out std_logic_vector ( 0 downto 0 )
Port

Definition at line 84 of file migui_arty.vhd.

◆ ddr3_ck_n

ddr3_ck_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 85 of file migui_arty.vhd.

◆ ddr3_cke

ddr3_cke out std_logic_vector ( 0 downto 0 )
Port

Definition at line 86 of file migui_arty.vhd.

◆ ddr3_cs_n

ddr3_cs_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 87 of file migui_arty.vhd.

◆ ddr3_dm

ddr3_dm out std_logic_vector ( 1 downto 0 )
Port

Definition at line 88 of file migui_arty.vhd.

◆ ddr3_odt

ddr3_odt out std_logic_vector ( 0 downto 0 )
Port

Definition at line 89 of file migui_arty.vhd.

◆ app_addr

app_addr in std_logic_vector ( 27 downto 0 )
Port

Definition at line 90 of file migui_arty.vhd.

◆ app_cmd

app_cmd in std_logic_vector ( 2 downto 0 )
Port

Definition at line 91 of file migui_arty.vhd.

◆ app_en

app_en in std_logic
Port

Definition at line 92 of file migui_arty.vhd.

◆ app_wdf_data

app_wdf_data in std_logic_vector ( 127 downto 0 )
Port

Definition at line 93 of file migui_arty.vhd.

◆ app_wdf_end

app_wdf_end in std_logic
Port

Definition at line 94 of file migui_arty.vhd.

◆ app_wdf_mask

app_wdf_mask in std_logic_vector ( 15 downto 0 )
Port

Definition at line 95 of file migui_arty.vhd.

◆ app_wdf_wren

app_wdf_wren in std_logic
Port

Definition at line 96 of file migui_arty.vhd.

◆ app_rd_data

app_rd_data out std_logic_vector ( 127 downto 0 )
Port

Definition at line 97 of file migui_arty.vhd.

◆ app_rd_data_end

app_rd_data_end out std_logic
Port

Definition at line 98 of file migui_arty.vhd.

◆ app_rd_data_valid

app_rd_data_valid out std_logic
Port

Definition at line 99 of file migui_arty.vhd.

◆ app_rdy

app_rdy out std_logic
Port

Definition at line 100 of file migui_arty.vhd.

◆ app_wdf_rdy

app_wdf_rdy out std_logic
Port

Definition at line 101 of file migui_arty.vhd.

◆ app_sr_req

app_sr_req in std_logic
Port

Definition at line 102 of file migui_arty.vhd.

◆ app_ref_req

app_ref_req in std_logic
Port

Definition at line 103 of file migui_arty.vhd.

◆ app_zq_req

app_zq_req in std_logic
Port

Definition at line 104 of file migui_arty.vhd.

◆ app_sr_active

app_sr_active out std_logic
Port

Definition at line 105 of file migui_arty.vhd.

◆ app_ref_ack

app_ref_ack out std_logic
Port

Definition at line 106 of file migui_arty.vhd.

◆ app_zq_ack

app_zq_ack out std_logic
Port

Definition at line 107 of file migui_arty.vhd.

◆ ui_clk

ui_clk out std_logic
Port

Definition at line 108 of file migui_arty.vhd.

◆ ui_clk_sync_rst

ui_clk_sync_rst out std_logic
Port

Definition at line 109 of file migui_arty.vhd.

◆ init_calib_complete

init_calib_complete out std_logic
Port

Definition at line 110 of file migui_arty.vhd.

◆ sys_clk_i

sys_clk_i in std_logic
Port

Definition at line 112 of file migui_arty.vhd.

◆ clk_ref_i

clk_ref_i in std_logic
Port

Definition at line 114 of file migui_arty.vhd.

◆ device_temp_i

device_temp_i in std_logic_vector ( 11 downto 0 )
Port

Definition at line 115 of file migui_arty.vhd.

◆ device_temp

device_temp out std_logic_vector ( 11 downto 0 )
Port

Definition at line 116 of file migui_arty.vhd.

◆ sys_rst

sys_rst in std_logic
Port

Definition at line 118 of file migui_arty.vhd.

The documentation for this design unit was generated from the following files: