w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
migui_artys7 Entity Reference
Inheritance diagram for migui_artys7:
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Collaboration diagram for migui_artys7:
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Entities

sim  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
slvtypes  Package <slvtypes>
miglib  Package <miglib>
miglib_artys7  Package <miglib_artys7>

Ports

DDR3_DQ   inout   slv16
DDR3_DQS_P   inout   slv2
DDR3_DQS_N   inout   slv2
DDR3_ADDR   out   slv14
DDR3_BA   out   slv3
DDR3_RAS_N   out   slbit
DDR3_CAS_N   out   slbit
DDR3_WE_N   out   slbit
DDR3_RESET_N   out   slbit
DDR3_CK_P   out   slv1
DDR3_CK_N   out   slv1
DDR3_CKE   out   slv1
DDR3_CS_N   out   slv1
DDR3_DM   out   slv2
DDR3_ODT   out   slv1
APP_ADDR   in   slv ( mig_mawidth- 1 downto 0 )
APP_CMD   in   slv3
APP_EN   in   slbit
APP_WDF_DATA   in   slv ( mig_dwidth- 1 downto 0 )
APP_WDF_END   in   slbit
APP_WDF_MASK   in   slv ( mig_mwidth- 1 downto 0 )
APP_WDF_WREN   in   slbit
APP_RD_DATA   out   slv ( mig_dwidth- 1 downto 0 )
APP_RD_DATA_END   out   slbit
APP_RD_DATA_VALID   out   slbit
APP_RDY   out   slbit
APP_WDF_RDY   out   slbit
APP_SR_REQ   in   slbit
APP_REF_REQ   in   slbit
APP_ZQ_REQ   in   slbit
APP_SR_ACTIVE   out   slbit
APP_REF_ACK   out   slbit
APP_ZQ_ACK   out   slbit
UI_CLK   out   slbit
UI_CLK_SYNC_RST   out   slbit
INIT_CALIB_COMPLETE   out   slbit
SYS_CLK_I   in   slbit
CLK_REF_I   in   slbit
DEVICE_TEMP_I   in   slv12
SYS_RST   in   slbit

Detailed Description

Definition at line 28 of file migui_artys7_gsim.vhd.

Member Data Documentation

◆ DDR3_DQ

DDR3_DQ inout slv16
Port

Definition at line 30 of file migui_artys7_gsim.vhd.

◆ DDR3_DQS_P

DDR3_DQS_P inout slv2
Port

Definition at line 31 of file migui_artys7_gsim.vhd.

◆ DDR3_DQS_N

DDR3_DQS_N inout slv2
Port

Definition at line 32 of file migui_artys7_gsim.vhd.

◆ DDR3_ADDR

DDR3_ADDR out slv14
Port

Definition at line 33 of file migui_artys7_gsim.vhd.

◆ DDR3_BA

DDR3_BA out slv3
Port

Definition at line 34 of file migui_artys7_gsim.vhd.

◆ DDR3_RAS_N

DDR3_RAS_N out slbit
Port

Definition at line 35 of file migui_artys7_gsim.vhd.

◆ DDR3_CAS_N

DDR3_CAS_N out slbit
Port

Definition at line 36 of file migui_artys7_gsim.vhd.

◆ DDR3_WE_N

DDR3_WE_N out slbit
Port

Definition at line 37 of file migui_artys7_gsim.vhd.

◆ DDR3_RESET_N

DDR3_RESET_N out slbit
Port

Definition at line 38 of file migui_artys7_gsim.vhd.

◆ DDR3_CK_P

DDR3_CK_P out slv1
Port

Definition at line 39 of file migui_artys7_gsim.vhd.

◆ DDR3_CK_N

DDR3_CK_N out slv1
Port

Definition at line 40 of file migui_artys7_gsim.vhd.

◆ DDR3_CKE

DDR3_CKE out slv1
Port

Definition at line 41 of file migui_artys7_gsim.vhd.

◆ DDR3_CS_N

DDR3_CS_N out slv1
Port

Definition at line 42 of file migui_artys7_gsim.vhd.

◆ DDR3_DM

DDR3_DM out slv2
Port

Definition at line 43 of file migui_artys7_gsim.vhd.

◆ DDR3_ODT

DDR3_ODT out slv1
Port

Definition at line 44 of file migui_artys7_gsim.vhd.

◆ APP_ADDR

APP_ADDR in slv ( mig_mawidth- 1 downto 0 )
Port

Definition at line 45 of file migui_artys7_gsim.vhd.

◆ APP_CMD

APP_CMD in slv3
Port

Definition at line 46 of file migui_artys7_gsim.vhd.

◆ APP_EN

APP_EN in slbit
Port

Definition at line 47 of file migui_artys7_gsim.vhd.

◆ APP_WDF_DATA

APP_WDF_DATA in slv ( mig_dwidth- 1 downto 0 )
Port

Definition at line 48 of file migui_artys7_gsim.vhd.

◆ APP_WDF_END

APP_WDF_END in slbit
Port

Definition at line 49 of file migui_artys7_gsim.vhd.

◆ APP_WDF_MASK

APP_WDF_MASK in slv ( mig_mwidth- 1 downto 0 )
Port

Definition at line 50 of file migui_artys7_gsim.vhd.

◆ APP_WDF_WREN

APP_WDF_WREN in slbit
Port

Definition at line 51 of file migui_artys7_gsim.vhd.

◆ APP_RD_DATA

APP_RD_DATA out slv ( mig_dwidth- 1 downto 0 )
Port

Definition at line 52 of file migui_artys7_gsim.vhd.

◆ APP_RD_DATA_END

APP_RD_DATA_END out slbit
Port

Definition at line 53 of file migui_artys7_gsim.vhd.

◆ APP_RD_DATA_VALID

APP_RD_DATA_VALID out slbit
Port

Definition at line 54 of file migui_artys7_gsim.vhd.

◆ APP_RDY

APP_RDY out slbit
Port

Definition at line 55 of file migui_artys7_gsim.vhd.

◆ APP_WDF_RDY

APP_WDF_RDY out slbit
Port

Definition at line 56 of file migui_artys7_gsim.vhd.

◆ APP_SR_REQ

APP_SR_REQ in slbit
Port

Definition at line 57 of file migui_artys7_gsim.vhd.

◆ APP_REF_REQ

APP_REF_REQ in slbit
Port

Definition at line 58 of file migui_artys7_gsim.vhd.

◆ APP_ZQ_REQ

APP_ZQ_REQ in slbit
Port

Definition at line 59 of file migui_artys7_gsim.vhd.

◆ APP_SR_ACTIVE

APP_SR_ACTIVE out slbit
Port

Definition at line 60 of file migui_artys7_gsim.vhd.

◆ APP_REF_ACK

APP_REF_ACK out slbit
Port

Definition at line 61 of file migui_artys7_gsim.vhd.

◆ APP_ZQ_ACK

APP_ZQ_ACK out slbit
Port

Definition at line 62 of file migui_artys7_gsim.vhd.

◆ UI_CLK

UI_CLK out slbit
Port

Definition at line 63 of file migui_artys7_gsim.vhd.

◆ UI_CLK_SYNC_RST

UI_CLK_SYNC_RST out slbit
Port

Definition at line 64 of file migui_artys7_gsim.vhd.

◆ INIT_CALIB_COMPLETE

INIT_CALIB_COMPLETE out slbit
Port

Definition at line 65 of file migui_artys7_gsim.vhd.

◆ SYS_CLK_I

SYS_CLK_I in slbit
Port

Definition at line 66 of file migui_artys7_gsim.vhd.

◆ CLK_REF_I

CLK_REF_I in slbit
Port

Definition at line 67 of file migui_artys7_gsim.vhd.

◆ DEVICE_TEMP_I

DEVICE_TEMP_I in slv12
Port

Definition at line 68 of file migui_artys7_gsim.vhd.

◆ SYS_RST

SYS_RST in slbit
Port

Definition at line 70 of file migui_artys7_gsim.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file migui_artys7_gsim.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 21 of file migui_artys7_gsim.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 22 of file migui_artys7_gsim.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 24 of file migui_artys7_gsim.vhd.

◆ miglib

miglib
use clause

Definition at line 25 of file migui_artys7_gsim.vhd.

◆ miglib_artys7

miglib_artys7
use clause

Definition at line 26 of file migui_artys7_gsim.vhd.

The documentation for this design unit was generated from the following file: