w11 - vhd 0.794
W11 CPU core and support modules
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sn_humanio Entity Reference
Inheritance diagram for sn_humanio:
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Collaboration diagram for sn_humanio:
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Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
slvtypes  Package <slvtypes>
xlib  Package <xlib>
bpgenlib  Package <bpgenlib>

Generics

SWIDTH  positive := 8
BWIDTH  positive := 4
LWIDTH  positive := 8
DCWIDTH  positive := 2
DEBOUNCE  boolean := true

Ports

CLK   in   slbit
RESET   in   slbit := ' 0 '
CE_MSEC   in   slbit
SWI   out   slv ( SWIDTH - 1 downto 0 )
BTN   out   slv ( BWIDTH - 1 downto 0 )
LED   in   slv ( LWIDTH - 1 downto 0 )
DSP_DAT   in   slv ( 4 * ( 2 ** DCWIDTH ) - 1 downto 0 )
DSP_DP   in   slv ( ( 2 ** DCWIDTH ) - 1 downto 0 )
I_SWI   in   slv ( SWIDTH - 1 downto 0 )
I_BTN   in   slv ( BWIDTH - 1 downto 0 )
O_LED   out   slv ( LWIDTH - 1 downto 0 )
O_ANO_N   out   slv ( ( 2 ** DCWIDTH ) - 1 downto 0 )
O_SEG_N   out   slv8

Detailed Description

Definition at line 48 of file sn_humanio.vhd.

Member Data Documentation

◆ SWIDTH

SWIDTH positive := 8
Generic

Definition at line 50 of file sn_humanio.vhd.

◆ BWIDTH

BWIDTH positive := 4
Generic

Definition at line 51 of file sn_humanio.vhd.

◆ LWIDTH

LWIDTH positive := 8
Generic

Definition at line 52 of file sn_humanio.vhd.

◆ DCWIDTH

DCWIDTH positive := 2
Generic

Definition at line 53 of file sn_humanio.vhd.

◆ DEBOUNCE

DEBOUNCE boolean := true
Generic

Definition at line 54 of file sn_humanio.vhd.

◆ CLK

CLK in slbit
Port

Definition at line 56 of file sn_humanio.vhd.

◆ RESET

RESET in slbit := ' 0 '
Port

Definition at line 57 of file sn_humanio.vhd.

◆ CE_MSEC

CE_MSEC in slbit
Port

Definition at line 58 of file sn_humanio.vhd.

◆ SWI

SWI out slv ( SWIDTH - 1 downto 0 )
Port

Definition at line 59 of file sn_humanio.vhd.

◆ BTN

BTN out slv ( BWIDTH - 1 downto 0 )
Port

Definition at line 60 of file sn_humanio.vhd.

◆ LED

LED in slv ( LWIDTH - 1 downto 0 )
Port

Definition at line 61 of file sn_humanio.vhd.

◆ DSP_DAT

DSP_DAT in slv ( 4 * ( 2 ** DCWIDTH ) - 1 downto 0 )
Port

Definition at line 62 of file sn_humanio.vhd.

◆ DSP_DP

DSP_DP in slv ( ( 2 ** DCWIDTH ) - 1 downto 0 )
Port

Definition at line 63 of file sn_humanio.vhd.

◆ I_SWI

I_SWI in slv ( SWIDTH - 1 downto 0 )
Port

Definition at line 64 of file sn_humanio.vhd.

◆ I_BTN

I_BTN in slv ( BWIDTH - 1 downto 0 )
Port

Definition at line 65 of file sn_humanio.vhd.

◆ O_LED

O_LED out slv ( LWIDTH - 1 downto 0 )
Port

Definition at line 66 of file sn_humanio.vhd.

◆ O_ANO_N

O_ANO_N out slv ( ( 2 ** DCWIDTH ) - 1 downto 0 )
Port

Definition at line 67 of file sn_humanio.vhd.

◆ O_SEG_N

O_SEG_N out slv8
Port

Definition at line 69 of file sn_humanio.vhd.

◆ ieee

ieee
Library

Definition at line 39 of file sn_humanio.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 40 of file sn_humanio.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 42 of file sn_humanio.vhd.

◆ xlib

xlib
use clause

Definition at line 43 of file sn_humanio.vhd.

◆ bpgenlib

bpgenlib
use clause

Definition at line 44 of file sn_humanio.vhd.


The documentation for this design unit was generated from the following file: