sim Architecture Reference

Architecture >> sim

Processes
proc_stim

Signals
CE_N	slbit := ' 1 '
OE_N	slbit := ' 1 '
WE_N	slbit := ' 1 '
UB_N	slbit := ' 1 '
LB_N	slbit := ' 1 '
ADDR	slv18 := ( others = > ' 0 ' )
DATA	slv16 := ( others = > ' 0 ' )

Instantiations
uut	is61lv25616al <Entity is61lv25616al>

Detailed Description

Definition at line 37 of file tb_is61lv25616al.vhd.

Member Function/Procedure/Process Documentation

proc_stim()

proc_stim

Definition at line 60 of file tb_is61lv25616al.vhd.

Member Data Documentation

CE_N

CE_N slbit := ' 1 '

Signal

Definition at line 39 of file tb_is61lv25616al.vhd.

OE_N

OE_N slbit := ' 1 '

Signal

Definition at line 40 of file tb_is61lv25616al.vhd.

WE_N

WE_N slbit := ' 1 '

Signal

Definition at line 41 of file tb_is61lv25616al.vhd.

UB_N

UB_N slbit := ' 1 '

Signal

Definition at line 42 of file tb_is61lv25616al.vhd.

LB_N

LB_N slbit := ' 1 '

Signal

Definition at line 43 of file tb_is61lv25616al.vhd.

ADDR

ADDR slv18 := ( others = > ' 0 ' )

Signal

Definition at line 44 of file tb_is61lv25616al.vhd.

DATA

DATA slv16 := ( others = > ' 0 ' )

Signal

Definition at line 45 of file tb_is61lv25616al.vhd.

uut

uut 61lv25616al

Instantiation

Definition at line 58 of file tb_is61lv25616al.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/issi/tb/tb_is61lv25616al.vhd