w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_port_mux  ( R_PORTSEL_SER , UART_TXD , CTS_N , O_TXD , O_FUSP_TXD , O_FUSP_RTS_N )
proc_moni 
proc_simbus  ( SB_VAL )

Constants

sbaddr_portsel  slv8 := slv ( to_unsigned ( 8 , 8 ) )
clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns

Signals

CLKOSC  slbit := ' 0 '
CLKCOM  slbit := ' 0 '
CLKCOM_CYCLE  integer := 0
RESET  slbit := ' 0 '
CLKDIV  slv2 := " 00 "
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
RX_HOLD  slbit := ' 0 '
I_RXD  slbit := ' 1 '
O_TXD  slbit := ' 1 '
I_SWI  slv8 := ( others = > ' 0 ' )
I_BTN  slv4 := ( others = > ' 0 ' )
O_LED  slv8 := ( others = > ' 0 ' )
O_ANO_N  slv4 := ( others = > ' 0 ' )
O_SEG_N  slv8 := ( others = > ' 0 ' )
O_MEM_CE_N  slbit := ' 1 '
O_MEM_BE_N  slv2 := ( others = > ' 1 ' )
O_MEM_WE_N  slbit := ' 1 '
O_MEM_OE_N  slbit := ' 1 '
O_MEM_ADV_N  slbit := ' 1 '
O_MEM_CLK  slbit := ' 0 '
O_MEM_CRE  slbit := ' 0 '
I_MEM_WAIT  slbit := ' 0 '
O_MEM_ADDR  slv23 := ( others = > ' Z ' )
IO_MEM_DATA  slv16 := ( others = > ' 0 ' )
O_FLA_CE_N  slbit := ' 0 '
O_FUSP_RTS_N  slbit := ' 0 '
I_FUSP_CTS_N  slbit := ' 0 '
I_FUSP_RXD  slbit := ' 1 '
O_FUSP_TXD  slbit := ' 1 '
UART_RESET  slbit := ' 0 '
UART_RXD  slbit := ' 1 '
UART_TXD  slbit := ' 1 '
CTS_N  slbit := ' 0 '
RTS_N  slbit := ' 0 '
R_PORTSEL_SER  slbit := ' 0 '
R_PORTSEL_XON  slbit := ' 0 '

Instantiations

clkgen  simclk <Entity simclk>
dcm_com  dcm_sfs <Entity dcm_sfs>
clkcnt  simclkcnt <Entity simclkcnt>
tbcore  tbcore_rlink <Entity tbcore_rlink>
n2core  tb_nexys2_core <Entity tb_nexys2_core>
uut  nexys2_fusp_aif
sermstr  serport_master_tb <Entity serport_master_tb>

Detailed Description

Definition at line 55 of file tb_nexys2_fusp.vhd.

Member Function/Procedure/Process Documentation

◆ proc_port_mux()

proc_port_mux (   R_PORTSEL_SER,
  UART_TXD,
  CTS_N,
  O_TXD,
  O_FUSP_TXD,
  O_FUSP_RTS_N 
)

Definition at line 213 of file tb_nexys2_fusp.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 233 of file tb_nexys2_fusp.vhd.

◆ proc_simbus()

proc_simbus (   SB_VAL  
)
Process

Definition at line 249 of file tb_nexys2_fusp.vhd.

Member Data Documentation

◆ CLKOSC

CLKOSC slbit := ' 0 '
Signal

Definition at line 57 of file tb_nexys2_fusp.vhd.

◆ CLKCOM

CLKCOM slbit := ' 0 '
Signal

Definition at line 58 of file tb_nexys2_fusp.vhd.

◆ CLKCOM_CYCLE

CLKCOM_CYCLE integer := 0
Signal

Definition at line 60 of file tb_nexys2_fusp.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 62 of file tb_nexys2_fusp.vhd.

◆ CLKDIV

CLKDIV slv2 := " 00 "
Signal

Definition at line 63 of file tb_nexys2_fusp.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 64 of file tb_nexys2_fusp.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 65 of file tb_nexys2_fusp.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 66 of file tb_nexys2_fusp.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 67 of file tb_nexys2_fusp.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 68 of file tb_nexys2_fusp.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 69 of file tb_nexys2_fusp.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 70 of file tb_nexys2_fusp.vhd.

◆ RX_HOLD

RX_HOLD slbit := ' 0 '
Signal

Definition at line 72 of file tb_nexys2_fusp.vhd.

◆ I_RXD

I_RXD slbit := ' 1 '
Signal

Definition at line 74 of file tb_nexys2_fusp.vhd.

◆ O_TXD

O_TXD slbit := ' 1 '
Signal

Definition at line 75 of file tb_nexys2_fusp.vhd.

◆ I_SWI

I_SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 76 of file tb_nexys2_fusp.vhd.

◆ I_BTN

I_BTN slv4 := ( others = > ' 0 ' )
Signal

Definition at line 77 of file tb_nexys2_fusp.vhd.

◆ O_LED

O_LED slv8 := ( others = > ' 0 ' )
Signal

Definition at line 78 of file tb_nexys2_fusp.vhd.

◆ O_ANO_N

O_ANO_N slv4 := ( others = > ' 0 ' )
Signal

Definition at line 79 of file tb_nexys2_fusp.vhd.

◆ O_SEG_N

O_SEG_N slv8 := ( others = > ' 0 ' )
Signal

Definition at line 80 of file tb_nexys2_fusp.vhd.

◆ O_MEM_CE_N

O_MEM_CE_N slbit := ' 1 '
Signal

Definition at line 82 of file tb_nexys2_fusp.vhd.

◆ O_MEM_BE_N

O_MEM_BE_N slv2 := ( others = > ' 1 ' )
Signal

Definition at line 83 of file tb_nexys2_fusp.vhd.

◆ O_MEM_WE_N

O_MEM_WE_N slbit := ' 1 '
Signal

Definition at line 84 of file tb_nexys2_fusp.vhd.

◆ O_MEM_OE_N

O_MEM_OE_N slbit := ' 1 '
Signal

Definition at line 85 of file tb_nexys2_fusp.vhd.

◆ O_MEM_ADV_N

O_MEM_ADV_N slbit := ' 1 '
Signal

Definition at line 86 of file tb_nexys2_fusp.vhd.

◆ O_MEM_CLK

O_MEM_CLK slbit := ' 0 '
Signal

Definition at line 87 of file tb_nexys2_fusp.vhd.

◆ O_MEM_CRE

O_MEM_CRE slbit := ' 0 '
Signal

Definition at line 88 of file tb_nexys2_fusp.vhd.

◆ I_MEM_WAIT

I_MEM_WAIT slbit := ' 0 '
Signal

Definition at line 89 of file tb_nexys2_fusp.vhd.

◆ O_MEM_ADDR

O_MEM_ADDR slv23 := ( others = > ' Z ' )
Signal

Definition at line 90 of file tb_nexys2_fusp.vhd.

◆ IO_MEM_DATA

IO_MEM_DATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 91 of file tb_nexys2_fusp.vhd.

◆ O_FLA_CE_N

O_FLA_CE_N slbit := ' 0 '
Signal

Definition at line 92 of file tb_nexys2_fusp.vhd.

◆ O_FUSP_RTS_N

O_FUSP_RTS_N slbit := ' 0 '
Signal

Definition at line 94 of file tb_nexys2_fusp.vhd.

◆ I_FUSP_CTS_N

I_FUSP_CTS_N slbit := ' 0 '
Signal

Definition at line 95 of file tb_nexys2_fusp.vhd.

◆ I_FUSP_RXD

I_FUSP_RXD slbit := ' 1 '
Signal

Definition at line 96 of file tb_nexys2_fusp.vhd.

◆ O_FUSP_TXD

O_FUSP_TXD slbit := ' 1 '
Signal

Definition at line 97 of file tb_nexys2_fusp.vhd.

◆ UART_RESET

UART_RESET slbit := ' 0 '
Signal

Definition at line 99 of file tb_nexys2_fusp.vhd.

◆ UART_RXD

UART_RXD slbit := ' 1 '
Signal

Definition at line 100 of file tb_nexys2_fusp.vhd.

◆ UART_TXD

UART_TXD slbit := ' 1 '
Signal

Definition at line 101 of file tb_nexys2_fusp.vhd.

◆ CTS_N

CTS_N slbit := ' 0 '
Signal

Definition at line 102 of file tb_nexys2_fusp.vhd.

◆ RTS_N

RTS_N slbit := ' 0 '
Signal

Definition at line 103 of file tb_nexys2_fusp.vhd.

◆ R_PORTSEL_SER

R_PORTSEL_SER slbit := ' 0 '
Signal

Definition at line 105 of file tb_nexys2_fusp.vhd.

◆ R_PORTSEL_XON

R_PORTSEL_XON slbit := ' 0 '
Signal

Definition at line 106 of file tb_nexys2_fusp.vhd.

◆ sbaddr_portsel

sbaddr_portsel slv8 := slv ( to_unsigned ( 8 , 8 ) )
Constant

Definition at line 108 of file tb_nexys2_fusp.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 110 of file tb_nexys2_fusp.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 111 of file tb_nexys2_fusp.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 121 of file tb_nexys2_fusp.vhd.

◆ dcm_com

dcm_com dcm_sfs
Instantiation

Definition at line 132 of file tb_nexys2_fusp.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 134 of file tb_nexys2_fusp.vhd.

◆ tbcore

tbcore tbcore_rlink
Instantiation

Definition at line 144 of file tb_nexys2_fusp.vhd.

◆ n2core

n2core tb_nexys2_core
Instantiation

Definition at line 162 of file tb_nexys2_fusp.vhd.

◆ uut

uut nexys2_fusp_aif
Instantiation

Definition at line 189 of file tb_nexys2_fusp.vhd.

◆ sermstr

sermstr serport_master_tb
Instantiation

Definition at line 211 of file tb_nexys2_fusp.vhd.

The documentation for this design unit was generated from the following file: