w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_moni 
proc_simbus  ( SB_VAL )

Constants

sbaddr_portsel  slv8 := slv ( to_unsigned ( 8 , 8 ) )
clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns

Signals

CLK  slbit := ' 0 '
CLK_CYCLE  integer := 0
RESET  slbit := ' 0 '
CLKDIV  slv2 := " 00 "
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
I_RXD  slbit := ' 1 '
O_TXD  slbit := ' 1 '
I_SWI  slv8 := ( others = > ' 0 ' )
I_BTN  slv4 := ( others = > ' 0 ' )
O_LED  slv8 := ( others = > ' 0 ' )
O_ANO_N  slv4 := ( others = > ' 0 ' )
O_SEG_N  slv8 := ( others = > ' 0 ' )
O_MEM_CE_N  slv2 := ( others = > ' 1 ' )
O_MEM_BE_N  slv4 := ( others = > ' 1 ' )
O_MEM_WE_N  slbit := ' 1 '
O_MEM_OE_N  slbit := ' 1 '
O_MEM_ADDR  slv18 := ( others = > ' Z ' )
IO_MEM_DATA  slv32 := ( others = > ' 0 ' )
R_PORTSEL_XON  slbit := ' 0 '

Instantiations

clkgen  simclk <Entity simclk>
clkcnt  simclkcnt <Entity simclkcnt>
tbcore  tbcore_rlink <Entity tbcore_rlink>
s3core  tb_s3board_core <Entity tb_s3board_core>
uut  s3board_aif
sermstr  serport_master_tb <Entity serport_master_tb>

Detailed Description

Definition at line 60 of file tb_s3board.vhd.

Member Function/Procedure/Process Documentation

◆ proc_moni()

proc_moni

Definition at line 171 of file tb_s3board.vhd.

◆ proc_simbus()

proc_simbus (   SB_VAL  
)
Process

Definition at line 187 of file tb_s3board.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 62 of file tb_s3board.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 64 of file tb_s3board.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 66 of file tb_s3board.vhd.

◆ CLKDIV

CLKDIV slv2 := " 00 "
Signal

Definition at line 67 of file tb_s3board.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 68 of file tb_s3board.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 69 of file tb_s3board.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 70 of file tb_s3board.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 71 of file tb_s3board.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 72 of file tb_s3board.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 73 of file tb_s3board.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 74 of file tb_s3board.vhd.

◆ I_RXD

I_RXD slbit := ' 1 '
Signal

Definition at line 76 of file tb_s3board.vhd.

◆ O_TXD

O_TXD slbit := ' 1 '
Signal

Definition at line 77 of file tb_s3board.vhd.

◆ I_SWI

I_SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 78 of file tb_s3board.vhd.

◆ I_BTN

I_BTN slv4 := ( others = > ' 0 ' )
Signal

Definition at line 79 of file tb_s3board.vhd.

◆ O_LED

O_LED slv8 := ( others = > ' 0 ' )
Signal

Definition at line 80 of file tb_s3board.vhd.

◆ O_ANO_N

O_ANO_N slv4 := ( others = > ' 0 ' )
Signal

Definition at line 81 of file tb_s3board.vhd.

◆ O_SEG_N

O_SEG_N slv8 := ( others = > ' 0 ' )
Signal

Definition at line 82 of file tb_s3board.vhd.

◆ O_MEM_CE_N

O_MEM_CE_N slv2 := ( others = > ' 1 ' )
Signal

Definition at line 83 of file tb_s3board.vhd.

◆ O_MEM_BE_N

O_MEM_BE_N slv4 := ( others = > ' 1 ' )
Signal

Definition at line 84 of file tb_s3board.vhd.

◆ O_MEM_WE_N

O_MEM_WE_N slbit := ' 1 '
Signal

Definition at line 85 of file tb_s3board.vhd.

◆ O_MEM_OE_N

O_MEM_OE_N slbit := ' 1 '
Signal

Definition at line 86 of file tb_s3board.vhd.

◆ O_MEM_ADDR

O_MEM_ADDR slv18 := ( others = > ' Z ' )
Signal

Definition at line 87 of file tb_s3board.vhd.

◆ IO_MEM_DATA

IO_MEM_DATA slv32 := ( others = > ' 0 ' )
Signal

Definition at line 88 of file tb_s3board.vhd.

◆ R_PORTSEL_XON

R_PORTSEL_XON slbit := ' 0 '
Signal

Definition at line 90 of file tb_s3board.vhd.

◆ sbaddr_portsel

sbaddr_portsel slv8 := slv ( to_unsigned ( 8 , 8 ) )
Constant

Definition at line 92 of file tb_s3board.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 94 of file tb_s3board.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 95 of file tb_s3board.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 105 of file tb_s3board.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 107 of file tb_s3board.vhd.

◆ tbcore

tbcore tbcore_rlink
Instantiation

Definition at line 117 of file tb_s3board.vhd.

◆ s3core

s3core tb_s3board_core
Instantiation

Definition at line 129 of file tb_s3board.vhd.

◆ uut

uut s3board_aif
Instantiation

Definition at line 147 of file tb_s3board.vhd.

◆ sermstr

sermstr serport_master_tb
Instantiation

Definition at line 169 of file tb_s3board.vhd.

The documentation for this design unit was generated from the following file: