25use ieee.std_logic_1164.
all;
61 proc_regs:
process (
CLK)
64 if rising_edge(CLK) then
71 end process proc_regs;
78 when "0000" => N_DATA <= "0001";
79 when "0001" => N_DATA <= "0011";
80 when "0011" => N_DATA <= "0010";
81 when "0010" => N_DATA <= "0110";
82 when "0110" => N_DATA <= "0111";
83 when "0111" => N_DATA <= "0101";
84 when "0101" => N_DATA <= "0100";
85 when "0100" => N_DATA <= "1100";
86 when "1100" => N_DATA <= "1101";
87 when "1101" => N_DATA <= "1111";
88 when "1111" => N_DATA <= "1110";
89 when "1110" => N_DATA <= "1010";
90 when "1010" => N_DATA <= "1011";
91 when "1011" => N_DATA <= "1001";
92 when "1001" => N_DATA <= "1000";
93 when "1000" => N_DATA <= "0000";
96 end process proc_next;
slv4 :=( others => '0') R_DATA
slv4 :=( others => '0') N_DATA
std_logic_vector( 3 downto 0) slv4