w11 - vhd 0.794
W11 CPU core and support modules
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nexys4_dummy.vhd
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1-- $Id: nexys4_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: nexys4_dummy - syn
7-- Description: nexys4 minimal target (base; serport loopback)
8--
9-- Dependencies: -
10-- To test: tb_nexys4
11-- Target Devices: generic
12-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2015-02-06 643 1.3 factor out memory
17-- 2015-02-01 641 1.1 separate I_BTNRST_N
18-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23
24use work.slvtypes.all;
25
26entity nexys4_dummy is -- NEXYS 4 dummy (base; loopback)
27 -- implements nexys4_aif
28 port (
29 I_CLK100 : in slbit; -- 100 MHz board clock
30 I_RXD : in slbit; -- receive data (board view)
31 O_TXD : out slbit; -- transmit data (board view)
32 O_RTS_N : out slbit; -- rx rts (board view; act.low)
33 I_CTS_N : in slbit; -- tx cts (board view; act.low)
34 I_SWI : in slv16; -- n4 switches
35 I_BTN : in slv5; -- n4 buttons
36 I_BTNRST_N : in slbit; -- n4 reset button
37 O_LED : out slv16; -- n4 leds
38 O_RGBLED0 : out slv3; -- n4 rgb-led 0
39 O_RGBLED1 : out slv3; -- n4 rgb-led 1
40 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
41 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
42 );
43end nexys4_dummy;
44
45architecture syn of nexys4_dummy is
46
47begin
48
49 O_TXD <= I_RXD; -- loop back serport
51
52 O_LED <= I_SWI; -- mirror SWI on LED
53
54 O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
55 O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
56
57 O_ANO_N <= (others=>'1');
58 O_SEG_N <= (others=>'1');
59
60end syn;
out O_TXD slbit
in I_RXD slbit
out O_LED slv16
in I_SWI slv16
in I_BTNRST_N slbit
in I_BTN slv5
out O_SEG_N slv8
out O_ANO_N slv8
in I_CTS_N slbit
out O_RGBLED0 slv3
in I_CLK100 slbit
out O_RTS_N slbit
out O_RGBLED1 slv3
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40