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W11 CPU core and support modules
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nexys4d_dram_dummy.vhd
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1-- $Id: nexys4d_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: nexys4d_dram_dummy - syn
7-- Description: nexys4d target (base; serport loopback, dram project)
8--
9-- Dependencies: -
10-- To test: tb_nexys4d_dram
11-- Target Devices: generic
12-- Tool versions: viv 2017.2; ghdl 0.34
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2018-12-30 1099 1.0 Initial version (derived from nexys4_dummy)
17------------------------------------------------------------------------------
18
19library ieee;
20use ieee.std_logic_1164.all;
21
22use work.slvtypes.all;
23
24entity nexys4d_dram_dummy is -- NEXYS 4DDR dummy (base+dram)
25 -- implements nexys4d_dram_aif
26 port (
27 I_CLK100 : in slbit; -- 100 MHz board clock
28 I_RXD : in slbit; -- receive data (board view)
29 O_TXD : out slbit; -- transmit data (board view)
30 O_RTS_N : out slbit; -- rx rts (board view; act.low)
31 I_CTS_N : in slbit; -- tx cts (board view; act.low)
32 I_SWI : in slv16; -- n4d switches
33 I_BTN : in slv5; -- n4d buttons
34 I_BTNRST_N : in slbit; -- n4d reset button
35 O_LED : out slv16; -- n4d leds
36 O_RGBLED0 : out slv3; -- n4d rgb-led 0
37 O_RGBLED1 : out slv3; -- n4d rgb-led 1
38 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
39 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
40 DDR2_DQ : inout slv16; -- dram: data in/out
41 DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
42 DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
43 DDR2_ADDR : out slv13; -- dram: address
44 DDR2_BA : out slv3; -- dram: bank address
45 DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
46 DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
47 DDR2_WE_N : out slbit; -- dram: write enable (act.low)
48 DDR2_CK_P : out slv1; -- dram: clock (diff-p)
49 DDR2_CK_N : out slv1; -- dram: clock (diff-n)
50 DDR2_CKE : out slv1; -- dram: clock enable
51 DDR2_CS_N : out slv1; -- dram: chip select (act.low)
52 DDR2_DM : out slv2; -- dram: data input mask
53 DDR2_ODT : out slv1 -- dram: on-die termination
54 );
56
57architecture syn of nexys4d_dram_dummy is
58
59begin
60
61 O_TXD <= I_RXD; -- loop back serport
63
64 O_LED <= I_SWI; -- mirror SWI on LED
65
66 O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
67 O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
68
69 O_ANO_N <= (others=>'1');
70 O_SEG_N <= (others=>'1');
71
72 DDR2_DQ <= (others=>'Z');
73 DDR2_DQS_P <= (others=>'Z');
74 DDR2_DQS_N <= (others=>'Z');
75 DDR2_ADDR <= (others=>'0');
76 DDR2_BA <= (others=>'0');
77 DDR2_RAS_N <= '1';
78 DDR2_CAS_N <= '1';
79 DDR2_WE_N <= '1';
80 DDR2_CK_P <= (others=>'0');
81 DDR2_CK_N <= (others=>'1');
82 DDR2_CKE <= (others=>'0');
83 DDR2_CS_N <= (others=>'1');
84 DDR2_DM <= (others=>'0');
85 DDR2_ODT <= (others=>'0');
86
87end syn;
std_logic_vector( 12 downto 0) slv13
Definition: slvtypes.vhd:45
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34