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W11 CPU core and support modules
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nexys4d_dummy.vhd
Go to the documentation of this file.
1
-- $Id: nexys4d_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: nexys4d_dummy - syn
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-- Description: nexys4d minimal target (base; serport loopback)
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--
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-- Dependencies: -
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-- To test: tb_nexys4d
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-- Target Devices: generic
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-- Tool versions: viv 2016.4; ghdl 0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2017-01-04 838 1.0 Initial version (derived from nexys4_dummy)
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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entity
nexys4d_dummy
is
-- NEXYS 4DDR dummy (base; loopback)
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-- implements nexys4d_aif
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port
(
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I_CLK100
:
in
slbit
;
-- 100 MHz board clock
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I_RXD
:
in
slbit
;
-- receive data (board view)
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O_TXD
:
out
slbit
;
-- transmit data (board view)
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O_RTS_N
:
out
slbit
;
-- rx rts (board view; act.low)
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I_CTS_N
:
in
slbit
;
-- tx cts (board view; act.low)
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I_SWI
:
in
slv16
;
-- n4d switches
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I_BTN
:
in
slv5
;
-- n4d buttons
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I_BTNRST_N
:
in
slbit
;
-- n4d reset button
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O_LED
:
out
slv16
;
-- n4d leds
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O_RGBLED0
:
out
slv3
;
-- n4d rgb-led 0
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O_RGBLED1
:
out
slv3
;
-- n4d rgb-led 1
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O_ANO_N
:
out
slv8
;
-- 7 segment disp: anodes (act.low)
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O_SEG_N
:
out
slv8
-- 7 segment disp: segments (act.low)
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)
;
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end
nexys4d_dummy
;
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architecture
syn
of
nexys4d_dummy
is
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begin
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O_TXD
<=
I_RXD
;
-- loop back serport
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O_RTS_N
<=
I_CTS_N
;
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O_LED
<=
I_SWI
;
-- mirror SWI on LED
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O_RGBLED0
<=
I_BTN
(
2
downto
0
)
;
-- mirror BTN on RGBLED
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O_RGBLED1
<=
not
I_BTNRST_N
&
I_BTN
(
4
)
&
I_BTN
(
3
)
;
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O_ANO_N
<=
(
others
=
>
'
1
'
)
;
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O_SEG_N
<=
(
others
=
>
'
1
'
)
;
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end
syn
;
nexys4d_dummy.syn
Definition:
nexys4d_dummy.vhd:43
nexys4d_dummy
Definition:
nexys4d_dummy.vhd:24
nexys4d_dummy.O_TXD
out O_TXD slbit
Definition:
nexys4d_dummy.vhd:29
nexys4d_dummy.I_RXD
in I_RXD slbit
Definition:
nexys4d_dummy.vhd:28
nexys4d_dummy.O_LED
out O_LED slv16
Definition:
nexys4d_dummy.vhd:35
nexys4d_dummy.I_SWI
in I_SWI slv16
Definition:
nexys4d_dummy.vhd:32
nexys4d_dummy.I_BTNRST_N
in I_BTNRST_N slbit
Definition:
nexys4d_dummy.vhd:34
nexys4d_dummy.I_BTN
in I_BTN slv5
Definition:
nexys4d_dummy.vhd:33
nexys4d_dummy.O_SEG_N
out O_SEG_N slv8
Definition:
nexys4d_dummy.vhd:40
nexys4d_dummy.O_ANO_N
out O_ANO_N slv8
Definition:
nexys4d_dummy.vhd:38
nexys4d_dummy.I_CTS_N
in I_CTS_N slbit
Definition:
nexys4d_dummy.vhd:31
nexys4d_dummy.O_RGBLED0
out O_RGBLED0 slv3
Definition:
nexys4d_dummy.vhd:36
nexys4d_dummy.I_CLK100
in I_CLK100 slbit
Definition:
nexys4d_dummy.vhd:27
nexys4d_dummy.O_RTS_N
out O_RTS_N slbit
Definition:
nexys4d_dummy.vhd:30
nexys4d_dummy.O_RGBLED1
out O_RGBLED1 slv3
Definition:
nexys4d_dummy.vhd:37
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv5
std_logic_vector( 4 downto 0) slv5
Definition:
slvtypes.vhd:37
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition:
slvtypes.vhd:35
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition:
slvtypes.vhd:40
bplib
nexys4d
tb
nexys4d_dummy.vhd
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