w11 - vhd 0.794
W11 CPU core and support modules
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ram_1swar_gen.vhd
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1-- $Id: ram_1swar_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ram_1swar_gen - syn
7-- Description: Single-Port RAM with with one synchronous write and one
8-- asynchronius read port (as distributed RAM).
9-- The code is inspired by Xilinx example rams_04.vhd. The
10-- 'ram_style' attribute is set to 'distributed', this will
11-- force in XST a synthesis as distributed RAM.
12--
13-- Dependencies: -
14-- Test bench: -
15-- Target Devices: generic Spartan, Virtex
16-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
17-- Revision History:
18-- Date Rev Version Comment
19-- 2011-11-08 422 1.0.2 now numeric_std clean
20-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
21-- 2007-06-03 45 1.0 Initial version
22--
23-- Some synthesis results:
24-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
25-- AWIDTH DWIDTH LUTl LUTm Comments
26-- 4 16 - 16 16*RAM16X1S
27-- 5 16 - 32 16*RAM32X1S
28-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
29------------------------------------------------------------------------------
30
31library ieee;
32use ieee.std_logic_1164.all;
33use ieee.numeric_std.all;
34
35use work.slvtypes.all;
36
37entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
38 generic (
39 AWIDTH : positive := 4; -- address port width
40 DWIDTH : positive := 16); -- data port width
41 port (
42 CLK : in slbit; -- clock
43 WE : in slbit; -- write enable
44 ADDR : in slv(AWIDTH-1 downto 0); -- address port
45 DI : in slv(DWIDTH-1 downto 0); -- data in port
46 DO : out slv(DWIDTH-1 downto 0) -- data out port
47 );
49
50
51architecture syn of ram_1swar_gen is
52 constant memsize : positive := 2**AWIDTH;
53 constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
54 type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
55 signal RAM : ram_type := (others=>datzero);
56
57 attribute ram_style : string;
58 attribute ram_style of RAM : signal is "distributed";
59
60begin
61
62 proc_clk: process (CLK)
63 begin
64 if rising_edge(CLK) then
65 if WE = '1' then
66 RAM(to_integer(unsigned(ADDR))) <= DI;
67 end if;
68 end if;
69 end process proc_clk;
70
71 DO <= RAM(to_integer(unsigned(ADDR)));
72
73end syn;
( memsize- 1 downto 0) slv( DWIDTH- 1 downto 0) ram_type
positive := 2** AWIDTH memsize
ram_type :=( others => datzero) RAM
slv( DWIDTH- 1 downto 0) :=( others => '0') datzero
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
in CLK slbit
in WE slbit
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31