32use ieee.std_logic_1164.
all;
33use ieee.numeric_std.
all;
62 proc_clk:
process (
CLK)
64 if rising_edge(CLK) then
( memsize- 1 downto 0) slv( DWIDTH- 1 downto 0) ram_type
positive := 2** AWIDTH memsize
ram_type :=( others => datzero) RAM
slv( DWIDTH- 1 downto 0) :=( others => '0') datzero
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)