w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
ram_1swsr_wfirst_gen.vhd
Go to the documentation of this file.
1-- $Id: ram_1swsr_wfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ram_1swsr_rfirst_gen - syn
7-- Description: Single-Port RAM with with one synchronous read/write port
8-- and 'read-through' semantics (as block RAM).
9-- The 'ram_style' attribute is set to 'block', this will
10-- force in XST a synthesis as block RAM.
11--
12-- Notes: For xst 8.1.03i: can be written with a signal or a shared
13-- variable declared at the architecture level. Use variable
14-- because this seemed better for simulation. Using a simple
15-- variable declared at process level leads to an array of
16-- registers and a big mux.
17--
18-- Dependencies: -
19-- Test bench: -
20-- Target Devices: generic Spartan, Virtex
21-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
22-- Revision History:
23-- Date Rev Version Comment
24-- 2011-11-08 422 1.0.4 now numeric_std clean
25-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
26-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
27-- 2008-03-02 122 1.0.1 change generic default for BRAM models
28-- 2007-06-03 45 1.0 Initial version
29------------------------------------------------------------------------------
30
31library ieee;
32use ieee.std_logic_1164.all;
33use ieee.numeric_std.all;
34
35use work.slvtypes.all;
36
37entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
38 generic (
39 AWIDTH : positive := 11; -- address port width
40 DWIDTH : positive := 9); -- data port width
41 port(
42 CLK : in slbit; -- clock
43 EN : in slbit; -- enable
44 WE : in slbit; -- write enable
45 ADDR : in slv(AWIDTH-1 downto 0); -- address port
46 DI : in slv(DWIDTH-1 downto 0); -- data in port
47 DO : out slv(DWIDTH-1 downto 0) -- data out port
48 );
50
51
52architecture syn of ram_1swsr_wfirst_gen is
53
54 constant memsize : positive := 2**AWIDTH;
55 constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
56 type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
57 shared variable sv_ram : ram_type := (others=>datzero);
58
59 attribute ram_style : string;
60 attribute ram_style of sv_ram : variable is "block";
61
62 signal R_DO : slv(DWIDTH-1 downto 0) := datzero;
63
64begin
65
66 proc_clk: process (CLK)
67 begin
68 if rising_edge(CLK) then
69 if EN = '1' then
70 if WE = '1' then
71 sv_ram(to_integer(unsigned(ADDR))) := DI;
72 end if;
73 R_DO <= sv_ram(to_integer(unsigned(ADDR)));
74 end if;
75 end if;
76 end process proc_clk;
77
78 DO <= R_DO;
79
80end syn;
81
( 0 to memsize- 1) slv( DWIDTH- 1 downto 0) ram_type
shared ram_type :=:=( others => datzero) sv_ram
positive := 2** AWIDTH memsize
slv( DWIDTH- 1 downto 0) :=( others => '0') datzero
slv( DWIDTH- 1 downto 0) := datzero R_DO
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31