32use ieee.std_logic_1164.
all;
33use ieee.numeric_std.
all;
66 proc_clk:
process (
CLK)
68 if rising_edge(CLK) then
( 0 to memsize- 1) slv( DWIDTH- 1 downto 0) ram_type
shared ram_type :=:=( others => datzero) sv_ram
positive := 2** AWIDTH memsize
slv( DWIDTH- 1 downto 0) :=( others => '0') datzero
slv( DWIDTH- 1 downto 0) := datzero R_DO
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)