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W11 CPU core and support modules
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ram_2swsr_rfirst_gen.vhd
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1-- $Id: ram_2swsr_rfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ram_2swsr_rfirst_gen - syn
7-- Description: Dual-Port RAM with with two synchronous read/write ports
8-- and 'read-before-write' semantics (as block RAM).
9-- The code is inspired by Xilinx example rams_16.vhd. The
10-- 'ram_style' attribute is set to 'block', this will
11-- force in XST a synthesis as block RAM.
12--
13-- Dependencies: -
14-- Test bench: -
15-- Target Devices: generic Spartan, Virtex
16-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
17-- Revision History:
18-- Date Rev Version Comment
19-- 2011-11-08 422 1.0.4 now numeric_std clean
20-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
21-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
22-- now initialize DO to all '0' at start
23-- 2008-03-02 122 1.0.1 change generic default for BRAM models
24-- 2007-06-03 45 1.0 Initial version
25------------------------------------------------------------------------------
26
27library ieee;
28use ieee.std_logic_1164.all;
29use ieee.numeric_std.all;
30
31use work.slvtypes.all;
32
33entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
34 generic (
35 AWIDTH : positive := 11; -- address port width
36 DWIDTH : positive := 9); -- data port width
37 port(
38 CLKA : in slbit; -- clock port A
39 CLKB : in slbit; -- clock port B
40 ENA : in slbit; -- enable port A
41 ENB : in slbit; -- enable port B
42 WEA : in slbit; -- write enable port A
43 WEB : in slbit; -- write enable port B
44 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
45 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
46 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
47 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
48 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
49 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
50 );
52
53
54architecture syn of ram_2swsr_rfirst_gen is
55 constant memsize : positive := 2**AWIDTH;
56 constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
57 type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
58 shared variable sv_ram : ram_type := (others=>datzero);
59
60 attribute ram_style : string;
61 attribute ram_style of sv_ram : variable is "block";
62
63 signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
64 signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
65
66begin
67
68 proc_clka: process (CLKA)
69 begin
70 if rising_edge(CLKA) then
71 if ENA = '1' then
72 R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
73 if WEA = '1' then
74 sv_ram(to_integer(unsigned(ADDRA))) := DIA;
75 end if;
76 end if;
77 end if;
78 end process proc_clka;
79
80 proc_clkb: process (CLKB)
81 begin
82 if rising_edge(CLKB) then
83 if ENB = '1' then
84 R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
85 if WEB = '1' then
86 sv_ram(to_integer(unsigned(ADDRB))) := DIB;
87 end if;
88 end if;
89 end if;
90 end process proc_clkb;
91
92 DOA <= R_DOA;
93 DOB <= R_DOB;
94
95end syn;
slv( DWIDTH- 1 downto 0) := datzero R_DOB
( 0 to memsize- 1) slv( DWIDTH- 1 downto 0) ram_type
shared ram_type :=:=( others => datzero) sv_ram
slv( DWIDTH- 1 downto 0) := datzero R_DOA
positive := 2** AWIDTH memsize
slv( DWIDTH- 1 downto 0) :=( others => '0') datzero
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31