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W11 CPU core and support modules
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s3board_dummy.vhd
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-- $Id: s3board_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: s3board_dummy - syn
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-- Description: s3board minimal target (base; serport loopback)
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--
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-- Dependencies: -
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-- To test: tb_s3board
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50
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-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy
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-- 2007-12-16 101 1.1.1 use _N for active low
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-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them
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-- 2007-09-23 85 1.0 Initial version
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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use
work.
s3boardlib
.
all
;
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entity
s3board_dummy
is
-- S3BOARD dummy (base; loopback)
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-- implements s3board_aif
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port
(
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I_CLK50
:
in
slbit
;
-- 50 MHz board clock
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I_RXD
:
in
slbit
;
-- receive data (board view)
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O_TXD
:
out
slbit
;
-- transmit data (board view)
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I_SWI
:
in
slv8
;
-- s3 switches
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I_BTN
:
in
slv4
;
-- s3 buttons
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O_LED
:
out
slv8
;
-- s3 leds
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O_ANO_N
:
out
slv4
;
-- 7 segment disp: anodes (act.low)
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O_SEG_N
:
out
slv8
;
-- 7 segment disp: segments (act.low)
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O_MEM_CE_N
:
out
slv2
;
-- sram: chip enables (act.low)
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O_MEM_BE_N
:
out
slv4
;
-- sram: byte enables (act.low)
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O_MEM_WE_N
:
out
slbit
;
-- sram: write enable (act.low)
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O_MEM_OE_N
:
out
slbit
;
-- sram: output enable (act.low)
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O_MEM_ADDR
:
out
slv18
;
-- sram: address lines
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IO_MEM_DATA
:
inout
slv32
-- sram: data lines
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)
;
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end
s3board_dummy
;
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architecture
syn
of
s3board_dummy
is
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begin
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O_TXD
<=
I_RXD
;
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SRAM :
s3_sram_dummy
-- connect SRAM
to
protection dummy
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port
map
(
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O_MEM_CE_N =>
O_MEM_CE_N
,
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O_MEM_BE_N =>
O_MEM_BE_N
,
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O_MEM_WE_N =>
O_MEM_WE_N
,
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O_MEM_OE_N =>
O_MEM_OE_N
,
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O_MEM_ADDR =>
O_MEM_ADDR
,
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IO_MEM_DATA =>
IO_MEM_DATA
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)
;
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end
syn
;
s3_sram_dummy
Definition:
s3_sram_dummy.vhd:25
s3board_dummy.syn
Definition:
s3board_dummy.vhd:48
s3board_dummy
Definition:
s3board_dummy.vhd:28
s3board_dummy.IO_MEM_DATA
inout IO_MEM_DATA slv32
Definition:
s3board_dummy.vhd:45
s3board_dummy.O_MEM_CE_N
out O_MEM_CE_N slv2
Definition:
s3board_dummy.vhd:39
s3board_dummy.I_CLK50
in I_CLK50 slbit
Definition:
s3board_dummy.vhd:31
s3board_dummy.O_TXD
out O_TXD slbit
Definition:
s3board_dummy.vhd:33
s3board_dummy.I_RXD
in I_RXD slbit
Definition:
s3board_dummy.vhd:32
s3board_dummy.O_MEM_WE_N
out O_MEM_WE_N slbit
Definition:
s3board_dummy.vhd:41
s3board_dummy.O_LED
out O_LED slv8
Definition:
s3board_dummy.vhd:36
s3board_dummy.O_MEM_ADDR
out O_MEM_ADDR slv18
Definition:
s3board_dummy.vhd:43
s3board_dummy.I_BTN
in I_BTN slv4
Definition:
s3board_dummy.vhd:35
s3board_dummy.O_SEG_N
out O_SEG_N slv8
Definition:
s3board_dummy.vhd:38
s3board_dummy.O_MEM_BE_N
out O_MEM_BE_N slv4
Definition:
s3board_dummy.vhd:40
s3board_dummy.O_MEM_OE_N
out O_MEM_OE_N slbit
Definition:
s3board_dummy.vhd:42
s3board_dummy.I_SWI
in I_SWI slv8
Definition:
s3board_dummy.vhd:34
s3board_dummy.O_ANO_N
out O_ANO_N slv4
Definition:
s3board_dummy.vhd:37
s3boardlib
Definition:
s3boardlib.vhd:38
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition:
slvtypes.vhd:36
slvtypes.slv18
std_logic_vector( 17 downto 0) slv18
Definition:
slvtypes.vhd:51
slvtypes.slv32
std_logic_vector( 31 downto 0) slv32
Definition:
slvtypes.vhd:59
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition:
slvtypes.vhd:40
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition:
slvtypes.vhd:34
bplib
s3board
tb
s3board_dummy.vhd
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