w11 - vhd 0.794
W11 CPU core and support modules
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s3board_dummy.vhd
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1-- $Id: s3board_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: s3board_dummy - syn
7-- Description: s3board minimal target (base; serport loopback)
8--
9-- Dependencies: -
10-- To test: tb_s3board
11-- Target Devices: generic
12-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
13-- Revision History:
14-- Date Rev Version Comment
15-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50
16-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy
17-- 2007-12-16 101 1.1.1 use _N for active low
18-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them
19-- 2007-09-23 85 1.0 Initial version
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24
25use work.slvtypes.all;
26use work.s3boardlib.all;
27
28entity s3board_dummy is -- S3BOARD dummy (base; loopback)
29 -- implements s3board_aif
30 port (
31 I_CLK50 : in slbit; -- 50 MHz board clock
32 I_RXD : in slbit; -- receive data (board view)
33 O_TXD : out slbit; -- transmit data (board view)
34 I_SWI : in slv8; -- s3 switches
35 I_BTN : in slv4; -- s3 buttons
36 O_LED : out slv8; -- s3 leds
37 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
38 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
39 O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
40 O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
41 O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
42 O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
43 O_MEM_ADDR : out slv18; -- sram: address lines
44 IO_MEM_DATA : inout slv32 -- sram: data lines
45 );
47
48architecture syn of s3board_dummy is
49
50begin
51
52 O_TXD <= I_RXD;
53
54 SRAM : s3_sram_dummy -- connect SRAM to protection dummy
55 port map (
56 O_MEM_CE_N => O_MEM_CE_N,
57 O_MEM_BE_N => O_MEM_BE_N,
58 O_MEM_WE_N => O_MEM_WE_N,
59 O_MEM_OE_N => O_MEM_OE_N,
60 O_MEM_ADDR => O_MEM_ADDR,
61 IO_MEM_DATA => IO_MEM_DATA
62 );
63
64end syn;
inout IO_MEM_DATA slv32
out O_MEM_CE_N slv2
in I_CLK50 slbit
out O_TXD slbit
in I_RXD slbit
out O_MEM_WE_N slbit
out O_LED slv8
out O_MEM_ADDR slv18
in I_BTN slv4
out O_SEG_N slv8
out O_MEM_BE_N slv4
out O_MEM_OE_N slbit
in I_SWI slv8
out O_ANO_N slv4
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 17 downto 0) slv18
Definition: slvtypes.vhd:51
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34