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Generated: 2023-02-09 |
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TMUCONV(1) Retro Project Manual TMUCONV(1) NAME tmuconv - convert w11a tmu output into human readable format SYNOPSIS tmuconv [OPTION]... FILE tmuconv --help DESCRIPTION Converts the output of the w11a trace and monitoring unit (tmu) into a human readable format. If no options are given, the default output is -t_id -t_vf. OPTIONS -dump dump all information. -cdump dump only changes relative to previous cycle. -emcancel show em 'cancel' cycles when -t_ib active. -t_id trace instruction decodes. -t_ru trace register updates. -t_ru06 trace register updates for r0-r5 and sp (subset of -t_ru). -t_em trace em transactions (external memory bus). em transactions that converted to an ib transaction are labeled 'cancel'. They are not shown when -t_ib is active and no -emcancel option is given. This gives the most readable output for -t_all. Each transaction is associated with type i instruction fetch v vector fetch or push m read modify write c control port access (often cdma) A blank type field means 'none of the above' and is used for all em transactions issued by instructions including index word and immediate value reads. The vector fetch transactions are further annotated for well known vector addresses. This is very helpful for the detection of interrupts. -t_emm trace only em transaction that are not type i or c and are not canceled (subset of -t_em). Useful in conjunction with -t_id because the information of the instruction fetch read is in- cluded in the -t_id output. -t_vf trace only vector fetch em transactions (subset of -t_em) -t_ib trace ib transactions (ibus cycles). em 'cancel' transactions are not shown unless the -emcancel option is given. -t_flow trace instruction flow, is equivalent to -t_id -t_ru06 -t_vf -t_fle trace instruction flow and show instruction related em transac- tions, is equivalent to -t_id -t_ru06 -t_emm -t_fli trace instruction flow and show ibus transactions, equivalent to -t_id -t_ru06 -t_vf -t_ib -t_flei combination of "-t_fle" and "-t_fli", is equivalent to -t_id -t_ru06 -t_emm -t_ib -t_all trace all, equivalent to -t_id -t_ru -t_em -t_ib -help print full help text and exit. TRACE OUTPUT FORMAT Each output line starts with the cycle number and the trace type. The format of the rest of the line depends on trace type. -t_id: the instruction decode trace gives - the PC of the instruction - the PSW at the beginning(!) of the instruction - the instruction word (as loaded into the instruction register) - the instruction in MACRO-11 syntax - the number of cycles of the previous(!) instruction cycle pc psw ireg code nc 71587 id 006054 000011 012410 mov (r4)+,(r0) (4) 71683 id 002146 000340 116767 movb nnn(pc),nnn(pc) (9) -t_ru: the register update trace gives - the byte update indicator - the register set (0 pr 1) - the register number (0 to 7) - the loaded data value - in case of a stack pointer update the values of kernel, supervisor and user stack pointers - in case of an R0-R5 update the values of all these six registers - the symbolic name of the register cycle b sr data 71578 ru 0 07 006102 pc 71649 ru 0 06 002000 002000*------ ------ ksp 71634 ru 0 04 010752 006110 006112 177776 010752 010752*010642 r04 -t_em: the memory transaction trace gives - the access type flag (values see -t_em descriprion) - the r/w flag - the byte enables - the memory address (as 22bit number) - the data written to memory - the data received from memory - four flag bits 'crwh' indicating cancel, read, write, and cache-hit - the number of extra wait cycles - in case of vector fetches and associated stack pushes some descrip- tive text cycle be addr wdat rdat crwh nc 11374 em w 11 00000004 000006 0010 (1) 52574 em r 11 00002164 177624 0101 (1) 86703 em mr 11 00003320 000000 0101 (1) 86705 em mw 11 00003320 000001 0010 (1) 87102 em vr 11 00000020 002222 0101 (1) VFETCH PC 020 IOT 87104 em vr 11 00000022 000340 0101 (1) VFETCH PS 87108 em vw 11 00001776 000004 0010 (1) VPUSH PS 87114 em vw 11 00001774 003324 0010 (5) VPUSH PC -t_ib: the ibus transaction trace gives - two flag bits 'cr' indicating console and remote access - two flag bits 'rm' indicating read/write and modify - the byte enables - the bus address (as 16bit number) - the data written to bus - the data received from bus - the acknowledge flag - the number of extra wait cycles - if known, the symbolic name of the register cycle cr rmbe addr wdat rdat a nc name 988 ib cr r 11 177500 000000 1 (0) ii.acr 52583 ib -- w 11 177570 000001 1 (0) sdreg 70729 ib -- r 11 177776 000004 1 (0) psw The w11 CPU starts a cache cycle for each read or write, and cancels the cache request when an ibus access is detected. These transactions are usually suppressed when -t_ib is active but are shown when -emcan- cel is given, resulting in output like 52582 em w 11 00177570 000001 cancel 1000 (1) 52583 ib -- w 11 177570 000001 1 (0) sdreg EXAMPLES tmuconv --t_id --t_em --t_ib tmu_ofile Produces an output with all instruction decodes and external memory interface and ibus transactions. The execution of a 'bisb #4,4(r4)' instruction which accesses the output CSR of a DL11 interface will look like 429 id 002002 000340 152764 bisb #nnn,nnn(r4) (5) 431 em r 01 00002004 000004 0100 (1) 433 em r 11 00002006 000004 0100 (1) 436 ib -- rm01 177564 000200 1 (0) to.csr 439 ib -- wm01 177564 000204 1 (0) to.csr and shows the ibus read-modify-write. tmuconv --t_all tmu_ofile Like above, in addition, also all register updates are shown. The execution of a 'cmp (r2),(r4)+' where r2 points to the psw will look like 934 id 003014 000011 021224 cmp (r2),(r4)+ (9) 937 ib -- r 11 177776 000011 1 (0) psw 939 ru 0 04 005676 003036 003040 177776 005700 005676*005570 r04 940 em r 11 00005674 000011 0101 (1) SEE ALSO ti_rri(1) AUTHOR Walter F.J. Mueller <W.F.J.Mueller@gsi.de> Retro Project 2023-01-08 TMUCONV(1)
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Generated: 2023-02-09 |
Generated by man2html V0.26
page hit count: 157 |
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