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Rw11CntlDEUNA.cpp
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1// $Id: Rw11CntlDEUNA.cpp 1186 2019-07-12 17:49:59Z mueller $
2// SPDX-License-Identifier: GPL-3.0-or-later
3// Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4//
5// Revision History:
6// Date Rev Version Comment
7// 2019-06-15 1164 0.5.10 adapt to new RtimerFd API
8// 2019-04-19 1133 0.5.9 use ExecWibr()
9// 2019-02-23 1114 0.5.8 use std::bind instead of lambda
10// 2018-12-19 1090 0.5.7 use RosPrintf(bool)
11// 2018-12-17 1087 0.5.6 use std::lock_guard instead of boost
12// 2018-12-15 1082 0.5.5 use lambda instead of boost::bind
13// 2018-12-09 1080 0.5.4 use HasVirt(); Virt() returns ref
14// 2018-12-08 1078 0.5.3 BUGFIX: Start(Tx|Rx)Ring, was broken in r1049
15// when fixing -Wunused-variable warnings
16// 2018-11-30 1075 0.5.2 use list-init
17// 2018-09-22 1048 0.5.1 BUGFIX: coverity (resource leak)
18// 2017-04-17 880 0.5 Initial version (minimal functions, 211bsd ready)
19// 2014-06-09 561 0.1 First draft
20// ---------------------------------------------------------------------------
21
26#include <string.h>
27#include <fcntl.h>
28#include <unistd.h>
29
30#include <sstream>
31#include <functional>
32
33#include "librtools/RosFill.hpp"
37#include "librtools/RlogMsg.hpp"
38#include "librtools/Rtools.hpp"
39
40#include "RethTools.hpp"
41
42#include "Rw11CntlDEUNA.hpp"
43
44using namespace std;
45using namespace std::placeholders;
46
52// all method definitions in namespace Retro
53namespace Retro {
54
55//------------------------------------------+-----------------------------------
56// constants definitions
57
58const uint16_t Rw11CntlDEUNA::kIbaddr;
59const int Rw11CntlDEUNA::kLam;
60
61const uint16_t Rw11CntlDEUNA::kPR0;
62const uint16_t Rw11CntlDEUNA::kPR1;
63const uint16_t Rw11CntlDEUNA::kPR2;
64const uint16_t Rw11CntlDEUNA::kPR3;
65
66const uint16_t Rw11CntlDEUNA::kProbeOff;
69
70const uint16_t Rw11CntlDEUNA::kPR0_M_SERI;
71const uint16_t Rw11CntlDEUNA::kPR0_M_PCEI;
72const uint16_t Rw11CntlDEUNA::kPR0_M_RXI;
73const uint16_t Rw11CntlDEUNA::kPR0_M_TXI;
74const uint16_t Rw11CntlDEUNA::kPR0_M_DNI;
75const uint16_t Rw11CntlDEUNA::kPR0_M_RCBI;
76const uint16_t Rw11CntlDEUNA::kPR0_M_USCI;
77const uint16_t Rw11CntlDEUNA::kPR0_M_INTR;
78const uint16_t Rw11CntlDEUNA::kPR0_M_INTE;
79const uint16_t Rw11CntlDEUNA::kPR0_M_RSET;
80const uint16_t Rw11CntlDEUNA::kPR0_M_BRST;
81const uint16_t Rw11CntlDEUNA::kPR0_M_PCMD;
82
83const uint16_t Rw11CntlDEUNA::kPR0_V_PCMDBP;
84const uint16_t Rw11CntlDEUNA::kPR0_B_PCMDBP;
85const uint16_t Rw11CntlDEUNA::kPR0_M_PDMDWB;
86const uint16_t Rw11CntlDEUNA::kPR0_M_PCWWB;
87
88const uint16_t Rw11CntlDEUNA::kPCMD_NOOP;
89const uint16_t Rw11CntlDEUNA::kPCMD_GETPCBB;
90const uint16_t Rw11CntlDEUNA::kPCMD_GETCMD;
91const uint16_t Rw11CntlDEUNA::kPCMD_SELFTST;
92const uint16_t Rw11CntlDEUNA::kPCMD_START;
93const uint16_t Rw11CntlDEUNA::kPCMD_BOOT;
94const uint16_t Rw11CntlDEUNA::kPCMD_PDMD;
95const uint16_t Rw11CntlDEUNA::kPCMD_HALT;
96const uint16_t Rw11CntlDEUNA::kPCMD_STOP;
97
98const uint16_t Rw11CntlDEUNA::kPR1_M_XPWR;
99const uint16_t Rw11CntlDEUNA::kPR1_M_ICAB;
100const uint16_t Rw11CntlDEUNA::kPR1_M_PCTO;
101const uint16_t Rw11CntlDEUNA::kPR1_M_DELUA;
102const uint16_t Rw11CntlDEUNA::kPR1_M_STATE;
103
104const uint16_t Rw11CntlDEUNA::kSTATE_RESET;
105const uint16_t Rw11CntlDEUNA::kSTATE_PLOAD;
106const uint16_t Rw11CntlDEUNA::kSTATE_READY;
107const uint16_t Rw11CntlDEUNA::kSTATE_RUN;
108const uint16_t Rw11CntlDEUNA::kSTATE_UHALT;
109const uint16_t Rw11CntlDEUNA::kSTATE_NHALT;
110const uint16_t Rw11CntlDEUNA::kSTATE_NUHALT;
111const uint16_t Rw11CntlDEUNA::kSTATE_PHALT;
112const uint16_t Rw11CntlDEUNA::kSTATE_SLOAD;
113
114const uint16_t Rw11CntlDEUNA::kPC0_M_FUNC;
115const uint16_t Rw11CntlDEUNA::kPC0_M_MBZ;
116
117const uint16_t Rw11CntlDEUNA::kFUNC_NOOP;
118const uint16_t Rw11CntlDEUNA::kFUNC_RDPA;
119const uint16_t Rw11CntlDEUNA::kFUNC_RPA;
120const uint16_t Rw11CntlDEUNA::kFUNC_WPA;
121const uint16_t Rw11CntlDEUNA::kFUNC_RMAL;
122const uint16_t Rw11CntlDEUNA::kFUNC_WMAL;
123const uint16_t Rw11CntlDEUNA::kFUNC_RRF;
124const uint16_t Rw11CntlDEUNA::kFUNC_WRF;
125const uint16_t Rw11CntlDEUNA::kFUNC_RCTR;
126const uint16_t Rw11CntlDEUNA::kFUNC_RCCTR;
127const uint16_t Rw11CntlDEUNA::kFUNC_RMODE;
128const uint16_t Rw11CntlDEUNA::kFUNC_WMODE;
129const uint16_t Rw11CntlDEUNA::kFUNC_RSTAT;
130const uint16_t Rw11CntlDEUNA::kFUNC_RCSTAT;
131const uint16_t Rw11CntlDEUNA::kFUNC_RSID;
132const uint16_t Rw11CntlDEUNA::kFUNC_WSID;
133
134const uint16_t Rw11CntlDEUNA::kSTAT_M_ERRS;
135const uint16_t Rw11CntlDEUNA::kSTAT_M_MERR;
136const uint16_t Rw11CntlDEUNA::kSTAT_M_BABL;
137const uint16_t Rw11CntlDEUNA::kSTAT_M_CERR;
138const uint16_t Rw11CntlDEUNA::kSTAT_M_TMOT;
139const uint16_t Rw11CntlDEUNA::kSTAT_M_RRNG;
140const uint16_t Rw11CntlDEUNA::kSTAT_M_TRNG;
141const uint16_t Rw11CntlDEUNA::kSTAT_M_PTCH;
142const uint16_t Rw11CntlDEUNA::kSTAT_M_RRAM;
143const uint16_t Rw11CntlDEUNA::kSTAT_M_RREV;
144
145const uint16_t Rw11CntlDEUNA::kMODE_M_PROM;
146const uint16_t Rw11CntlDEUNA::kMODE_M_ENAL;
147const uint16_t Rw11CntlDEUNA::kMODE_M_DRDC;
148const uint16_t Rw11CntlDEUNA::kMODE_M_TPAD;
149const uint16_t Rw11CntlDEUNA::kMODE_M_ECT;
150const uint16_t Rw11CntlDEUNA::kMODE_M_DMNT;
151const uint16_t Rw11CntlDEUNA::kMODE_M_INTL;
152const uint16_t Rw11CntlDEUNA::kMODE_M_DTCR;
153const uint16_t Rw11CntlDEUNA::kMODE_M_LOOP;
154const uint16_t Rw11CntlDEUNA::kMODE_M_HDPX;
157
158const uint16_t Rw11CntlDEUNA::kTXR2_M_OWN;
159const uint16_t Rw11CntlDEUNA::kTXR2_M_ERRS;
160const uint16_t Rw11CntlDEUNA::kTXR2_M_MTCH;
161const uint16_t Rw11CntlDEUNA::kTXR2_M_MORE;
162const uint16_t Rw11CntlDEUNA::kTXR2_M_ONE;
163const uint16_t Rw11CntlDEUNA::kTXR2_M_DEF;
164const uint16_t Rw11CntlDEUNA::kTXR2_M_STF;
165const uint16_t Rw11CntlDEUNA::kTXR2_M_ENF;
166const uint16_t Rw11CntlDEUNA::kTXR2_M_SEGB;
167const uint16_t Rw11CntlDEUNA::kTXR3_M_BUFL;
168const uint16_t Rw11CntlDEUNA::kTXR3_M_UBTO;
169const uint16_t Rw11CntlDEUNA::kTXR3_M_UFLO;
170const uint16_t Rw11CntlDEUNA::kTXR3_M_LCOL;
171const uint16_t Rw11CntlDEUNA::kTXR3_M_LCAR;
172const uint16_t Rw11CntlDEUNA::kTXR3_M_RTRY;
173const uint16_t Rw11CntlDEUNA::kTXR3_M_TDR;
174
175const uint16_t Rw11CntlDEUNA::kRXR2_M_OWN;
176const uint16_t Rw11CntlDEUNA::kRXR2_M_ERRS;
177const uint16_t Rw11CntlDEUNA::kRXR2_M_FRAM;
178const uint16_t Rw11CntlDEUNA::kRXR2_M_OFLO;
179const uint16_t Rw11CntlDEUNA::kRXR2_M_CRC;
180const uint16_t Rw11CntlDEUNA::kRXR2_M_STF;
181const uint16_t Rw11CntlDEUNA::kRXR2_M_ENF;
182const uint16_t Rw11CntlDEUNA::kRXR2_M_SEGB;
183const uint16_t Rw11CntlDEUNA::kRXR3_M_BUFL;
184const uint16_t Rw11CntlDEUNA::kRXR3_M_UBTO;
185const uint16_t Rw11CntlDEUNA::kRXR3_M_NCHN;
186const uint16_t Rw11CntlDEUNA::kRXR3_M_OVRN;
187const uint16_t Rw11CntlDEUNA::kRXR3_M_MLEN;
188
189const uint32_t Rw11CntlDEUNA::kUBA_M;
190const uint32_t Rw11CntlDEUNA::kUBAODD_M;
191const uint16_t Rw11CntlDEUNA::kDimMcast;
192const uint16_t Rw11CntlDEUNA::kDimCtrDeuna;
193const uint16_t Rw11CntlDEUNA::kDimCtrDelua;
194const uint16_t Rw11CntlDEUNA::kDimCtr;
195
196//------------------------------------------+-----------------------------------
198
200 : Rw11CntlBase<Rw11UnitDEUNA,1>("deuna"),
201 fPC_rdpr0(0),
202 fPC_rdpcb(0),
203 fPC_lapcb(0),
204 fPC_rdtxdsccur(0),
205 fPC_latxdsccur(0),
206 fPC_rdtxdscnxt(0),
207 fPC_latxdscnxt(0),
208 fPC_rdrxdsccur(0),
209 fPC_larxdsccur(0),
210 fPC_rdrxdscnxt(0),
211 fPcbbValid(false),
212 fPcbb(0),
213 fPcb{},
214 fRingValid(false),
215 fTxRingBase(0),
216 fTxRingSize(0),
217 fTxRingELen(0),
218 fRxRingBase(0),
219 fRxRingSize(0),
220 fRxRingELen(0),
221 fMacDefault(RethTools::String2Mac("08:00:2b:00:00:00")),
222 fPr0Last(0),
223 fPr1Pcto(false),
224 fPr1Delua(false),
225 fPr1State(kSTATE_RESET),
226 fRunning(false),
227 fMode(0),
228 fStatus(0),
229 fTxRingIndex(0),
230 fRxRingIndex(0),
231 fTxDscCurPC{},
232 fTxDscNxtPC{},
233 fRxDscCurPC{},
234 fRxDscNxtPC{},
235 fTxRingState(kStateTxIdle),
236 fTxDscCur{},
237 fTxDscNxt{},
238 fTxBuf(),
239 fTxBufOffset(0),
240 fRxRingState(kStateRxIdle),
241 fRxDscCur{},
242 fRxDscNxt{},
243 fRxPollTime(0.01),
244 fRxQueLimit(1000),
245 fRxPollTimer("Rw11CntlDEUNA::fRxPollTimer."),
246 fRxBufQueue(),
247 fRxBufCurr(),
248 fRxBufOffset(0)
249{
250 // must be here because Units have a back-ptr (not available at Rw11CntlBase)
251 fspUnit[0].reset(new Rw11UnitDEUNA(this, 0)); // single unit controller
252
253 ClearMacList();
254 ClearCtr();
255
256 // setup fStats
257 fStats.Define(kStatNPcmdNoop , "NPcmdNoop" , "pcmd NOOP (spurious)");
258 fStats.Define(kStatNPcmdGetpcbb, "NPcmdGetpcbb", "pcmd GETPCBB");
259 fStats.Define(kStatNPcmdGetcmd , "NPcmdGetcmd" , "pcmd GETCMD");
260 fStats.Define(kStatNPcmdSelftst, "NPcmdSelftst", "pcmd SELFTST");
261 fStats.Define(kStatNPcmdStart , "NPcmdStart" , "pcmd START");
262 fStats.Define(kStatNPcmdPdmd , "NPcmdPdmd" , "pcmd PDMD");
263 fStats.Define(kStatNPcmdStop , "NPcmdStop" , "pcmd STOP");
264 fStats.Define(kStatNPcmdHalt , "NPcmdHalt" , "pcmd HALT");
265 fStats.Define(kStatNPcmdRsrvd , "NPcmdRsrvd" , "pcmd reserved");
266 fStats.Define(kStatNPcmdUimpl , "NPcmdUimpl" , "pcmd not implemented");
267 fStats.Define(kStatNPcmdWBPdmd , "NPcmdWBPdmd" , "pcmd write w/ busy: pdmd");
268 fStats.Define(kStatNPcmdWBOther, "NPcmdWBOther", "pcmd write w/ busy: other");
269 fStats.Define(kStatNPdmdRestart, "NPdmdRestart", "pcmd pdmd restart");
270 fStats.Define(kStatNFuncNoop , "NFuncNoop" , "func NOOP");
271 fStats.Define(kStatNFuncRdpa , "NFuncRdpa" , "func RDPA");
272 fStats.Define(kStatNFuncRpa , "NFuncRpa" , "func PRA");
273 fStats.Define(kStatNFuncWpa , "NFuncWpa" , "func WPA");
274 fStats.Define(kStatNFuncRmal , "NFuncRmal" , "func RMAL");
275 fStats.Define(kStatNFuncWmal , "NFuncWmal" , "func WMAL");
276 fStats.Define(kStatNFuncRrf , "NFuncRrf" , "func RRF");
277 fStats.Define(kStatNFuncWrf , "NFuncWrf" , "func WRF");
278 fStats.Define(kStatNFuncRctr , "NFuncRctr" , "func RCTR");
279 fStats.Define(kStatNFuncRcctr , "NFuncRcctr" , "func RCCTR");
280 fStats.Define(kStatNFuncRmode , "NFuncRmode" , "func RMODE");
281 fStats.Define(kStatNFuncWmode , "NFuncWmode" , "func WMODE");
282 fStats.Define(kStatNFuncRstat , "NFuncRstat" , "func RSTAT");
283 fStats.Define(kStatNFuncRcstat , "NFuncRcstat" , "func RCSTAT");
284 fStats.Define(kStatNFuncRsid , "NFuncRsid" , "func RSID");
285 fStats.Define(kStatNFuncWsid , "NFuncWsid" , "func WSID");
286 fStats.Define(kStatNFuncUimpl , "NFuncUimpl" , "func not implemented");
287 fStats.Define(kStatNRxFraSeen , "NRxFraSeen" , "in frames seen");
288 fStats.Define(kStatNRxFraFDst , "NRxFraFDst" , "in frames match dst mac");
289 fStats.Define(kStatNRxFraFBcast, "NRxFraFBcast", "in frames match bcast");
290 fStats.Define(kStatNRxFraFMcast, "NRxFraFMcast", "in frames match mcast");
291 fStats.Define(kStatNRxFraFProm , "NRxFraFProm" , "in frames promiscous");
292 fStats.Define(kStatNRxFraFUDrop, "NRxFraFUDrop", "in frames drop miss mac");
293 fStats.Define(kStatNRxFraFMDrop, "NRxFraFMDrop", "in frames drop miss mcast");
294 fStats.Define(kStatNRxFraQLDrop, "NRxFraQLDrop", "in frames drop drop");
295 fStats.Define(kStatNRxFraNRDrop, "NRxFraNRDrop", "in frames drop not running");
296 fStats.Define(kStatNRxFra , "NRxFra" , "rcvd frames");
297 fStats.Define(kStatNRxFraMcast , "NRxFraMcast" , "rcvd bcast+mcast frames");
298 fStats.Define(kStatNRxFraBcast , "NRxFraBcast" , "rcvd bcast frames");
299 fStats.Define(kStatNRxByt , "NRxByt" , "rcvd bytes");
300 fStats.Define(kStatNRxBytMcast , "NRxBytMcast" , "rcvd mcast bytes");
301 fStats.Define(kStatNRxFraLoInt , "NRxFraLoInt" , "lost frames int err ");
302 fStats.Define(kStatNRxFraLoBuf , "NRxFraLoBuf" , "lost frames buffer");
303 fStats.Define(kStatNRxFraPad , "NRxFraPad" , "rcvd padded frames");
304 fStats.Define(kStatNTxFra , "NTxFra" , "xmit frames");
305 fStats.Define(kStatNTxFraMcast , "NTxFraMcast" , "xmit bcast+mcast frames");
306 fStats.Define(kStatNTxFraBcast , "NTxFraBcast" , "xmit bcast frames");
307 fStats.Define(kStatNTxByt , "NTxByt" , "xmit bytes");
308 fStats.Define(kStatNTxBytMcast , "NTxBytMcast" , "xmit mcast bytes");
309 fStats.Define(kStatNTxFraAbort , "NTxFraAbort" , "xmit aborted frames");
310 fStats.Define(kStatNTxFraPad , "NTxFraPad" , "xmit padded frames");
311 fStats.Define(kStatNFraLoop , "NFraLoop" , "loopback frames");
312}
313
314//------------------------------------------+-----------------------------------
316
318{}
319
320//------------------------------------------+-----------------------------------
322
323void Rw11CntlDEUNA::Config(const std::string& name, uint16_t base, int lam)
324{
325 ConfigCntl(name, base, lam, kProbeOff, kProbeInt, kProbeRem);
326 return;
327}
328
329//------------------------------------------+-----------------------------------
331
333{
334 if (fStarted || fLam<0 || !fEnable || !fProbe.Found())
335 throw Rexception("Rw11CntlDEUNA::Start",
336 "Bad state: started, no lam, not enabled, not found");
337
338 // add device register address ibus and rbus mappings
339 // done here because now Cntl bound to Cpu and Cntl probed
340 Cpu().AllIAddrMapInsert(Name()+".pr0", Base() + kPR0);
341 Cpu().AllIAddrMapInsert(Name()+".pr1", Base() + kPR1);
342 Cpu().AllIAddrMapInsert(Name()+".pr2", Base() + kPR2);
343 Cpu().AllIAddrMapInsert(Name()+".pr3", Base() + kPR3);
344
345 // setup primary info clist
347
348 // ensure unit status is initialized
350 UnitSetupAll();
351
352 // add attn handler
354 uint16_t(1)<<fLam, this);
355 fStarted = true;
356
357 return;
358}
359
360//------------------------------------------+-----------------------------------
362
363void Rw11CntlDEUNA::UnitSetup(size_t /*ind*/)
364{
366 // FIXME_code !!! Is that all ???
367 return;
368}
369
370//------------------------------------------+-----------------------------------
372
373void Rw11CntlDEUNA::SetType(const std::string& type)
374{
375 if (fPr1State != kSTATE_READY || fspUnit[0]->HasVirt())
376 throw Rexception("Rw11CntlDEUNA::SetType",
377 string("Bad state: not in READY state or attached"));
378
379 if (type == "deuna") {
380 fPr1Delua = false;
381 } else if (type == "delua") {
382 fPr1Delua = true;
383 } else {
384 throw Rexception("Rw11CntlDEUNA::SetType",
385 string("Bad args: only deuna or delua supported"));
386 }
387 fType = type;
388 UnitSetup(0);
389 return;
390}
391
392//------------------------------------------+-----------------------------------
394// allow xx:xx:xx:xx:xx:xx
395// random --> random mac, with 1st bit=0; 2nd bit=1 (LAA)
396// dec:xx:xx:xx --> 08:00:0b:xx:xx:xx --> DEC OUI
397// retro::xx --> 52:65:74:72:6f:xx --> ascii 'Retro'
398// 'R' = 52 -> 2nd bit = 1 -> locally administered address
399
400void Rw11CntlDEUNA::SetMacDefault(const std::string& mac)
401{
402 string machex = mac;
403 uint64_t bmac;
404 const uint64_t macbit1 = 0x1;
405 const uint64_t macbit2 = 0x2;
406
407 if (mac == "random") {
408 int fd = ::open("/dev/urandom",O_RDONLY);
409 if (fd < 0)
410 throw Rexception("Rw11CntlDEUNA::SetMacDefault",
411 "open() for '/dev/urandom' failed: ", errno);
412
413 if (::read(fd, &bmac, sizeof(bmac)) != sizeof(bmac)) {
414 int rd_errno = errno;
415 ::close(fd);
416 throw Rexception("Rw11CntlDEUNA::SetMacDefault",
417 "read() for '/dev/random' failed: ", rd_errno);
418 }
419 bmac &= ~macbit1; // ensure bcast bit is clear
420 bmac |= macbit2; // ensure laa bit is set
421 ::close(fd);
422
423 } else {
424 if (mac.substr(0,4) == "dec:") {
425 machex = "08:00:0b:"; // DEC OUI
426 machex += mac.substr(4);
427 } else if (mac.substr(0,6) == "retro:") {
428 machex = "52:65:74:72:6f:"; // ascii 'Retro'; 52 -> LAA
429 machex += mac.substr(6);
430 }
431
432 bmac = RethTools::String2Mac(machex);
433 }
434
435 if (bmac & macbit1)
436 throw Rexception("Rw11CntlDEUNA::SetMacDefault",
437 string("Bad args: mcast address given, lsb not 0"));
438 if (fPr1State == kSTATE_READY && // if not running
439 (!fspUnit[0]->HasVirt()) && // and not attached
440 fMacList[0] == fMacDefault) { // and old pa was old dpa
441 fMacList[0] = bmac; // update also pa !
442 }
443 fMacDefault = bmac; // and always dpa !
444 return;
445}
446
447//------------------------------------------+-----------------------------------
449
451{
452 if (!time.IsPositive())
453 throw Rexception("Rw11CntlDEUNA::SetRxPollTime",
454 string("Bad args: time <= 0"));
455 fRxPollTime = time;
456 return;
457}
458
459//------------------------------------------+-----------------------------------
461
463{
464 if (rxqlim <= 0)
465 throw Rexception("Rw11CntlDEUNA::SetRxQueLimit",
466 string("Bad args: rxqlim <= 0"));
467 fRxQueLimit = rxqlim;
468 return;
469}
470
471//--------------------------------------+-----------------------------------
473
474std::string Rw11CntlDEUNA::MacDefault() const
475{
477}
478
479//--------------------------------------+-----------------------------------
481
482const char* Rw11CntlDEUNA::MnemoPcmd(uint16_t pcmd) const
483{
484 static const char* mnemopcmd[16] = {"noop ","getpcb","getcmd","slftst",
485 "start ","boot ","rsrv06","rsrv07",
486 "pdmd ","rsrv11","rsrv12","rsrv13",
487 "rsrv14","rsrv15","halt ","stop "};
488 if (pcmd >= 16) return "??????";
489 return mnemopcmd[pcmd];
490}
491
492//--------------------------------------+-----------------------------------
494
495const char* Rw11CntlDEUNA::MnemoFunc(uint16_t func) const
496{
497 static const char* mnemofunc[32] = {"noop ","uimp01","rdpa ","noop03",
498 "rpa ","wpa ","rmal ","wmal ",
499 "rrf ","wrf ","rctr ","rcctr ",
500 "rmode ","wmode ","rstat ","rcstat",
501 "uimp20","uimp21","rsid ","wsid ",
502 "uimp24","uimp25","uimp26","uimp27",
503 "uimp30","uimp31","uimp32","uimp33",
504 "uimp34","uimp35","uimp36","uimp37"};
505 if (func >= 32) return "??????";
506 return mnemofunc[func];
507}
508
509//--------------------------------------+-----------------------------------
511
512const char* Rw11CntlDEUNA::MnemoState(uint16_t state) const
513{
514 static const char* mnemostate[16] = {"reset ","pload ","ready ","run ",
515 "rsrv04","uhalt ","nhalt ","nuhalt",
516 "phalt ","rsrv11","rsrv12","rsrv13",
517 "rsrv14","rsrv15","rsrv16","sload "};
518 if (state >= 16) return "??????";
519 return mnemostate[state];
520}
521
522//------------------------------------------+-----------------------------------
524
526{
527 // lock connect to protect rxqueue
528 lock_guard<RlinkConnect> lock(Connect());
529
531 if (!Running()) { // drop if not running
533 return true;
534 }
535
536 uint64_t macdst = pbuf->MacDestination();
537 int matchdst = MacFilter(macdst);
538
539 if (matchdst < 0) { // not matched ?
540 if (fMode & kMODE_M_PROM) { // promiscous mode
541 fStats.Inc(kStatNRxFraFProm); // count and accept
542 } else { // otherwise drop
543 if (matchdst & 0x1) { // mcast address
545 } else {
547 }
548 if (fTraceLevel>1) {
549 RlogMsg lmsg(LogFile());
550 lmsg << "-I " << Name() << ": fdrop " << pbuf->FrameInfo() << endl;
551 }
552 return true;
553 }
554 } else { // machted
555 if (matchdst == 0) {
557 } else if (matchdst == 1) {
559 } else {
561 }
562 }
563
564 if (fRxBufQueue.size() >= fRxQueLimit) { // drop if queue too long
566 if (fTraceLevel>0) {
567 RlogMsg lmsg(LogFile());
568 lmsg << "-I " << Name() << ": qdrop " << pbuf->FrameInfo() << endl;
569 }
570 return true;
571 }
572
573 fRxBufQueue.push_back(pbuf);
574
575 // FIXME_code: can we (should we) use last cached dscs ???
577
578 return true;
579}
580
581//------------------------------------------+-----------------------------------
583
584void Rw11CntlDEUNA::Dump(std::ostream& os, int ind, const char* text,
585 int detail) const
586{
587 // lock connect to protect, e.g fRxBufQueue access
588 lock_guard<RlinkConnect> lock(Connect());
589
590 RosFill bl(ind);
591 os << bl << (text?text:"--") << "Rw11CntlDEUNA @ " << this << endl;
592 os << bl << " fPC_rdpr0: " << fPC_rdpr0 << endl;
593 os << bl << " fPC_rdpcb: " << fPC_rdpcb << endl;
594 os << bl << " fPC_lapcb: " << fPC_lapcb << endl;
595 os << bl << " fPC_rdtxdsccur: " << fPC_rdtxdsccur << endl;
596 os << bl << " fPC_latxdsccur: " << fPC_latxdsccur << endl;
597 os << bl << " fPC_rdtxdscnxt: " << fPC_rdtxdscnxt << endl;
598 os << bl << " fPC_latxdscnxt: " << fPC_latxdscnxt << endl;
599 os << bl << " fPC_rdrxdsccur: " << fPC_rdrxdsccur << endl;
600 os << bl << " fPC_larxdsccur: " << fPC_larxdsccur << endl;
601 os << bl << " fPC_rdrxdscnxt: " << fPC_rdrxdscnxt << endl;
602 os << bl << " fPcbbValid: " << RosPrintf(fPcbbValid) << endl;
603 os << bl << " fPcbb: " << RosPrintf(fPcbb,"o0", 6) << endl;
604 os << bl << " fPcb: ";
605 for (auto& v : fPcb) os << " " << RosPrintf(v,"o0", 6);
606 os << endl;
607
608 os << bl << " fRingValid: " << RosPrintf(fRingValid) << endl;
609 os << bl << " fTxRing format: " << RosPrintf(fTxRingBase,"o0", 7)
610 << "," << RosPrintf(fTxRingSize,"d", 3)
611 << "," << RosPrintf(fTxRingELen,"d", 3) << endl;
612 os << bl << " fRxRing format: " << RosPrintf(fRxRingBase,"o0", 7)
613 << "," << RosPrintf(fRxRingSize,"d", 3)
614 << "," << RosPrintf(fRxRingELen,"d", 3) << endl;
615
616 os << bl << " fMacDefault: "
617 << RosPrintf(fMacDefault,"x0",12) << " "
619 os << bl << " fMacList[0]: "
620 << RosPrintf(fMacList[0],"x0",12) << " "
621 << RethTools::Mac2String(fMacList[0]) << endl;
622 os << bl << " fMacList[1]: "
623 << RosPrintf(fMacList[1],"x0",12) << " "
624 << RethTools::Mac2String(fMacList[1]) << endl;
625 os << bl << " fMacastCnt: " << RosPrintf(fMcastCnt,"d", 2) << endl;
626 for (int i=0; i<fMcastCnt; i++) {
627 os << bl << " fMacList[" << RosPrintf(i,"d",2) << "]: "
628 << RosPrintf(fMacList[2+i],"x0",12) << " "
629 << RethTools::Mac2String(fMacList[2+i]) << endl;
630 }
631
632 os << bl << " fPr0Last*: " << RosPrintf(fPr0Last,"o0", 6) << endl;
633 os << bl << " fPr1*: "
634 << " Pcto=" << RosPrintf(fPr1Pcto)
635 << " Delua=" << RosPrintf(fPr1Delua)
636 << " State=" << RosPrintf(fPr1State,"o0", 2) << ":" << MnemoState(fPr1State)
637 << " GetPr1()=" << RosPrintf(GetPr1(),"o0", 6) << endl;
638 os << bl << " fRunning: " << RosPrintf(fRunning) << endl;
639 os << bl << " fMode: " << RosPrintf(fMode,"o0", 6) << endl;
640 os << bl << " fStatus: " << RosPrintf(fStatus,"o0", 6) << endl;
641
642 os << bl << " fTxRingIndex: " << RosPrintf(fTxRingIndex,"d", 3) << endl;
643 os << bl << " fRxRingIndex: " << RosPrintf(fRxRingIndex,"d", 3) << endl;
644 os << bl << " fTxDscCurPC: " << RingDsc2String(fTxDscCurPC,'t') << endl;
645 os << bl << " fTxDscNxtPC: " << RingDsc2String(fTxDscNxtPC,'t') << endl;
646 os << bl << " fRxDscCurPC: " << RingDsc2String(fRxDscCurPC,'r') << endl;
647 os << bl << " fRxDscNxtPC: " << RingDsc2String(fRxDscNxtPC,'r') << endl;
648 os << bl << " fTxRingState: " << fTxRingState << endl;
649 os << bl << " fTxDscCur: " << RingDsc2String(fTxDscCur,'t') << endl;
650 os << bl << " fTxDscNxt: " << RingDsc2String(fTxDscNxt,'t') << endl;
651 fTxBuf.Dump(os, ind+2, "fTxBuf:", detail);
652 os << bl << " fRxRingState: " << fRxRingState << endl;
653 os << bl << " fRxDscCur: " << RingDsc2String(fRxDscCur,'r') << endl;
654 os << bl << " fRxDscNxt: " << RingDsc2String(fRxDscNxt,'r') << endl;
655
656 os << bl << " fRxPollTime: " << fRxPollTime << endl;
657 os << bl << " fRxQueLimit: " << RosPrintf(fRxQueLimit,"d", 4) << endl;
658 os << bl << " fRxPollTimer: " << fRxPollTimer.Fd() << endl;
659 size_t rxquesize = fRxBufQueue.size();
660 os << bl << " fRxBufQueue.size: " << RosPrintf(rxquesize,"d", 4) << endl;
661 for (size_t i=0; i<rxquesize; i++) {
662 os << bl << " fRxBufQueue[" << RosPrintf(i,"d", 4)
663 << "]: " << fRxBufQueue[i]->FrameInfo() << endl;
664 }
665 if (fRxBufCurr) {
666 fRxBufCurr->Dump(os, ind+2, "fRxBufCurr:", detail);
667 } else {
668 os << bl << " fRxBufCurr: " << "null" << endl;
669 }
670 os << bl << " fCtrTimeCleared: "
671 << RosPrintf(fCtrTimeCleared.Age(CLOCK_MONOTONIC),"f",10,2) << endl;
672 os << bl << " fCtrRxFra: "
673 << RosPrintf(fCtrRxFra,"d",10) << endl;
674 os << bl << " fCtrRxFraMcast: "
675 << RosPrintf(fCtrRxFraMcast,"d",10) << endl;
676 os << bl << " fCtrRxByt: "
677 << RosPrintf(fCtrRxByt,"d",10) << endl;
678 os << bl << " fCtrRxBytMcast: "
679 << RosPrintf(fCtrRxBytMcast,"d",10) << endl;
680 os << bl << " fCtrRxFraLoInt: "
681 << RosPrintf(fCtrRxFraLoInt,"d",10) << endl;
682 os << bl << " fCtrRxFraLoBuf: "
683 << RosPrintf(fCtrRxFraLoBuf,"d",10) << endl;
684 os << bl << " fCtrTxFra: "
685 << RosPrintf(fCtrTxFra,"d",10) << endl;
686 os << bl << " fCtrTxFraMcast: "
687 << RosPrintf(fCtrTxFraMcast,"d",10) << endl;
688 os << bl << " fCtrTxByt: "
689 << RosPrintf(fCtrTxByt,"d",10) << endl;
690 os << bl << " fCtrTxBytMcast: "
691 << RosPrintf(fCtrTxBytMcast,"d",10) << endl;
692 os << bl << " fCtrTxFraAbort: "
693 << RosPrintf(fCtrTxFraAbort,"d",10) << endl;
694 os << bl << " fCtrFramesLoop: "
695 << RosPrintf(fCtrFraLoop,"d",10) << endl;
696 Rw11CntlBase<Rw11UnitDEUNA,1>::Dump(os, ind, " ^", detail);
697 return;
698}
699
700//--------------------------------------+-----------------------------------
702
703// summary of log entry
704// handler lines
705// -I xua: cmd pr0=oooooo rset=b brst=b
706// -I xua: cmd pr0=000110 cmd=......
707// -I xua: cmd pr0=000110 cmd=pdmd t00,OSE,OSE r00,OSE,OSE
708// -I xua: cmd pr0=oooooo cmd=getcmd fu=...... udbb=oooooo
709// -I xua: txr t00 < dddd,oooooo,dddd; bbbbbbbb,bbbb: OSE, ...
710// -I xua: snd 00:00:00:00:00:00 > 00:00:00:00:00:00 typ: xxxx len: dddd
711// command specific lines
712// -I xua: GETPCBB: oooooo
713// -I xua: RPA: 08:00:2b:00:00:00
714// -I xua: WRF: tx base=oooooo size=dd elen=dd; rx base=oooooo size=dd elen=dd
715// -I xua: WMODE: mode=oooooo
716
717
719{
721
722 Rw11Cpu& cpu = Cpu();
723 if (fPC_rdtxdsccur > 0) { // txdsc read update, if setup
732 }
733
735 // FIXME_code: handle pcb and txdsc read errors ...
736
737 fPr0Last = fPrimClist[fPC_rdpr0].Data();
738
739 bool rset = fPr0Last & kPR0_M_RSET;
740 bool brst = fPr0Last & kPR0_M_BRST;
741 uint16_t pcmd = (fPr0Last>>kPR0_V_PCMDBP) & kPR0_B_PCMDBP;
742
743 // check for pcmd write while busy
744 if (fPr0Last & kPR0_M_PCWWB) {
745 uint16_t pcmdwwb = fPr0Last & kPR0_M_PCMD;
746 if (pcmdwwb == kPCMD_PDMD) {
748 } else {
750 RlogMsg lmsg(LogFile());
751 lmsg << "-E " << Name() << ": pcmd write w/ busy"
752 << " pr0=" << RosPrintBvi(fPr0Last,8)
753 << " pcmd-1st=" << MnemoPcmd(pcmd)
754 << " pcmd-2nd=" << MnemoPcmd(pcmdwwb);
755 }
756 }
757 // check for pcmd pdmd while busy restarts
758 if (fPr0Last & kPR0_M_PDMDWB) {
760 }
761
762 RlinkCommandList clist;
763
764 fPr1Pcto = false;
765 uint16_t pr0out = 0;
766
767 // handle bus and software reset: stop runnig, poll for RingHandler run-down
768 if (rset || brst) {
769 if (fTraceLevel>0) {
770 RlogMsg lmsg(LogFile());
771 lmsg << "-I " << Name() << ": cmd"
772 << " pr0=" << RosPrintBvi(fPr0Last,8)
773 << " rset=" << rset << " brst=" << brst;
774 }
775 Reset();
776 if (rset) pr0out |= kPR0_M_RSET|kPR0_M_DNI;
777 if (brst) pr0out |= kPR0_M_BRST;
778 cpu.AddWibr(clist, fBase+kPR1, GetPr1());
779 cpu.AddWibr(clist, fBase+kPR0, pr0out);
780 Server().Exec(clist);
781 return 0;
782 }
783
784 if (fTraceLevel>0) {
785 RlogMsg lmsg(LogFile());
786 lmsg << "-I " << Name() << ": cmd"
787 << " pr0=" << RosPrintBvi(fPr0Last,8)
788 << " r=" << rset << "," << brst
789 << " cmd=" << MnemoPcmd(pcmd);
790
791 if (pcmd == kPCMD_GETCMD && fPC_rdpcb > 0) { // if GETCMD and pdb loaded
792 uint16_t func = fPcb[0] & kPC0_M_FUNC;
793 lmsg << " fu=" << MnemoFunc(func);
794
795 if (func == kFUNC_RMAL || func == kFUNC_WMAL || // if func with udbb
796 func == kFUNC_RRF || func == kFUNC_WRF ||
797 func == kFUNC_RCTR || func == kFUNC_RCCTR ||
798 func == kFUNC_RSID || func == kFUNC_WSID) {
799 uint32_t udbb = 0777777;
800 Wlist2UBAddr(&fPcb[1], udbb);
801 lmsg << " udbb=" << RosPrintf(udbb&kUBA_M,"o0", 6);
802 }
803 }
804 if (pcmd == kPCMD_PDMD && fPC_rdtxdsccur > 0) { // PDMD and txdsc ect loaded
805 lmsg << " t" << RosPrintf(fTxRingIndex,"d0", 2)
806 << "," << RingDsc2OSEString(fTxDscCurPC,'-')
807 << "," << RingDsc2OSEString(fTxDscNxtPC,'-')
808 << " r" << RosPrintf(fRxRingIndex,"d0", 2)
809 << "," << RingDsc2OSEString(fRxDscCurPC,'-')
810 << "," << RingDsc2OSEString(fRxDscNxtPC,'-');
811 }
812 }
813
814 switch (pcmd) {
815 case kPCMD_NOOP: // NOOP --------------------------
817 return 0; // fully handled in FPGA
818
819 case kPCMD_GETPCBB: // GETPCBB -----------------------
820 {
822 size_t ipr2 = cpu.AddRibr(clist, fBase+kPR2);
823 size_t ipr3 = cpu.AddRibr(clist, fBase+kPR3);
824 cpu.AddWibr(clist, fBase+kPR1, GetPr1());
825 cpu.AddWibr(clist, fBase+kPR0, kPR0_M_DNI);
826 Server().Exec(clist);
827 fPcbb = ( uint32_t(clist[ipr2].Data()) |
828 (uint32_t(clist[ipr3].Data())<<16)) & kUBA_M; // 17:01 valid!
829 fPcbbValid = true;
831 if (fTraceLevel>0) {
832 RlogMsg lmsg(LogFile());
833 lmsg << "-I " << Name() << ": GETPCBB: " << RosPrintBvi(fPcbb,8,18);
834 }
835 }
836 return 0;
837
838 case kPCMD_GETCMD: // GETCMD ------------------------
839 {
841 bool ok = ExecGetcmd(clist);
842 pr0out |= ok ? kPR0_M_DNI : kPR0_M_PCEI;
843 }
844 break;
845
846 case kPCMD_SELFTST: // SELFTST -----------------------
847 {
849 Reset(); // handle like reset
850 pr0out |= kPR0_M_DNI;
851 }
852 return 0;
853
854 case kPCMD_START: // START -------------------------
855 {
857 if (fPr1State == kSTATE_RUN) { // start while running is a noop
858 pr0out |= kPR0_M_DNI;
859 break;
860 }
861 if (fPr1State == kSTATE_READY && fRingValid) { // in _READY and ring ok
862 SetRunning(true);
863 pr0out |= kPR0_M_DNI;
864 } else {
865 pr0out |= kPR0_M_PCEI;
866 }
867 }
868 break;
869
870 case kPCMD_BOOT: // BOOT --------------------------
871 {
872 fStats.Inc(kStatNPcmdUimpl); // not implemented ...
873 pr0out |= kPR0_M_PCEI;
874 }
875 break;
876
877 case kPCMD_PDMD: // PDMD --------------------------
878 {
880 if (Running()) {
883 }
884 pr0out |= kPR0_M_DNI;
885 }
886 break;
887
888 case kPCMD_HALT: // HALT --------------------------
889 {
890 if (fPr1Delua) {
891 fStats.Inc(kStatNPcmdHalt); // defined for DELUA
892 SetRunning(false);
893 fPr1State = kSTATE_PHALT; // ends in dead end state
894 } else {
896 }
897 pr0out |= kPR0_M_DNI; // always DNI it (is noop on DEUNA)
898 }
899 break;
900
901 case kPCMD_STOP: // STOP --------------------------
902 {
904 if (fPr1State == kSTATE_RUN) { // stop if in _RUN, noop otherwise
905 SetRunning(false);
906 }
907 pr0out |= kPR0_M_PCEI;
908 }
909 break;
910
911 default: // all others are reserved codes
912 {
914 pr0out |= kPR0_M_DNI;
915 }
916 break;
917 }
918
919 cpu.AddWibr(clist, fBase+kPR1, GetPr1());
920 cpu.AddWibr(clist, fBase+kPR0, pr0out);
921 Server().Exec(clist);
922 return 0;
923}
924
925//--------------------------------------+-----------------------------------
927
929{
930 for (auto& mac : fMacList) mac = 0;
932 fMacList[1] = 0xffffffffffff;
933 fMcastCnt = 0;
934 return;
935}
936
937//--------------------------------------+-----------------------------------
939
941{
942 fCtrTimeCleared.GetClock(CLOCK_MONOTONIC);
943 fCtrRxFra = 0;
944 fCtrRxFraMcast = 0;
945 fCtrRxByt = 0;
946 fCtrRxBytMcast = 0;
947 fCtrRxFraLoInt = 0;
948 fCtrRxFraLoBuf = 0;
949 fCtrTxFra = 0;
950 fCtrTxFraMcast = 0;
951 fCtrTxByt = 0;
952 fCtrTxBytMcast = 0;
953 fCtrTxFraAbort = 0;
954 fCtrFraLoop = 0;
955 return;
956}
957
958//--------------------------------------+-----------------------------------
960
962{
963 fStatus = 0; // lsb is 0 anyway. so clear all
964 return;
965}
966
967//--------------------------------------+-----------------------------------
970{
971 fRunning = false; // end running
972 StopTxRing(); // run-down tx ring
973 StopRxRing(); // run-down rx ring
974 fPcbbValid = false; // clear state
975 fPcbb = 0;
976 fRingValid = false;
977 fTxRingBase = 0;
978 fTxRingSize = 0;
979 fTxRingELen = 0;
980 fRxRingBase = 0;
981 fRxRingSize = 0;
982 fRxRingELen = 0;
983 fTxRingIndex = 0;
984 fRxRingIndex = 0;
986 fMcastCnt = 0;
987 fPr1Pcto = false;
990 ClearStatus();
991 ClearCtr();
992 return;
993}
994
995//--------------------------------------+-----------------------------------
998{
999 if (fRunning == run) return;
1000 if (run) { // start
1001 if (! fRxPollTimer.IsOpen()) { // start poll timer if needed
1003 Server().AddPollHandler([this](const pollfd& pfd)
1004 { return RxPollHandler(pfd); },
1005 fRxPollTimer.Fd(), POLLIN);
1006 }
1007
1008 fRunning = true;
1010 fTxRingIndex = 0;
1011 fTxBufOffset = 0;
1012 fRxRingIndex = 0;
1013 fRxBufOffset = 0;
1014
1015 StartTxRing();
1016 StartRxRing();
1017
1018 } else { // stop
1019 fRunning = false;
1020 StopTxRing();
1021 StopRxRing();
1023 }
1024
1026 return;
1027}
1028
1029//--------------------------------------+-----------------------------------
1032{
1033 Rw11Cpu& cpu = Cpu();
1034
1035 // FIXME_code: where is pcb read status checked ??
1036 if (fPC_rdpcb == 0) { // if pcb not available
1037 fPr1Pcto = true;
1038 return false;
1039 }
1040
1041 uint16_t func = fPcb[0] & kPC0_M_FUNC;
1042 if (fPcb[0] & kPC0_M_MBZ) return false;
1043
1044 uint32_t udbb;
1045 uint16_t pr2len;
1046 Wlist2UBAddrLen(&fPcb[1], udbb, pr2len);
1047 bool udbb_ok = (udbb & ~kUBA_M) == 0;
1048
1049 switch (func) {
1050 case kFUNC_NOOP: // NOOP --------------------------
1052 return true;
1053
1054 case kFUNC_RDPA: // RDPA -- read default mac -----
1055 {
1058 cpu.AddWMem(clist, fPcbb+2, &fPcb[1], 3, Rw11Cpu::kCPAH_M_UBM22, true);
1059 LogMacFunc("RDPA", fMacDefault);
1060 return true;
1061 }
1062
1063 case kFUNC_RPA: // RPA -- read mac ---------------
1064 {
1067 cpu.AddWMem(clist, fPcbb+2, &fPcb[1], 3, Rw11Cpu::kCPAH_M_UBM22, true);
1068 LogMacFunc("RPA", fMacList[0]);
1069 return true;
1070 }
1071
1072 case kFUNC_WPA: // WPA -- write mac---------------
1073 {
1075 uint64_t mac= RethTools::WList2Mac(&fPcb[1]);
1076 if (mac & 0x1) return false; // lsb of MAC must be 0
1077 fMacList[0] = mac;
1078 LogMacFunc("RPA", fMacList[0]);
1079 return true;
1080 }
1081
1082 case kFUNC_RMAL: // RMAL -- read mcast list -------
1083 {
1085 if (!udbb_ok) return false;
1086 uint16_t mltlen = pr2len;
1087 if (mltlen > kDimMcast) return false;
1088 if (mltlen == 0) return true;
1089 uint16_t udb[3*kDimMcast];
1090 for (int i=0; i<mltlen; i++) {
1091 RethTools::Mac2WList(fMacList[2+i], &udb[3*i]);
1092 }
1093 LogMcastFunc("RMAL");
1094
1095 RlinkCommandList clist1;
1096 cpu.AddWMem(clist1, udbb, udb, 3*mltlen, Rw11Cpu::kCPAH_M_UBM22, true);
1097 Server().Exec(clist1);
1098 // FIXME_code: handle access errors
1099 return true;
1100 }
1101
1102 case kFUNC_WMAL: // WMAL -- write mcast list ------
1103 {
1105 if (!udbb_ok) return false;
1106 uint16_t mltlen = pr2len;
1107 if (mltlen > kDimMcast) return false;
1108 fMcastCnt = 0;
1109 for (int i=0; i<kDimMcast; i++) fMacList[2+i] = 0;
1110 if (mltlen == 0) return true;
1111
1112 uint16_t udb[3*kDimMcast];
1113 RlinkCommandList clist1;
1114 cpu.AddRMem(clist1, udbb, udb, 3*mltlen, Rw11Cpu::kCPAH_M_UBM22, true);
1115 Server().Exec(clist1);
1116 // FIXME_code: handle access errors
1117 for (int i=0; i<mltlen; i++) {
1118 uint64_t mac = RethTools::WList2Mac(&udb[3*i]);
1119 if (!(mac & 0x1)) return false; // FIXME_code: check needed? DELUA ?
1120 fMacList[2+i] = mac;
1121 }
1122 fMcastCnt = mltlen;
1123 LogMcastFunc("WMAL");
1124
1125 return true;
1126 }
1127
1128 case kFUNC_RRF: // RRF -- read ring format -------
1129 {
1131 // FIXME_code: get correct MBZ test !!
1132 if (!udbb_ok) return false; // pdb[2] length ignored
1133 uint16_t udb[6];
1135 udb[2] = fTxRingSize;
1137 udb[5] = fRxRingSize;
1138 LogRingFunc("RRF");
1139
1140 RlinkCommandList clist1;
1141 cpu.AddWMem(clist1, udbb, udb, 6, Rw11Cpu::kCPAH_M_UBM22, true);
1142 Server().Exec(clist1);
1143 // FIXME_code: handle access errors
1144 return true;
1145 }
1146
1147 case kFUNC_WRF: // WRF -- write ring format ------
1148 {
1150 if (!udbb_ok) return false; // pdb[2] length ignored
1151 uint16_t udb[6];
1152 RlinkCommandList clist1;
1153 cpu.AddRMem(clist1, udbb, udb, 6, Rw11Cpu::kCPAH_M_UBM22, true);
1154 Server().Exec(clist1);
1155 // FIXME_code: handle access errors
1156 uint32_t txbase, rxbase;
1157 uint16_t txelen, rxelen;
1158 uint16_t txsize, rxsize;
1159 Wlist2UBAddrLen(&udb[0], txbase, txelen);
1160 if (txbase & ~kUBA_M) return false;
1161 txsize = udb[2];
1162 if (txsize <= 1) return false;
1163 Wlist2UBAddrLen(&udb[3], rxbase, rxelen);
1164 if (rxbase & ~kUBA_M) return false;
1165 rxsize = udb[5];
1166 if (rxsize <= 1) return false;
1167 fRingValid = true;
1168 fTxRingBase = txbase;
1169 fTxRingELen = txelen;
1170 fTxRingSize = txsize;
1171 fRxRingBase = rxbase;
1172 fRxRingELen = rxelen;
1173 fRxRingSize = rxsize;
1174 LogRingFunc("WRF");
1175 return true;
1176 }
1177
1178 case kFUNC_RCTR: // RCTR -- read counters ---------
1179 case kFUNC_RCCTR: // RCCTR -- read&clear counters --
1180 {
1182 if ((!udbb_ok) || pr2len != 0) return false; // pdb[2] length mbz
1183 uint16_t ctrlen = fPcb[3];
1184 if (ctrlen &0x1) return false; // must be even
1185 if (ctrlen == 0) return true; // nothing to do...
1186 uint16_t ctrmax = fPr1Delua ? kDimCtrDelua : kDimCtrDeuna;
1187 if (ctrlen > ctrmax) ctrlen = ctrmax;
1188
1189 uint16_t udb[kDimCtr];
1190 for (auto& w : udb) w = 0;
1191
1192 Rtime dt = Rtime(CLOCK_MONOTONIC) - fCtrTimeCleared;
1193 udb[ 0] = ctrlen;
1194 udb[ 1] = (dt.Sec() < 0xffff) ? uint16_t(dt.Sec()) : 0xffff;
1195 udb[ 2] = fCtrRxFra & 0xffff;
1196 udb[ 3] = fCtrRxFra >> 16;
1197 udb[ 4] = fCtrRxFraMcast & 0xffff;
1198 udb[ 5] = fCtrRxFraMcast >> 16;
1199 udb[ 8] = fCtrRxByt & 0xffff;
1200 udb[ 9] = fCtrRxByt >> 16;
1201 udb[10] = fCtrRxBytMcast & 0xffff;
1202 udb[11] = fCtrRxBytMcast >> 16;
1203 udb[12] = fCtrRxFraLoInt;
1204 udb[13] = fCtrRxFraLoBuf;
1205 udb[14] = fCtrTxFra & 0xffff;
1206 udb[15] = fCtrTxFra >> 16;
1207 udb[16] = fCtrTxFraMcast & 0xffff;
1208 udb[17] = fCtrTxFraMcast >> 16;
1209 udb[24] = fCtrTxByt & 0xffff;
1210 udb[25] = fCtrTxByt >> 16;
1211 udb[26] = fCtrTxBytMcast & 0xffff;
1212 udb[27] = fCtrTxBytMcast >> 16;
1213 udb[29] = fCtrTxFraAbort;
1214 RlinkCommandList clist1;
1215 cpu.AddWMem(clist1, udbb, udb, ctrlen, Rw11Cpu::kCPAH_M_UBM22, true);
1216 Server().Exec(clist1);
1217 // FIXME_code: handle access errors
1218 if (func==kFUNC_RCCTR) ClearCtr();
1219 return true;
1220 }
1221
1222 case kFUNC_RMODE: // RMODE -- read mode ------------
1223 {
1225 fPcb[1] = fMode;
1226 cpu.AddWMem(clist, fPcbb+2, &fPcb[1], 1, Rw11Cpu::kCPAH_M_UBM22, true);
1227 LogFunc("RMODE", "mode", fMode);
1228 return true;
1229 }
1230
1231 case kFUNC_WMODE: // WMODE -- write mode -----------
1232 {
1235 if (fPcb[1] & mbz) return false;
1236 fMode = fPcb[1];
1237 LogFunc("WMODE", "mode", fMode);
1238 return true;
1239 }
1240
1241 case kFUNC_RSTAT: // RSTAT -- read status ----------
1242 case kFUNC_RCSTAT: // RCSTAT -- read&clear status ---
1243 {
1245 fPcb[1] = fStatus;
1248 cpu.AddWMem(clist, fPcbb+2, &fPcb[1], 3, Rw11Cpu::kCPAH_M_UBM22, true);
1249 LogFunc((func==kFUNC_RCSTAT) ? "RCSTAT" : "RSTAT",
1250 "stat", fStatus, "mltlen", fMcastCnt);
1251 if (func==kFUNC_RCSTAT) ClearStatus();
1252 return true;
1253 }
1254
1255 case kFUNC_RSID: // RSID -- read system ID --------
1256 {
1258 if ((!udbb_ok) || pr2len != 0) return false; // pdb[2] length mbz
1259 uint16_t pltlen = fPcb[3];
1260 if (pltlen &0x1) return false; // must be even
1261 if (pltlen == 0) return true; // nothing to do...
1262 if (pltlen > kDimPlt) return false; // PLTLEN to high is error
1263
1264 uint16_t udb[kDimPlt];
1265 for (auto& w : udb) w = 0;
1266
1267 // this follow DEUNA UG and DELUA UG (defaults are same for both)
1268 // and the simh pdp11_xu.c implementation
1269 udb[11] = 0x260; // type
1270 udb[12] = 28; // ccount (+parameters... NI)
1271 udb[13] = 7; // code
1272 udb[14] = 0; // recnum
1273 // mop information
1274 udb[15] = 1; // mvtype
1275 udb[16] = 0x0303; // mvver + mvlen
1276 udb[17] = 0; // mvueco + mveco
1277 // function information
1278 udb[18] = 2; // ftype
1279 udb[19] = 0x0502; // fval1 + flen
1280 udb[20] = 0x0700; // hatype<07:00> + fval2
1281 udb[21] = 0x0600; // halen + hatype<15:08>
1282 // built-in MAC address
1283 RethTools::Mac2WList(fMacList[0], &udb[21]); // HA
1284 udb[24] = 0x64; // dtype
1285 udb[25] = (11 << 8) + 1; // dvalue + dlen
1286 RlinkCommandList clist1;
1287 cpu.AddWMem(clist1, udbb, udb, pltlen, Rw11Cpu::kCPAH_M_UBM22, true);
1288 Server().Exec(clist1);
1289 // FIXME_code: handle access errors
1290 return true;
1291 }
1292
1293 case kFUNC_WSID: // WSID -- write system ID -------
1294 {
1296 return false; // currently not implemented
1297 }
1298
1299 default:
1301 return false;
1302 }
1303 return false;
1304}
1305
1306//--------------------------------------+-----------------------------------
1309{
1310 Rw11Cpu& cpu = Cpu();
1311
1312 fPrimClist.Clear();
1315 fPC_rdpcb = 0;
1316 fPC_lapcb = 0;
1317 fPC_rdtxdsccur = 0;
1318 fPC_latxdsccur = 0;
1319 fPC_rdtxdscnxt = 0;
1320 fPC_latxdscnxt = 0;
1321 fPC_rdrxdsccur = 0;
1322 fPC_larxdsccur = 0;
1323 fPC_rdrxdscnxt = 0;
1324 if (!fPcbbValid) return;
1328 if (!Running()) return;
1329
1330 // Note: the memory addresses will be set before each usage with ModLalh()
1331 // that's why the initial memory address is set as kUBA_M (end of ubmap)
1335
1339
1343
1346 return;
1347}
1348
1349//--------------------------------------+-----------------------------------
1351
1353{
1354 uint16_t pr1 = fPr1State;
1355 if (fPr1Pcto) pr1 |= kPR1_M_PCTO;
1356 if (fPr1Delua) {
1357 pr1 |= kPR1_M_DELUA;
1358 } else {
1359 if (!fspUnit[0]->HasVirt()) {
1360 pr1 |= kPR1_M_XPWR | kPR1_M_ICAB;
1361 }
1362 }
1363 return pr1;
1364}
1365
1366//--------------------------------------+-----------------------------------
1369{
1370 RlinkCommandList clist;
1371 uint16_t txdsccur[4];
1372 uint16_t txdscnxt[4];
1374 txdsccur, 3, Rw11Cpu::kCPAH_M_UBM22, true);
1376 txdscnxt, 3, Rw11Cpu::kCPAH_M_UBM22, true);
1377 Server().Exec(clist);
1378 // FIXME_code: check dsc read errors !
1379 StartTxRing(txdsccur, txdscnxt);
1380 return;
1381}
1382
1383//--------------------------------------+-----------------------------------
1385void Rw11CntlDEUNA::StartTxRing(const uint16_t dsccur[4],
1386 const uint16_t dscnxt[4])
1387{
1388 if (fTxRingState != kStateTxIdle) return;
1389
1390 SetRingDsc(fTxDscCur, dsccur);
1391 SetRingDsc(fTxDscNxt, dscnxt);
1392
1393 if (fTxDscCurPC[2] & kTXR2_M_OWN) { // pending tx frames ?
1395 Server().QueueAction([this](){ return TxRingHandler(); });
1396 }
1397 return;
1398}
1399
1400//--------------------------------------+-----------------------------------
1403{
1405 return;
1406}
1407
1408//--------------------------------------+-----------------------------------
1411{
1412 RlinkCommandList clist;
1413 uint16_t rxdsccur[4];
1414 uint16_t rxdscnxt[4];
1416 rxdsccur, 3, Rw11Cpu::kCPAH_M_UBM22, true);
1418 rxdscnxt, 3, Rw11Cpu::kCPAH_M_UBM22, true);
1419 Server().Exec(clist);
1420 // FIXME_code: check dsc read errors !
1421 StartRxRing(rxdsccur, rxdscnxt);
1422 return;
1423}
1424
1425//--------------------------------------+-----------------------------------
1427void Rw11CntlDEUNA::StartRxRing(const uint16_t dsccur[4],
1428 const uint16_t dscnxt[4])
1429{
1430 if (fRxRingState != kStateRxIdle) return;
1431
1432 SetRingDsc(fRxDscCur, dsccur);
1433 SetRingDsc(fRxDscNxt, dscnxt);
1434
1435 if (!fRxBufQueue.empty() && // if pending rx frames
1436 fRxDscCur[2] & kRXR2_M_OWN) { // and buffer available
1438 Server().QueueAction([this](){ return RxRingHandler(); });
1439 }
1440 return;
1441}
1442
1443//--------------------------------------+-----------------------------------
1446{
1449 return;
1450}
1451//--------------------------------------+-----------------------------------
1454{
1455 fTxRingState = kStateTxIdle; // expect quit
1456 if (!Running()) return 0; // quit if not running
1457
1458 RlinkCommandList clist;
1459 Rw11Cpu& cpu = Cpu();
1460 Rw11UnitDEUNA& unit = *fspUnit[0];
1461
1462 if (!(fTxDscCur[2] & kTXR2_M_OWN)) return 0; // FIXME_code: shouldn't happen !
1463 // FIXME_code: quit if ring bad, not attached,...
1464
1465 LogRingInfo('t','<'); // log initial ring dsc state
1466
1467 if (fTxBufOffset == 0) { // new frame processed
1468 fTxBuf.Clear(); // clear buffer
1469 fTxBuf.SetTime(); // set timestamp
1470 }
1471
1472 // clear OWN+flags, keep SEGB,STF,ENF
1474 fTxDscCur[3] = 0;
1475
1476 uint16_t stat = 0;
1477 uint16_t pr0out = 0;
1478
1479 uint16_t slen = fTxDscCur[0];
1480 uint32_t segb = uint32_t(fTxDscCur[1]) | uint32_t(fTxDscCur[2] & 0xff)<<16;
1481 if (segb & ~kUBA_M) stat |= kSTAT_M_TRNG; // FIXME_code: see MBZ comment above
1482
1483 uint16_t tsize = slen;
1484 if (tsize > RethBuf::kMaxSize) {
1485 tsize = RethBuf::kMaxSize;
1486 fTxDscCur[3] |= kTXR3_M_BUFL; // FIXME_code: is that correct ?
1487 }
1488
1489 // read data
1490 // FIXME_code: handle odd base !!
1491 cpu.AddRMem(clist, segb, fTxBuf.Buf16(), (tsize+1)/2,
1493 Server().Exec(clist);
1494 // FIXME_code: handle errors !!
1495
1496 fTxBuf.SetSize(tsize); // FIXME_code: handle chunks !
1497
1498 clist.Clear();
1499
1500 // update current dsc
1501 cpu.AddWMem(clist, TxRingDscAddr(fTxRingIndex)+4, &fTxDscCur[2], 2,
1503 clist.AddLabo();
1504
1505 // re-read next dsc; and read next-next dsc
1506 uint16_t dsccurnew[4];
1507 uint16_t dscnxtnew[4];
1508 cpu.AddRMem(clist, TxRingDscAddr(TxRingIndexNext(1)), dsccurnew, 3,
1510 clist.AddLabo();
1511 cpu.AddRMem(clist, TxRingDscAddr(TxRingIndexNext(2)), dscnxtnew, 3,
1513 clist.AddLabo();
1514
1515 // signal frame done
1516 pr0out |= kPR0_M_TXI;
1517 cpu.AddWibr(clist, fBase+kPR0, pr0out);
1518
1519 // final frame handling
1520 fTxBuf.SetMacSource(fMacList[0]); // set source address
1521 if (fTxBuf.Size() < RethBuf::kMinSize) { // pad if to small
1522 ::memset(fTxBuf.Buf8()+fTxBuf.Size(), 0, RethBuf::kMinSize-fTxBuf.Size());
1525 if (!(fMode&kMODE_M_TPAD)) { // runt error unless TPAD active
1526 fTxDscCur[3] |= kTXR3_M_BUFL;
1527 }
1528 }
1529
1530 // check for 'station match'
1531 uint64_t macdst = fTxBuf.MacDestination();
1532 int matchdst = MacFilter(macdst);
1533 if (matchdst > 0) {
1534 fTxDscCur[2] |= kTXR2_M_MTCH;
1535 }
1536
1539 if (fTxBuf.IsMcast()) { // Mcast includes Bcast !
1542 if (fTxBuf.IsBcast()) {
1544 }
1545 }
1546
1547 if (fTraceLevel>2) {
1548 RlogMsg lmsg(LogFile());
1549 std::ostringstream sos;
1550 fTxBuf.Dump(sos, 4, "fTxBuf: ");
1551 lmsg << sos.str();
1552 }
1553
1554 LogFrameInfo('t', fTxBuf); // log transmitted frame
1555 if (unit.HasVirt()) { // attached ?
1556 RerrMsg emsg;
1557 unit.Virt().Snd(fTxBuf, emsg);
1558 // FIXME_code: error handling
1559 }
1560
1561 LogRingInfo('t','>'); // log final ring dsc state
1562 Server().Exec(clist);
1563 // FIXME_code: handle errors
1564
1565 // push ring index, update current and next dsc
1567 SetRingDsc(fTxDscCur, dsccurnew);
1568 SetRingDsc(fTxDscNxt, dscnxtnew);
1569
1570 // now decide whether to idle or continue
1571 if (!(fTxDscCur[2] & kTXR2_M_OWN)) return 0; // quit if nothing to do
1572
1573 fTxRingState = kStateTxBusy; // otherwise continue
1574 return 1;
1575}
1576
1577//--------------------------------------+-----------------------------------
1580{
1582 if (!Running()) return 0; // quit if not running
1583
1584 RlinkCommandList clist;
1585 Rw11Cpu& cpu = Cpu();
1586
1587 if (!(fRxDscCur[2] & kRXR2_M_OWN)) return 0; // FIXME_code: shouldn't happen !
1588
1589 if (fRxBufOffset == 0) { // new frame needed
1590 if (fRxBufQueue.empty()) return 0; // quit if none available
1591 fRxBufCurr = fRxBufQueue.front();
1592 fRxBufQueue.pop_front();
1593 }
1594 RethBuf& ebuf = *fRxBufCurr;
1595
1596 if (true && ebuf.Size() < RethBuf::kMinSize) { // pad if ena
1597 ::memset(ebuf.Buf8()+ebuf.Size(), 0, RethBuf::kMinSize-ebuf.Size());
1600 }
1601
1602 LogRingInfo('r','<'); // log initial ring dsc state
1603 LogFrameInfo('e', ebuf); // log reveived frame
1604
1605 // FIXME_code: this also clears the MBZ areas !! handle this correctly
1606 // clear OWN+flags, keep SEGB
1607 fRxDscCur[2] &= kRXR2_M_SEGB;
1608 fRxDscCur[3] = 0;
1609
1610 uint16_t stat = 0;
1611 uint16_t pr0out = 0;
1612
1613 uint16_t slen = fRxDscCur[0];
1614 uint32_t segb = uint32_t(fRxDscCur[1]) | uint32_t(fRxDscCur[2] & 0xff)<<16;
1615 if (segb & ~kUBA_M) stat |= kSTAT_M_RRNG; // FIXME_code: see MBZ comment above
1616
1617 uint16_t tsize = ebuf.Size();
1618
1619 if (ebuf.Size() > slen) {
1620 tsize = slen;
1621 fRxDscCur[3] |= kRXR3_M_BUFL;
1622 }
1623
1624 // Note: the DEUNA returns in the rx descriptor the frame length including
1625 // the CRC length (4 bytes) !! But apparently does not transfer the
1626 // CRC, at least in normal mode !! See comments in simh pdp11_xu.c.
1628 fRxDscCur[3] |= tsize+RethBuf::kCrcSize;
1629
1630 // write data
1631 cpu.AddWMem(clist, segb, ebuf.Buf16(), (tsize+1)/2,
1633 clist.AddLabo();
1634 // update current dsc
1635 cpu.AddWMem(clist, RxRingDscAddr(fRxRingIndex)+4, &fRxDscCur[2], 2,
1637 clist.AddLabo();
1638
1639 // re-read next dsc; and read next-next dsc
1640 uint16_t dsccurnew[4];
1641 uint16_t dscnxtnew[4];
1642 cpu.AddRMem(clist, RxRingDscAddr(RxRingIndexNext(1)), dsccurnew, 3,
1644 clist.AddLabo();
1645 cpu.AddRMem(clist, RxRingDscAddr(RxRingIndexNext(2)), dscnxtnew, 3,
1647 clist.AddLabo();
1648
1649 // signal frame done
1650 pr0out |= kPR0_M_RXI;
1651 cpu.AddWibr(clist, fBase+kPR0, pr0out);
1652
1655 if (ebuf.IsMcast()) { // Mcast includes Bcast !
1658 if (ebuf.IsBcast()) {
1660 }
1661 }
1662
1663 LogRingInfo('r','>'); // log final ring dsc state
1664 Server().Exec(clist);
1665 // FIXME_code: handle errors
1666
1667 // push ring index, update current and next dsc
1669 SetRingDsc(fRxDscCur, dsccurnew);
1670 SetRingDsc(fRxDscNxt, dscnxtnew);
1671
1672 // now decide whether to idle, continue, or poll
1673 if (fRxBufQueue.empty()) return 0; // quit if nothing to do
1674 if (!(fRxDscCur[2] & kRXR2_M_OWN)) { // no free buffer
1676 fRxRingState = kStateRxPoll; // activate timer
1677 return 0;
1678 }
1679
1680 fRxRingState = kStateRxBusy; // otherwise continue
1681 return 1;
1682}
1683
1684//--------------------------------------+-----------------------------------
1686int Rw11CntlDEUNA::RxPollHandler(const pollfd& pfd)
1687{
1688 // bail-out and cancel handler if poll returns an error event
1689 if (pfd.revents & (~pfd.events)) return -1;
1690
1691 uint64_t cnt = fRxPollTimer.Read(); // harvest expiration count
1692 if (!Running() || // if not running
1693 fRxRingState != kStateRxPoll || // if not polling
1694 !cnt) return 0; // if not expired -> quit
1695
1696 fRxRingState = kStateRxIdle; // end poll
1697 StartRxRing(); // re-start rx ring
1698
1699 return 0;
1700}
1701
1702//--------------------------------------+-----------------------------------
1705{
1706 int maxind = 2 + fMcastCnt;
1707 for (int i=0; i<maxind; i++) {
1708 if (fMacList[i] == mac) return i;
1709 }
1710 return -1;
1711}
1712//--------------------------------------+-----------------------------------
1714
1715void Rw11CntlDEUNA::UpdateStat16(uint32_t& stat, size_t ind, uint32_t inc)
1716{
1717 fStats.Inc(ind, inc);
1718 stat += inc;
1719 if (stat < inc || stat > 0xffff) stat = 0xffff;
1720}
1721
1722//--------------------------------------+-----------------------------------
1724
1725void Rw11CntlDEUNA::UpdateStat32(uint32_t& stat, size_t ind, uint32_t inc)
1726{
1727 fStats.Inc(ind, inc);
1728 stat += inc;
1729 if (stat < inc) stat = 0xffffffff;
1730}
1731
1732//--------------------------------------+-----------------------------------
1734void Rw11CntlDEUNA::LogMacFunc(const char* cmd, uint64_t mac)
1735{
1736 if (fTraceLevel == 0) return;
1737 RlogMsg lmsg(LogFile());
1738 lmsg << "-I " << Name() << ": " << cmd << ": " << RethTools::Mac2String(mac);
1739 return;
1740}
1741
1742//--------------------------------------+-----------------------------------
1744void Rw11CntlDEUNA::LogMcastFunc(const char* cmd)
1745{
1746 if (fTraceLevel == 0) return;
1747 RlogMsg lmsg(LogFile());
1748 lmsg << "-I " << Name() << ": " << cmd << ": mltlen=" << fMcastCnt;
1749 for (int i=0; i<fMcastCnt; i++) {
1750 lmsg << "\n " << RethTools::Mac2String(fMacList[2+i]);
1751 }
1752 return;
1753}
1754
1755//--------------------------------------+-----------------------------------
1757void Rw11CntlDEUNA::LogRingFunc(const char* cmd)
1758{
1759 if (fTraceLevel == 0) return;
1760 RlogMsg lmsg(LogFile());
1761 lmsg << "-I " << Name() << ": " << cmd << ":"
1762 << " tx base=" << RosPrintBvi(fTxRingBase,8,18)
1763 << " size=" << RosPrintf(fTxRingSize, "d", 2)
1764 << " elen=" << RosPrintf(fTxRingELen, "d", 2)
1765 << "; rx base=" << RosPrintBvi(fRxRingBase,8,18)
1766 << " size=" << RosPrintf(fRxRingSize, "d", 2)
1767 << " elen=" << RosPrintf(fRxRingELen, "d", 2);
1768 return;
1769}
1770
1771//--------------------------------------+-----------------------------------
1773void Rw11CntlDEUNA::LogFunc(const char* cmd, const char* tag1, uint16_t val1,
1774 const char* tag2, uint16_t val2)
1775{
1776 if (fTraceLevel == 0) return;
1777 RlogMsg lmsg(LogFile());
1778 lmsg << "-I " << Name() << ": " << cmd << ": "
1779 << tag1 << "=" << RosPrintBvi(val1,8);
1780 if (tag2) lmsg << tag2 << "=" << RosPrintBvi(val2,8);
1781 return;
1782}
1783
1784//--------------------------------------+-----------------------------------
1786void Rw11CntlDEUNA::LogRingInfo(char rxtx, char rw)
1787{
1788 if (fTraceLevel == 0) return;
1789
1790 bool tx = (rxtx == 't');
1791 uint16_t rind = tx ? fTxRingIndex : fRxRingIndex;
1792 uint16_t* rdsc = tx ? fTxDscCur : fRxDscCur;
1793
1794 RlogMsg lmsg(LogFile());
1795 lmsg << "-I " << Name() << ": " << rxtx << "xr "
1796 << rxtx << RosPrintf(rind,"d0", 2) << " " << rw
1797 << " " << RingDsc2String(rdsc, rxtx);
1798 return;
1799}
1800
1801//--------------------------------------+-----------------------------------
1803void Rw11CntlDEUNA::LogFrameInfo(char rxtx, const RethBuf& buf)
1804{
1805 if (fTraceLevel == 0) return;
1806
1807 bool tx = (rxtx == 't');
1808 RlogMsg lmsg(LogFile());
1809 lmsg << "-I " << Name() << ":" << (tx ? " snd " : " rcv ") << buf.FrameInfo();
1810 return;
1811}
1812
1813//--------------------------------------+-----------------------------------
1815
1816std::string Rw11CntlDEUNA::RingDsc2String(const uint16_t dsc[4], char rxtx)
1817{
1818 std::ostringstream sos;
1819 uint32_t segb = uint32_t(dsc[1]) + (uint32_t(dsc[2] & kTXR2_M_SEGB)<<16);
1820 uint16_t mlen = dsc[3] & kRXR3_M_MLEN;
1821 sos << RosPrintf(dsc[0],"d", 4)
1822 << "," << RosPrintBvi(segb, 8, 18)
1823 << "," << RosPrintf(mlen,"d", 4)
1824 << "; " << RosPrintBvi(uint16_t(dsc[2]>>8), 2, 8)
1825 << "," << RosPrintBvi(uint16_t(dsc[3]>>12), 2, 4) << ": ";
1826
1827 sos << RingDsc2OSEString(dsc);
1828
1829 if (dsc[2] & kTXR2_M_ERRS) sos << " errs";
1830 if (rxtx == 't') {
1831 if (dsc[2] & kTXR2_M_MTCH) sos << " mtch";
1832 if (dsc[2] & kTXR2_M_MORE) sos << " more";
1833 if (dsc[2] & kTXR2_M_ONE) sos << " one";
1834 if (dsc[2] & kTXR2_M_DEF) sos << " def";
1835 sos << ",";
1836 if (dsc[2] & kTXR3_M_BUFL) sos << " bufl";
1837 if (dsc[2] & kTXR3_M_UBTO) sos << " ubto";
1838 if (dsc[2] & kTXR3_M_LCOL) sos << " lcol";
1839 if (dsc[2] & kTXR3_M_LCAR) sos << " lcar";
1840 if (dsc[2] & kTXR3_M_RTRY) sos << " rtry";
1841 } else {
1842 if (dsc[2] & kRXR2_M_FRAM) sos << " fram";
1843 if (dsc[2] & kRXR2_M_OFLO) sos << " oflo";
1844 if (dsc[2] & kRXR2_M_CRC) sos << " crc";
1845 sos << ",";
1846 if (dsc[2] & kRXR3_M_BUFL) sos << " bufl";
1847 if (dsc[2] & kRXR3_M_UBTO) sos << " ubto";
1848 if (dsc[2] & kRXR3_M_NCHN) sos << " nchn";
1849 if (dsc[2] & kRXR3_M_OVRN) sos << " ovrn";
1850 }
1851
1852 return sos.str();
1853}
1854
1855//--------------------------------------+-----------------------------------
1857
1858std::string Rw11CntlDEUNA::RingDsc2OSEString(const uint16_t dsc[4], char fill)
1859{
1860 char res[4] = {fill,fill,fill,0};
1861 if (dsc[2] & kTXR2_M_OWN) res[0] = 'O';
1862 if (dsc[2] & kTXR2_M_STF) res[1] = 'S';
1863 if (dsc[2] & kTXR2_M_ENF) res[2] = 'E';
1864 return string(res);
1865}
1866
1867} // end namespace Retro
FIXME_docs.
Definition: RerrMsg.hpp:25
FIXME_docs.
Definition: RethBuf.hpp:27
void SetTime()
FIXME_docs.
Definition: RethBuf.ipp:42
bool IsMcast() const
FIXME_docs.
Definition: RethBuf.ipp:158
static const size_t kCrcSize
size of ethernet CRC
Definition: RethBuf.hpp:70
static const size_t kMinSize
min ethernet frame size
Definition: RethBuf.hpp:69
bool IsBcast() const
FIXME_docs.
Definition: RethBuf.ipp:166
void Dump(std::ostream &os, int ind=0, const char *text=0, int detail=0) const
FIXME_docs.
Definition: RethBuf.cpp:102
void SetMacSource(uint64_t mac)
FIXME_docs.
Definition: RethBuf.ipp:133
const uint8_t * Buf8() const
FIXME_docs.
Definition: RethBuf.ipp:76
uint64_t MacDestination() const
FIXME_docs.
Definition: RethBuf.ipp:142
static const size_t kMaxSize
max ethernet frame size
Definition: RethBuf.hpp:68
const uint16_t * Buf16() const
FIXME_docs.
Definition: RethBuf.ipp:84
std::shared_ptr< RethBuf > pbuf_t
Definition: RethBuf.hpp:29
std::string FrameInfo() const
FIXME_docs.
Definition: RethBuf.cpp:89
void SetSize(uint16_t size)
FIXME_docs.
Definition: RethBuf.ipp:33
uint16_t Size() const
FIXME_docs.
Definition: RethBuf.ipp:60
void Clear()
FIXME_docs.
Definition: RethBuf.ipp:24
FIXME_docs.
Definition: Rexception.hpp:29
bool IsOpen() const
FIXME_docs.
Definition: Rfd.ipp:28
int Fd() const
FIXME_docs.
Definition: Rfd.ipp:20
size_t AddAttn()
FIXME_docs.
size_t AddLabo()
FIXME_docs.
void AddAttnHandler(attnhdl_t &&attnhdl, uint16_t mask, void *cdata=nullptr)
FIXME_docs.
void QueueAction(actnhdl_t &&actnhdl)
FIXME_docs.
void GetAttnInfo(AttnArgs &args, RlinkCommandList &clist)
FIXME_docs.
bool Exec(RlinkCommandList &clist, RerrMsg &emsg)
FIXME_docs.
Definition: RlinkServer.ipp:60
void AddPollHandler(pollhdl_t &&pollhdl, int fd, short events=POLLIN)
FIXME_docs.
FIXME_docs.
Definition: RlogMsg.hpp:24
I/O appicator to generate fill characters.
Definition: RosFill.hpp:24
void Inc(size_t ind, double val=1.)
FIXME_docs.
Definition: Rstats.ipp:29
void Define(size_t ind, const std::string &name, const std::string &text)
FIXME_docs.
Definition: Rstats.cpp:72
FIXME_docs.
Definition: Rtime.hpp:25
time_t Sec() const
FIXME_docs.
Definition: Rtime.ipp:109
bool IsPositive() const
FIXME_docs.
Definition: Rtime.ipp:93
void GetClock(clockid_t clkid)
FIXME_docs.
Definition: Rtime.cpp:41
double Age(clockid_t clkid) const
FIXME_docs.
Definition: Rtime.cpp:72
uint64_t Read()
FIXME_docs.
Definition: RtimerFd.cpp:114
void Cancel()
FIXME_docs.
Definition: RtimerFd.cpp:87
void Open(clockid_t clkid=CLOCK_MONOTONIC)
FIXME_docs.
Definition: RtimerFd.cpp:51
void SetRelative(const Rtime &dt)
FIXME_docs.
Definition: RtimerFd.cpp:65
Implemenation (inline) of Rw11CntlBase.
virtual void Dump(std::ostream &os, int ind=0, const char *text=0, int detail=0) const
FIXME_docs.
std::shared_ptr< Rw11UnitDEUNA > fspUnit[NU]
static const uint16_t kMODE_M_MBZ_DEUNA
MBZ bit:10,8:4,1.
static const uint16_t kSTAT_M_RRNG
RRNG: rx ring error.
static const uint16_t kTXR2_M_SEGB
SEGB: msg of seg base.
virtual void UnitSetup(size_t ind)
FIXME_docs.
static const uint16_t kPR0_M_RSET
RSET: sw reset.
static const uint16_t kSTATE_PHALT
port halted
static const uint16_t kFUNC_WSID
WSID: write system id.
uint16_t fTxRingELen
tx ring entry length
static std::string RingDsc2OSEString(const uint16_t dsc[4], char fill=' ')
FIXME_docs.
static const uint16_t kSTAT_M_TMOT
TMOT: UNIBUS timeout.
static const uint16_t kSTAT_M_MERR
MERR: multiple errors.
bool fRunning
in kSTATE_RUN and active
static const uint16_t kPC0_M_FUNC
FUNC: function code.
static const uint16_t kFUNC_RMAL
RMAL: read mcast MAC list.
void Wlist2UBAddrLen(const uint16_t wlist[2], uint32_t &addr, uint16_t &len)
FIXME_docs.
static const uint16_t kPR0_M_RXI
RXI: receive rung intr.
uint32_t fCtrTxFraAbort
ctr: xmit aborted frames
enum s_rx fRxRingState
rx ring handler busy
void Config(const std::string &name, uint16_t base, int lam)
FIXME_docs.
static const uint16_t kTXR3_M_LCAR
LCAR: lost carrier.
static const uint16_t kRXR3_M_MLEN
MLEN: message length.
static std::string RingDsc2String(const uint16_t dsc[4], char rxtx)
FIXME_docs.
int AttnHandler(RlinkServer::AttnArgs &args)
FIXME_docs.
static const uint16_t kRXR2_M_ERRS
ERRS: error summary.
void Wlist2UBAddr(const uint16_t wlist[2], uint32_t &addr)
FIXME_docs.
static const uint16_t kSTATE_NHALT
ni halted
void ClearStatus()
FIXME_docs.
static const uint16_t kPCMD_GETCMD
GETCMD: get command.
void SetupPrimClist()
FIXME_docs.
uint16_t fRxDscNxt[4]
rx nxt ring dsc
static const uint16_t kMODE_M_INTL
INTL: int loopback(DELUA)
static const uint32_t kUBAODD_M
bits of odd unibus address
bool ExecGetcmd(RlinkCommandList &clist)
FIXME_docs.
static const uint16_t kPR0_V_PCMDBP
PCMDBP: pcmd busy prot.
void StartTxRing()
FIXME_docs.
Rtime fRxPollTime
rx poll time interval
static const uint16_t kSTATE_RESET
reset
uint16_t TxRingIndexNext(uint16_t inc=1) const
FIXME_docs.
static const uint16_t kPCMD_HALT
HALT: halt.
static const uint16_t kFUNC_RSTAT
RSTAT: read status.
static const uint16_t kTXR2_M_ONE
ONE: one collision.
uint16_t fRxRingELen
rx ring entry length
static const uint16_t kMODE_M_DMNT
DMNT: dis maint message.
void SetRxQueLimit(size_t rxqlim)
FIXME_docs.
int RxPollHandler(const pollfd &pfd)
FIXME_docs.
static const uint16_t kPR0_M_PDMDWB
PDMDWB: pdmd while busy.
static const uint16_t kMODE_M_DRDC
DRDC: dis data chaining.
static const uint16_t kPR0_M_TXI
TXI: transmit rung intr.
std::string MacDefault() const
FIXME_docs.
static const uint16_t kPR0_M_PCMD
PCMD: port command.
static const uint16_t kRXR2_M_OWN
OWN: owned by DENUA.
static const uint16_t kTXR2_M_OWN
OWN: owned by DEUNA.
void Reset()
FIXME_docs.
static const uint16_t kSTAT_M_TRNG
TRNG: tx ring error.
uint16_t fRxDscNxtPC[4]
rx nxt ring dsc from PrimClist
static const uint16_t kPR0
PR0 reg offset.
int fMcastCnt
mcast count
static const uint16_t kPCMD_STOP
STOP: stop.
static const uint16_t kPCMD_SELFTST
SELFTST: self test.
void LogRingFunc(const char *cmd)
FIXME_docs.
static const uint16_t kTXR3_M_UBTO
UBTO: UNIBUS timeout.
uint16_t fStatus
status
static const uint16_t kDimCtrDelua
DELUA count words (MAXCTR)
void UBAddrLen2Wlist(uint16_t wlist[2], uint32_t addr, uint16_t len)
FIXME_docs.
RtimerFd fRxPollTimer
rx poll timer
void LogFunc(const char *cmd, const char *tag1, uint16_t val1, const char *tag2=nullptr, uint16_t val2=0)
FIXME_docs.
static const uint16_t kTXR3_M_TDR
TDR: TDR value if RTRY=1.
size_t fPC_rdrxdsccur
PrimClist: rd rxdsc index.
static const uint16_t kRXR2_M_ENF
ENF: end of frame.
static const uint16_t kFUNC_WMODE
WMODE: write write.
static const uint16_t kDimCtr
max MAXCTR
size_t fRxQueLimit
rx queue limit
static const uint16_t kFUNC_RMODE
RMODE: read mode.
static const uint16_t kProbeOff
probe address offset (pr0)
uint32_t fCtrTxFraMcast
ctr: xmit mcast frames
static const uint16_t kRXR3_M_BUFL
BUFL: buf length error.
uint16_t fTxDscCur[4]
tx cur ring dsc
static const uint16_t kTXR2_M_ERRS
ERRS: error summary.
size_t fPC_rdpr0
PrimClist: rd pr0 index.
void SetType(const std::string &type)
FIXME_docs.
static const uint16_t kFUNC_RRF
RRF: read ring format.
RethBuf::pbuf_t fRxBufCurr
rx packet current
uint16_t fTxRingIndex
tx ring index
static const uint16_t kRXR2_M_FRAM
FRAM: frame error.
uint32_t fCtrFraLoop
ctr: loopback frames
size_t fPC_rdrxdscnxt
PrimClist: rd rxdsc index.
void ClearMacList()
FIXME_docs.
static const uint16_t kPCMD_GETPCBB
GETPCBB: get pcb base.
static const uint16_t kPCMD_NOOP
NOOP: noop.
std::deque< RethBuf::pbuf_t > fRxBufQueue
rx packet queue
uint32_t fCtrRxFra
ctr: rcvd frames
bool fPcbbValid
pcbb valid
uint16_t fPr0Last
last pr0 value
static const uint16_t kPR0_M_INTR
INTR: intr summary.
static const uint16_t kPR1_M_STATE
STATE: port status.
uint32_t TxRingDscAddr(uint16_t index) const
FIXME_docs.
static const uint16_t kTXR3_M_LCOL
LCOL: late collision.
static const uint16_t kMODE_M_TPAD
TPAD: tx msg padding ena.
void StartRxRing()
FIXME_docs.
static const uint16_t kDimMcast
max length Mcast list (MAXMLT)
bool Running() const
FIXME_docs.
uint16_t fPcb[4]
process control block
const char * MnemoFunc(uint16_t func) const
FIXME_docs.
static const uint16_t kPR3
PR3 reg offset.
size_t fRxBufOffset
rx packet offset
uint16_t fRxDscCur[4]
rx cur ring dsc
static const uint16_t kFUNC_RDPA
RDPA: read def MAC.
static const uint16_t kSTATE_SLOAD
secondary load
void UpdateStat16(uint32_t &stat, size_t ind, uint32_t inc=1)
FIXME_docs.
static const uint16_t kFUNC_RCTR
RCTR: read counters.
uint16_t fTxDscCurPC[4]
tx cur ring dsc from PrimClist
static const uint16_t kMODE_M_DTCR
DTCR: dis tx CRC.
static const uint16_t kTXR3_M_UFLO
UFLO: UNIBUS underflow.
static const uint16_t kMODE_M_ECT
ECT: ena collision test.
static const uint16_t kTXR3_M_BUFL
BUFL: buf length error.
static const uint16_t kIbaddr
DEUNA default address.
static const bool kProbeInt
probe int active
static const uint16_t kRXR2_M_CRC
CRC: CRC check error.
static const uint16_t kPR1_M_ICAB
ICAB: cable fail.
static const uint16_t kSTAT_M_RREV
RREV: ROM version.
static const uint16_t kRXR3_M_NCHN
NCHN: no data chaining.
static const uint16_t kPR0_M_BRST
RSET: breset seen.
static const uint16_t kFUNC_RPA
RPA: read phys MAC.
uint32_t fPcbb
process control block base
static const uint16_t kPR0_M_DNI
DNI: done intr.
static const uint16_t kPCMD_START
START: start tx/rx.
void SetRxPollTime(const Rtime &time)
FIXME_docs.
uint32_t fCtrRxFraLoBuf
ctr: rcvd frame lost buffers
bool RcvCallback(RethBuf::pbuf_t &pbuf)
FIXME_docs.
static const uint16_t kPC0_M_MBZ
MBZ.
void SetMacDefault(const std::string &mac)
FIXME_docs.
virtual void Start()
FIXME_docs.
RethBuf fTxBuf
tx packet buffer
size_t fPC_lapcb
PrimClist: la pcb index.
static const uint16_t kFUNC_RCSTAT
RCSTAT: read&clr status.
static const uint16_t kPR2
PR2 reg offset.
const char * MnemoPcmd(uint16_t pcmd) const
FIXME_docs.
static const uint16_t kRXR2_M_OFLO
OFLO: message overflow.
uint16_t fTxDscNxtPC[4]
tx nxt ring dsc from PrimClist
static const uint16_t kTXR2_M_STF
STF: start of frame.
static const uint16_t kSTAT_M_CERR
CERR: collision test er.
static const uint16_t kFUNC_WPA
WPA: write phys MAC.
static const uint16_t kSTAT_M_BABL
BABL: xmit on long(DELUA)
static const uint16_t kSTATE_NUHALT
ni and unibus halted
uint32_t fCtrTxByt
ctr: xmit bytes
uint32_t fCtrTxFra
ctr: xmit frames
static const uint16_t kSTATE_UHALT
unibus halted
size_t fPC_latxdscnxt
PrimClist: la txdsc nxt index.
static const uint16_t kPR0_M_SERI
SERI: status error intr.
static const bool kProbeRem
probr rem active
void StopTxRing()
FIXME_docs.
void LogRingInfo(char rxtx, char rw)
FIXME_docs.
void StopRxRing()
FIXME_docs.
void LogFrameInfo(char rxtx, const RethBuf &buf)
FIXME_docs.
int MacFilter(uint64_t mac)
FIXME_docs.
Rtime fCtrTimeCleared
ctr: time when cleared
uint16_t fRxRingIndex
rx ring index
static const uint16_t kTXR2_M_ENF
ENF: end of frame.
static const uint16_t kFUNC_WRF
WRF: write ring format.
static const uint16_t kPR1_M_XPWR
XPWR: transceive pwr fail.
virtual void Dump(std::ostream &os, int ind=0, const char *text=0, int detail=0) const
FIXME_docs.
size_t fPC_larxdsccur
PrimClist: la rxdsc index.
static const uint16_t kFUNC_RSID
RSID: read system id.
static const uint16_t kTXR3_M_RTRY
RTRY: retry failure.
uint32_t fTxRingBase
tx ring base
uint16_t fRxRingSize
rx ring size (# of entries)
uint16_t GetPr1() const
FIXME_docs.
static const uint16_t kSTAT_M_ERRS
ERRS: error summary.
void UpdateStat32(uint32_t &stat, size_t ind, uint32_t inc=1)
FIXME_docs.
static const uint16_t kTXR2_M_DEF
DEF: deferred.
int TxRingHandler()
FIXME_docs.
uint32_t RxRingDscAddr(uint16_t index) const
FIXME_docs.
static const uint16_t kTXR2_M_MORE
MORE: mult retry needed.
uint64_t fMacDefault
default MAC
uint16_t fTxRingSize
tx ring size (# of entries)
static const uint16_t kPR0_M_USCI
USCI: unsol state chang.
uint32_t fCtrRxByt
ctr: rcvd bytes
uint32_t fCtrTxBytMcast
ctr: xmit mcast bytes
size_t fPC_rdtxdscnxt
PrimClist: rd txdsc nxt index.
static const uint16_t kPR0_M_INTE
INTE: intr enable.
static const uint16_t kSTATE_PLOAD
primary load
static const uint16_t kRXR3_M_OVRN
OVRN: overrun error.
static const uint16_t kFUNC_WMAL
RMAL: write mcast MAC list.
static const uint16_t kPCMD_BOOT
BOOT: boot.
static const uint16_t kSTAT_M_PTCH
PTCH: ROM patch.
int RxRingHandler()
FIXME_docs.
static const uint16_t kRXR2_M_SEGB
SEGB: msg of seg base.
static const uint16_t kTXR2_M_MTCH
MTCH: station match.
Rw11CntlDEUNA()
Default constructor.
static const uint16_t kPR0_B_PCMDBP
PCMDBP: pcmd busy prot.
static const uint16_t kSTATE_READY
ready
static const uint16_t kPR1_M_DELUA
ID0: 1=DELUA;0=DEUNA
uint32_t fRxRingBase
rx ring base
void LogMacFunc(const char *cmd, uint64_t mac)
FIXME_docs.
uint32_t fCtrRxBytMcast
ctr: rcvd mcast bytes
static const uint16_t kMODE_M_PROM
PROM: promiscous mode.
static const uint16_t kPR0_M_PCEI
PCEI: port cmd err intr.
static const uint16_t kPR0_M_PCWWB
PCWWB: pcmd write w busy.
size_t fTxBufOffset
tx packet offset
static const uint16_t kPR1_M_PCTO
PCTO: port cmd timeout.
void ClearCtr()
FIXME_docs.
bool fPr1Delua
pr1 delua flag
bool fRingValid
ring format valid
uint16_t fTxDscNxt[4]
tx nxt ring dsc
uint32_t fCtrRxFraLoInt
ctr: rcvd frame lost int error
size_t fPC_latxdsccur
PrimClist: la txdsc cur index.
uint16_t fRxDscCurPC[4]
rx cur ring dsc from PrimClist
static const uint16_t kMODE_M_MBZ_DELUA
MBZ bit:10,8:7,5:4,1.
const char * MnemoState(uint16_t state) const
FIXME_docs.
static const uint16_t kPR0_M_RCBI
RCBI: rcv buff unavail.
uint32_t fCtrRxFraMcast
ctr: rcvd mcast frames
size_t fPC_rdtxdsccur
PrimClist: rd txdsc cur index.
static const uint16_t kFUNC_NOOP
NOOP: noop.
enum s_tx fTxRingState
tx ring handler state
static const uint16_t kMODE_M_ENAL
ENAL: ena all mcasts.
static void SetRingDsc(uint16_t dst[4], const uint16_t src[4])
FIXME_docs.
static const uint16_t kDimCtrDeuna
DEUNA count words (MAXCTR)
~Rw11CntlDEUNA()
Destructor.
static const uint16_t kPCMD_PDMD
PDMD: poll demand.
static const uint16_t kDimPlt
max MAXPLT
static const uint16_t kFUNC_RCCTR
RCCTR: read&clr counters.
uint16_t fPr1State
pr1 state
static const uint16_t kMODE_M_HDPX
HDPX: half-duplex (DEUNA)
static const uint16_t kSTAT_M_RRAM
RRAM: run from RAM.
uint64_t fMacList[2+kDimMcast]
MAC list:0=phys,1=bcast,2+=mcast.
static const uint16_t kRXR2_M_STF
STF: start of frame.
static const uint16_t kRXR3_M_UBTO
UBTO: UNIBUS timeout.
static const uint16_t kPR1
PR1 reg offset.
bool fPr1Pcto
pr1 pcto flag
void SetRunning(bool run)
FIXME_docs.
size_t fPC_rdpcb
PrimClist: rd pcb index.
static const int kLam
DEUNA default lam.
uint16_t RxRingIndexNext(uint16_t inc=1) const
FIXME_docs.
static const uint16_t kMODE_M_LOOP
LOOP: int loopback.
static const uint16_t kSTATE_RUN
running
static const uint32_t kUBA_M
bits of even unibus address
void LogMcastFunc(const char *cmd)
FIXME_docs.
int fLam
attn bit number (-1 of none)
Definition: Rw11Cntl.hpp:110
uint32_t fTraceLevel
trace level; 0=off;1=cntl
Definition: Rw11Cntl.hpp:114
std::string fType
controller type
Definition: Rw11Cntl.hpp:107
RlinkCommandList fPrimClist
clist for attn primary info
Definition: Rw11Cntl.hpp:115
RlinkConnect & Connect() const
FIXME_docs.
Definition: Rw11Cntl.ipp:56
uint16_t Base() const
FIXME_docs.
Definition: Rw11Cntl.ipp:88
Rstats fStats
statistics
Definition: Rw11Cntl.hpp:116
Rw11Probe fProbe
controller probe context
Definition: Rw11Cntl.hpp:113
Rw11Cpu & Cpu() const
FIXME_docs.
Definition: Rw11Cntl.ipp:32
void ConfigCntl(const std::string &name, uint16_t base, int lam, uint16_t probeoff, bool probeint, bool proberem)
FIXME_docs.
Definition: Rw11Cntl.cpp:156
bool fStarted
true if Start() called
Definition: Rw11Cntl.hpp:112
bool fEnable
enable flag
Definition: Rw11Cntl.hpp:111
RlinkServer & Server() const
FIXME_docs.
Definition: Rw11Cntl.ipp:48
const std::string & Name() const
FIXME_docs.
Definition: Rw11Cntl.ipp:80
RlogFile & LogFile() const
FIXME_docs.
Definition: Rw11Cntl.ipp:64
virtual void UnitSetupAll()
FIXME_docs.
Definition: Rw11Cntl.cpp:113
uint16_t fBase
controller base address
Definition: Rw11Cntl.hpp:109
FIXME_docs.
Definition: Rw11Cpu.hpp:66
void AllIAddrMapInsert(const std::string &name, uint16_t ibaddr)
FIXME_docs.
Definition: Rw11Cpu.cpp:902
void ModLalh(RlinkCommandList &clist, size_t ind, uint32_t addr, uint16_t mode=kCPAH_M_22BIT)
FIXME_docs.
Definition: Rw11Cpu.cpp:421
int AddWMem(RlinkCommandList &clist, uint32_t addr, const uint16_t *buf, size_t size, uint16_t mode=kCPAH_M_22BIT, bool singleblk=false)
FIXME_docs.
Definition: Rw11Cpu.cpp:469
int AddRMem(RlinkCommandList &clist, uint32_t addr, uint16_t *buf, size_t size, uint16_t mode=kCPAH_M_22BIT, bool singleblk=false)
FIXME_docs.
Definition: Rw11Cpu.cpp:448
void ExecWibr(uint16_t ibaddr0, uint16_t data0, uint16_t ibaddr1=0, uint16_t data1=0, uint16_t ibaddr2=0, uint16_t data2=0)
FIXME_docs.
Definition: Rw11Cpu.cpp:491
int AddWibr(RlinkCommandList &clist, uint16_t ibaddr, uint16_t data)
FIXME_docs.
Definition: Rw11Cpu.cpp:365
int AddRibr(RlinkCommandList &clist, uint16_t ibaddr)
FIXME_docs.
Definition: Rw11Cpu.cpp:354
static const uint16_t kCPAH_M_UBM22
ubmap+22bit
Definition: Rw11Cpu.hpp:228
TV & Virt()
FIXME_docs.
bool HasVirt() const
FIXME_docs.
virtual bool Snd(const RethBuf &ebuf, RerrMsg &emsg)=0
RosPrintfS< bool > RosPrintf(bool value, const char *form=0, int width=0, int prec=0)
Creates a print object for the formatted output of a bool value.
Definition: RosPrintf.ipp:38
void Mac2WList(uint64_t mac, uint16_t wlist[3])
FIXME_docs.
Definition: RethTools.ipp:21
uint64_t WList2Mac(const uint16_t wlist[3])
FIXME_docs.
Definition: RethTools.ipp:32
bool String2Mac(const std::string &str, uint64_t &mac, RerrMsg &emsg)
FIXME_docs.
Definition: RethTools.cpp:52
std::string Mac2String(uint64_t mac)
FIXME_docs.
Definition: RethTools.cpp:34
uint16_t Bytes2Word(uint16_t byte0, uint16_t byte1)
FIXME_docs.
Definition: Rtools.ipp:30
Declaration of class ReventLoop.
Definition: ReventLoop.cpp:47
bool Found() const
FIXME_docs.
Definition: Rw11Probe.cpp:52