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W11 CPU core and support modules
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cdclib.vhd
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1-- $Id: cdclib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: cdclib
7-- Description: clock domain crossing components
8--
9-- Dependencies: -
10-- Tool versions: viv 2016.1-2017.2; ghdl 0.33-0.34
11-- Revision History:
12-- Date Rev Version Comment
13-- 2019-01-02 1101 1.0.2 cdc_vector_s0,cdc_pulse interface changed
14-- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic
15-- 2016-04-02 757 1.0 Initial version
16------------------------------------------------------------------------------
17
18library ieee;
19use ieee.std_logic_1164.all;
20
21use work.slvtypes.all;
22
23package cdclib is
24
25component cdc_signal_s1 is -- cdc for signal (2 stage)
26 generic (
27 INIT : slbit := '0'); -- initial state
28 port (
29 CLKO : in slbit; -- O|output clock
30 DI : in slbit; -- I|input data
31 DO : out slbit -- O|output data
32 );
33end component;
34
35component cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input
36 generic (
37 INIT : slbit := '0'); -- initial state
38 port (
39 CLKO : in slbit; -- O|output clock
40 DI : in slbit; -- I|input data
41 DO : out slbit -- O|output data
42 );
43end component;
44
45component cdc_vector_s0 is -- cdc for vector (1 stage)
46 generic (
47 DWIDTH : positive := 16); -- data port width
48 port (
49 CLKO : in slbit; -- O|output clock
50 ENA : in slbit := '1'; -- O|capture enable
51 DI : in slv(DWIDTH-1 downto 0); -- I|input data
52 DO : out slv(DWIDTH-1 downto 0) -- O|output data
53 );
54end component;
55
56component cdc_vector_s1 is -- cdc for vector (2 stage)
57 generic (
58 DWIDTH : positive := 16); -- data port width
59 port (
60 CLKO : in slbit; -- O|output clock
61 DI : in slv(DWIDTH-1 downto 0); -- I|input data
62 DO : out slv(DWIDTH-1 downto 0) -- O|output data
63 );
64end component;
65
66component cdc_pulse is -- clock domain crossing for a pulse
67 generic (
68 POUT_SINGLE : boolean := false; -- if true: single cycle pout
69 BUSY_WACK : boolean := false; -- if true: busy waits for ack
70 INIT : slbit := '0'); -- initial state
71 port (
72 CLKM : in slbit; -- M|clock master
73 RESET : in slbit := '0'; -- M|reset
74 CLKS : in slbit; -- S|clock slave
75 PIN : in slbit; -- M|pulse in
76 BUSY : out slbit; -- M|busy
77 POUT : out slbit -- S|pulse out
78 );
79end component;
80
81component cdc_value is -- cdc for value (slow change)
82 generic (
83 DWIDTH : positive := 16); -- data port width
84 port (
85 CLKI : in slbit; -- I|input clock
86 CLKO : in slbit; -- O|output clock
87 DI : in slv(DWIDTH-1 downto 0); -- I|input data
88 DO : out slv(DWIDTH-1 downto 0); -- O|output data
89 UPDT : out slbit -- O|output data updated
90 );
91end component;
92
93end package cdclib;
in CLKM slbit
Definition: cdc_pulse.vhd:32
out BUSY slbit
Definition: cdc_pulse.vhd:36
out POUT slbit
Definition: cdc_pulse.vhd:38
in CLKS slbit
Definition: cdc_pulse.vhd:34
in PIN slbit
Definition: cdc_pulse.vhd:35
INIT slbit := '0'
Definition: cdc_pulse.vhd:30
BUSY_WACK boolean := false
Definition: cdc_pulse.vhd:29
in RESET slbit := '0'
Definition: cdc_pulse.vhd:33
POUT_SINGLE boolean := false
Definition: cdc_pulse.vhd:28
in DI slbit
in CLKO slbit
INIT slbit := '0'
out DO slbit
out DO slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:34
in CLKO slbit
Definition: cdc_value.vhd:32
in DI slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:33
in CLKI slbit
Definition: cdc_value.vhd:31
out UPDT slbit
Definition: cdc_value.vhd:36
DWIDTH positive := 16
Definition: cdc_value.vhd:29
out DO slv( DWIDTH- 1 downto 0)
in CLKO slbit
in DI slv( DWIDTH- 1 downto 0)
in ENA slbit := '1'
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31