19use ieee.std_logic_1164.
all;
56component cdc_vector_s1
is
58 DWIDTH :
positive :=
16);
61 DI :
in slv(DWIDTH
-1 downto 0);
62 DO :
out slv(DWIDTH
-1 downto 0)
BUSY_WACK boolean := false
POUT_SINGLE boolean := false
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)