clkdivce_tb Entity Reference

Inheritance diagram for clkdivce_tb:

Entities
sim	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std
slvtypes	Package <slvtypes>

Generics
CDUWIDTH	positive := 6
USECDIV	positive := 50
MSECDIV	positive := 1000

Ports
CLK	in	slbit
CE_USEC	out	slbit
CE_MSEC	out	slbit

Detailed Description

Definition at line 24 of file clkdivce_tb.vhd.

Member Data Documentation

CDUWIDTH

CDUWIDTH positive := 6

Generic

Definition at line 26 of file clkdivce_tb.vhd.

USECDIV

USECDIV positive := 50

Generic

Definition at line 27 of file clkdivce_tb.vhd.

MSECDIV

MSECDIV positive := 1000

Generic

Definition at line 28 of file clkdivce_tb.vhd.

CLK

CLK in slbit

Port

Definition at line 30 of file clkdivce_tb.vhd.

CE_USEC

CE_USEC out slbit

Port

Definition at line 31 of file clkdivce_tb.vhd.

CE_MSEC

CE_MSEC out slbit

Port

Definition at line 33 of file clkdivce_tb.vhd.

ieee

ieee

Library

Definition at line 18 of file clkdivce_tb.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 19 of file clkdivce_tb.vhd.

numeric_std

numeric_std

use clause

Definition at line 20 of file clkdivce_tb.vhd.

slvtypes

slvtypes

use clause

Definition at line 22 of file clkdivce_tb.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/genlib/tb/clkdivce_tb.vhd