sim Architecture Reference

Architecture >> sim

Processes
proc_regs	( CLK )
proc_next	( R_REGS )

Constants
regs_init	regs_type := ( slv ( to_unsigned ( USECDIV - 1 , CDUWIDTH ) ) , slv ( to_unsigned ( MSECDIV - 1 , 10 ) ) , ' 0 ' , ' 0 ' )

Signals
R_REGS	regs_type := regs_init
N_REGS	regs_type := regs_init

Records
regs_type
ucnt	slv ( CDUWIDTH - 1 downto 0 )
mcnt	slv10
usec	slbit
msec	slbit

Detailed Description

Definition at line 37 of file clkdivce_tb.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 62 of file clkdivce_tb.vhd.

proc_next()

proc_next (   R_REGS   )

Process

Definition at line 71 of file clkdivce_tb.vhd.

Member Data Documentation

regs_type

regs_type

Record

Definition at line 39 of file clkdivce_tb.vhd.

ucnt

ucnt slv ( CDUWIDTH - 1 downto 0 )

Record

Definition at line 40 of file clkdivce_tb.vhd.

mcnt

mcnt slv10

Record

Definition at line 41 of file clkdivce_tb.vhd.

usec

usec slbit

Record

Definition at line 42 of file clkdivce_tb.vhd.

msec

msec slbit

Record

Definition at line 43 of file clkdivce_tb.vhd.

regs_init

regs_init regs_type := ( slv ( to_unsigned ( USECDIV - 1 , CDUWIDTH ) ) , slv ( to_unsigned ( MSECDIV - 1 , 10 ) ) , ' 0 ' , ' 0 ' )

Constant

Definition at line 46 of file clkdivce_tb.vhd.

R_REGS

R_REGS regs_type := regs_init

Signal

Definition at line 52 of file clkdivce_tb.vhd.

N_REGS

N_REGS regs_type := regs_init

Signal

Definition at line 53 of file clkdivce_tb.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/genlib/tb/clkdivce_tb.vhd