w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Records | Signals
syn Architecture Reference
Architecture >> syn

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , RESET , CE , WE )
proc_moni  ( CLK )

Constants

memsize  positive := 2 ** AWIDTH
regs_init  regs_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 1 ' , ' 0 ' )

Signals

R_REGS  regs_type := regs_init
N_REGS  regs_type := regs_init
RAM_WE  slbit := ' 0 '
RAM_ADDR  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Records

regs_type 
waddr slv ( AWIDTH - 1 downto 0 )
raddr slv ( AWIDTH - 1 downto 0 )
empty slbit
full slbit

Instantiations

ram  ram_1swar_gen <Entity ram_1swar_gen>

Detailed Description

Definition at line 47 of file fifo_simple_dram.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regs()

proc_regs (   CLK)

Definition at line 83 of file fifo_simple_dram.vhd.

◆ proc_next()

proc_next (   R_REGS ,
  RESET ,
  CE ,
  WE  
)
Process

Definition at line 96 of file fifo_simple_dram.vhd.

◆ proc_moni()

proc_moni (   CLK  
)
Process

Definition at line 153 of file fifo_simple_dram.vhd.

Member Data Documentation

◆ regs_type

regs_type
Record

Definition at line 49 of file fifo_simple_dram.vhd.

◆ waddr

waddr slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 50 of file fifo_simple_dram.vhd.

◆ raddr

raddr slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 51 of file fifo_simple_dram.vhd.

◆ empty

empty slbit
Record

Definition at line 52 of file fifo_simple_dram.vhd.

◆ full

full slbit
Record

Definition at line 53 of file fifo_simple_dram.vhd.

◆ memsize

memsize positive := 2 ** AWIDTH
Constant

Definition at line 56 of file fifo_simple_dram.vhd.

◆ regs_init

regs_init regs_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 1 ' , ' 0 ' )
Constant

Definition at line 57 of file fifo_simple_dram.vhd.

◆ R_REGS

R_REGS regs_type := regs_init
Signal

Definition at line 63 of file fifo_simple_dram.vhd.

◆ N_REGS

N_REGS regs_type := regs_init
Signal

Definition at line 64 of file fifo_simple_dram.vhd.

◆ RAM_WE

RAM_WE slbit := ' 0 '
Signal

Definition at line 66 of file fifo_simple_dram.vhd.

◆ RAM_ADDR

RAM_ADDR slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 67 of file fifo_simple_dram.vhd.

◆ ram

ram ram_1swar_gen
Instantiation

Definition at line 81 of file fifo_simple_dram.vhd.

The documentation for this design unit was generated from the following file: