21use ieee.std_logic_1164.
all;
22use ieee.numeric_std.
all;
23use ieee.std_logic_textio.
all;
83 proc_regs:
process (
CLK)
86 if rising_edge(CLK) then
94 end process proc_regs;
101 variable iram_we : slbit := '0';
102 variable iram_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
103 variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
112 iram_addr := r.waddr;
114 iram_addr := r.raddr;
117 isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
123 n.waddr := slv(unsigned(r.waddr) + 1);
125 if unsigned(isize) = memsize-2 then
131 if r.empty = '0' then
132 n.raddr := slv(unsigned(r.raddr) + 1);
134 if unsigned(isize) = 1 then
150 end process proc_next;
154 variable oline : line;
157 if rising_edge(CLK) then
161 write(oline, now, right, 12);
162 write(oline, string'(" read on empty fifo - FAIL in "));
163 write(oline, fifo_simple_dram'path_name);
164 writeline(output, oline);
168 write(oline, now, right, 12);
169 write(oline, string'(" write on full fifo - FAIL in "));
170 write(oline, fifo_simple_dram'path_name);
171 writeline(output, oline);
177 end process proc_moni;
regs_type := regs_init N_REGS
slv( AWIDTH- 1 downto 0) :=( others => '0') RAM_ADDR
positive := 2** AWIDTH memsize
regs_type := regs_init R_REGS
regs_type :=( slv( to_unsigned( 0, AWIDTH) ), slv( to_unsigned( 0, AWIDTH) ), '1', '0') regs_init
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out SIZE slv( AWIDTH- 1 downto 0)
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)