iob_reg_io_gen Entity Reference

Inheritance diagram for iob_reg_io_gen:

Collaboration diagram for iob_reg_io_gen:

Entities
syn	architecture

Libraries
ieee

Use Clauses
std_logic_1164
slvtypes	Package <slvtypes>
xlib	Package <xlib>

Generics
DWIDTH	positive := 16
INITI	slbit := ' 0 '
INITO	slbit := ' 0 '
INITE	slbit := ' 0 '
PULL	string := " NONE "

Ports
CLK	in	slbit
CEI	in	slbit := ' 1 '
CEO	in	slbit := ' 1 '
OE	in	slbit
DI	out	slv ( DWIDTH - 1 downto 0 )
DO	in	slv ( DWIDTH - 1 downto 0 )
PAD	inout	slv ( DWIDTH - 1 downto 0 )

Detailed Description

Definition at line 28 of file iob_reg_io_gen.vhd.

Member Data Documentation

DWIDTH

DWIDTH positive := 16

Generic

Definition at line 30 of file iob_reg_io_gen.vhd.

INITI

INITI slbit := ' 0 '

Generic

Definition at line 31 of file iob_reg_io_gen.vhd.

INITO

INITO slbit := ' 0 '

Generic

Definition at line 32 of file iob_reg_io_gen.vhd.

INITE

INITE slbit := ' 0 '

Generic

Definition at line 33 of file iob_reg_io_gen.vhd.

PULL

PULL string := " NONE "

Generic

Definition at line 34 of file iob_reg_io_gen.vhd.

CLK

CLK in slbit

Port

Definition at line 36 of file iob_reg_io_gen.vhd.

CEI

CEI in slbit := ' 1 '

Port

Definition at line 37 of file iob_reg_io_gen.vhd.

CEO

CEO in slbit := ' 1 '

Port

Definition at line 38 of file iob_reg_io_gen.vhd.

OE

OE in slbit

Port

Definition at line 39 of file iob_reg_io_gen.vhd.

DI

DI out slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 40 of file iob_reg_io_gen.vhd.

DO

DO in slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 41 of file iob_reg_io_gen.vhd.

PAD

PAD inout slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 43 of file iob_reg_io_gen.vhd.

ieee

ieee

Library

Definition at line 22 of file iob_reg_io_gen.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 23 of file iob_reg_io_gen.vhd.

slvtypes

slvtypes

use clause

Definition at line 25 of file iob_reg_io_gen.vhd.

xlib

xlib	use clause

Definition at line 26 of file iob_reg_io_gen.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/xlib/iob_reg_io_gen.vhd