syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )
proc_moni	( CLK )

Constants
mwidth	positive := 2 ** BAWIDTH

Signals
CLKFX	slbit := ' 0 '
CLK	slbit := ' 0 '
R_RDVAL	slv ( RDELAY downto 0 ) := ( others = > ' 0 ' )
LOCKED	slbit := ' 0 '
LOCKED_UICLK	slbit := ' 0 '
MEM_WE	slbit := ' 0 '

Instantiations
gen_clkmui	s7_cmt_sfs <Entity s7_cmt_sfs>
cdc_locked	cdc_signal_s1_as <Entity cdc_signal_s1_as>
mcell	ram_1swsr_wfirst_gen <Entity ram_1swsr_wfirst_gen>

Detailed Description

Definition at line 63 of file migui2bram.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs

(

CLK

)

Definition at line 130 of file migui2bram.vhd.

proc_moni()

proc_moni (   CLK   )

Process

Definition at line 149 of file migui2bram.vhd.

Member Data Documentation

mwidth

mwidth positive := 2 ** BAWIDTH

Constant

Definition at line 65 of file migui2bram.vhd.

CLKFX

CLKFX slbit := ' 0 '

Signal

Definition at line 67 of file migui2bram.vhd.

CLK

CLK slbit := ' 0 '

Signal

Definition at line 68 of file migui2bram.vhd.

R_RDVAL

R_RDVAL slv ( RDELAY downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 69 of file migui2bram.vhd.

LOCKED

LOCKED slbit := ' 0 '

Signal

Definition at line 71 of file migui2bram.vhd.

LOCKED_UICLK

LOCKED_UICLK slbit := ' 0 '

Signal

Definition at line 72 of file migui2bram.vhd.

MEM_WE

slbit := '0' MEM_WE

Definition at line 107 of file migui2bram.vhd.

gen_clkmui

gen_clkmui s7_cmt_sfs

Instantiation

Definition at line 94 of file migui2bram.vhd.

cdc_locked

cdc_locked cdc_signal_s1_as

Instantiation

Definition at line 104 of file migui2bram.vhd.

mcell

mcell ram_1swsr_wfirst_gen

Instantiation

Definition at line 121 of file migui2bram.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/mig/migui2bram.vhd