w11 - vhd 0.794
W11 CPU core and support modules
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Generics | Libraries | Ports | Use Clauses
migui_nexys4d_mig Entity Reference
Inheritance diagram for migui_nexys4d_mig:
[legend]

Entities

arch_migui_nexys4d_mig  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

RST_ACT_LOW  integer := 0
BANK_WIDTH  integer := 3
CK_WIDTH  integer := 1
COL_WIDTH  integer := 10
CS_WIDTH  integer := 1
nCS_PER_RANK  integer := 1
CKE_WIDTH  integer := 1
DATA_BUF_ADDR_WIDTH  integer := 5
DQ_CNT_WIDTH  integer := 4
DQ_PER_DM  integer := 8
DM_WIDTH  integer := 2
DQ_WIDTH  integer := 16
DQS_WIDTH  integer := 2
DQS_CNT_WIDTH  integer := 1
DRAM_WIDTH  integer := 8
ECC  string := " OFF "
ECC_TEST  string := " OFF "
PAYLOAD_WIDTH  integer := 16
MEM_ADDR_ORDER  string := " ROW_BANK_COLUMN "
nBANK_MACHS  integer := 2
RANKS  integer := 1
ODT_WIDTH  integer := 1
ROW_WIDTH  integer := 13
ADDR_WIDTH  integer := 27
USE_CS_PORT  integer := 1
USE_DM_PORT  integer := 1
USE_ODT_PORT  integer := 1
PHY_CONTROL_MASTER_BANK  integer := 0
MEM_DENSITY  string := " 1Gb "
MEM_SPEEDGRADE  string := " 25E "
MEM_DEVICE_WIDTH  integer := 16
AL  string := " 0 "
nAL  integer := 0
BURST_MODE  string := " 8 "
BURST_TYPE  string := " SEQ "
CL  integer := 5
OUTPUT_DRV  string := " HIGH "
RTT_NOM  string := " 50 "
ADDR_CMD_MODE  string := " 1T "
REG_CTRL  string := " OFF "
CLKIN_PERIOD  integer := 9999
CLKFBOUT_MULT  integer := 12
DIVCLK_DIVIDE  integer := 1
CLKOUT0_PHASE  real := 0 . 0
CLKOUT0_DIVIDE  integer := 2
CLKOUT1_DIVIDE  integer := 4
CLKOUT2_DIVIDE  integer := 64
CLKOUT3_DIVIDE  integer := 16
MMCM_VCO  integer := 1200
MMCM_MULT_F  integer := 15
MMCM_DIVCLK_DIVIDE  integer := 1
tCKE  integer := 7500
tFAW  integer := 45000
tPRDI  integer := 1000000
tRAS  integer := 40000
tRCD  integer := 15000
tREFI  integer := 7800000
tRFC  integer := 127500
tRP  integer := 12500
tRRD  integer := 10000
tRTP  integer := 7500
tWTR  integer := 7500
tZQI  integer := 128000000
tZQCS  integer := 64
SIM_BYPASS_INIT_CAL  string := " OFF "
SIMULATION  string := " FALSE "
BYTE_LANES_B0  std_logic_vector ( 3 downto 0 ) := " 1111 "
BYTE_LANES_B1  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B2  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B3  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B4  std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B0  std_logic_vector ( 3 downto 0 ) := " 0101 "
DATA_CTL_B1  std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B2  std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B3  std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B4  std_logic_vector ( 3 downto 0 ) := " 0000 "
PHY_0_BITLANES  std_logic_vector ( 47 downto 0 ) := X " FFC3F7FFF3FE "
PHY_1_BITLANES  std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
PHY_2_BITLANES  std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
CK_BYTE_MAP  std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000003 "
ADDR_MAP  std_logic_vector ( 191 downto 0 ) := X " 00000000001003301A01903203A034018036012011017015 "
BANK_MAP  std_logic_vector ( 35 downto 0 ) := X " 01301601B "
CAS_MAP  std_logic_vector ( 11 downto 0 ) := X " 039 "
CKE_ODT_BYTE_MAP  std_logic_vector ( 7 downto 0 ) := X " 00 "
CKE_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000038 "
ODT_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000035 "
CS_MAP  std_logic_vector ( 119 downto 0 ) := X " 000000000000000000000000000037 "
PARITY_MAP  std_logic_vector ( 11 downto 0 ) := X " 000 "
RAS_MAP  std_logic_vector ( 11 downto 0 ) := X " 014 "
WE_MAP  std_logic_vector ( 11 downto 0 ) := X " 03B "
DQS_BYTE_MAP  std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000200 "
DATA0_MAP  std_logic_vector ( 95 downto 0 ) := X " 008004009007005001006003 "
DATA1_MAP  std_logic_vector ( 95 downto 0 ) := X " 022028020024027025026021 "
DATA2_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA3_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA4_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA5_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA6_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA7_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA8_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA9_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA10_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA11_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA12_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA13_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA14_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA15_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA16_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA17_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
MASK0_MAP  std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000029002 "
MASK1_MAP  std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
SLOT_0_CONFIG  std_logic_vector ( 7 downto 0 ) := " 00000001 "
SLOT_1_CONFIG  std_logic_vector ( 7 downto 0 ) := " 00000000 "
IBUF_LPWR_MODE  string := " OFF "
DATA_IO_IDLE_PWRDWN  string := " ON "
BANK_TYPE  string := " HR_IO "
DATA_IO_PRIM_TYPE  string := " HR_LP "
CKE_ODT_AUX  string := " FALSE "
USER_REFRESH  string := " OFF "
WRLVL  string := " OFF "
ORDERING  string := " STRICT "
CALIB_ROW_ADD  std_logic_vector ( 15 downto 0 ) := X " 0000 "
CALIB_COL_ADD  std_logic_vector ( 11 downto 0 ) := X " 000 "
CALIB_BA_ADD  std_logic_vector ( 2 downto 0 ) := " 000 "
TCQ  integer := 100
IODELAY_GRP0  string := " MIGUI_NEXYS4D_IODELAY_MIG0 "
IODELAY_GRP1  string := " MIGUI_NEXYS4D_IODELAY_MIG1 "
SYSCLK_TYPE  string := " NO_BUFFER "
REFCLK_TYPE  string := " NO_BUFFER "
SYS_RST_PORT  string := " FALSE "
FPGA_SPEED_GRADE  integer := 1
REF_CLK_MMCM_IODELAY_CTRL  string := " FALSE "
CMD_PIPE_PLUS1  string := " ON "
DRAM_TYPE  string := " DDR2 "
CAL_WIDTH  string := " HALF "
STARVE_LIMIT  integer := 2
REFCLK_FREQ  real := 200 . 0
DIFF_TERM_REFCLK  string := " TRUE "
tCK  integer := 3333
nCK_PER_CLK  integer := 4
DIFF_TERM_SYSCLK  string := " TRUE "
DEBUG_PORT  string := " OFF "
TEMP_MON_CONTROL  string := " EXTERNAL "

Ports

ddr2_dq   inout   std_logic_vector ( DQ_WIDTH - 1 downto 0 )
ddr2_dqs_p   inout   std_logic_vector ( DQS_WIDTH - 1 downto 0 )
ddr2_dqs_n   inout   std_logic_vector ( DQS_WIDTH - 1 downto 0 )
ddr2_addr   out   std_logic_vector ( ROW_WIDTH - 1 downto 0 )
ddr2_ba   out   std_logic_vector ( BANK_WIDTH - 1 downto 0 )
ddr2_ras_n   out   std_logic
ddr2_cas_n   out   std_logic
ddr2_we_n   out   std_logic
ddr2_ck_p   out   std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr2_ck_n   out   std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr2_cke   out   std_logic_vector ( CKE_WIDTH - 1 downto 0 )
ddr2_cs_n   out   std_logic_vector ( ( CS_WIDTH * nCS_PER_RANK ) - 1 downto 0 )
ddr2_dm   out   std_logic_vector ( DM_WIDTH - 1 downto 0 )
ddr2_odt   out   std_logic_vector ( ODT_WIDTH - 1 downto 0 )
sys_clk_i   in   std_logic
clk_ref_i   in   std_logic
app_addr   in   std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
app_cmd   in   std_logic_vector ( 2 downto 0 )
app_en   in   std_logic
app_wdf_data   in   std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )
app_wdf_end   in   std_logic
app_wdf_mask   in   std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH / 8 ) - 1 downto 0 )
app_wdf_wren   in   std_logic
app_rd_data   out   std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )
app_rd_data_end   out   std_logic
app_rd_data_valid   out   std_logic
app_rdy   out   std_logic
app_wdf_rdy   out   std_logic
app_sr_req   in   std_logic
app_ref_req   in   std_logic
app_zq_req   in   std_logic
app_sr_active   out   std_logic
app_ref_ack   out   std_logic
app_zq_ack   out   std_logic
ui_clk   out   std_logic
ui_clk_sync_rst   out   std_logic
init_calib_complete   out   std_logic
device_temp_i   in   std_logic_vector ( 11 downto 0 )
sys_rst   in   std_logic

Detailed Description

Definition at line 77 of file migui_nexys4d_mig.vhd.

Member Data Documentation

◆ RST_ACT_LOW

RST_ACT_LOW integer := 0
Generic

Definition at line 80 of file migui_nexys4d_mig.vhd.

◆ BANK_WIDTH

BANK_WIDTH integer := 3
Generic

Definition at line 86 of file migui_nexys4d_mig.vhd.

◆ CK_WIDTH

CK_WIDTH integer := 1
Generic

Definition at line 88 of file migui_nexys4d_mig.vhd.

◆ COL_WIDTH

COL_WIDTH integer := 10
Generic

Definition at line 90 of file migui_nexys4d_mig.vhd.

◆ CS_WIDTH

CS_WIDTH integer := 1
Generic

Definition at line 92 of file migui_nexys4d_mig.vhd.

◆ nCS_PER_RANK

nCS_PER_RANK integer := 1
Generic

Definition at line 94 of file migui_nexys4d_mig.vhd.

◆ CKE_WIDTH

CKE_WIDTH integer := 1
Generic

Definition at line 96 of file migui_nexys4d_mig.vhd.

◆ DATA_BUF_ADDR_WIDTH

DATA_BUF_ADDR_WIDTH integer := 5
Generic

Definition at line 98 of file migui_nexys4d_mig.vhd.

◆ DQ_CNT_WIDTH

DQ_CNT_WIDTH integer := 4
Generic

Definition at line 99 of file migui_nexys4d_mig.vhd.

◆ DQ_PER_DM

DQ_PER_DM integer := 8
Generic

Definition at line 101 of file migui_nexys4d_mig.vhd.

◆ DM_WIDTH

DM_WIDTH integer := 2
Generic

Definition at line 102 of file migui_nexys4d_mig.vhd.

◆ DQ_WIDTH

DQ_WIDTH integer := 16
Generic

Definition at line 104 of file migui_nexys4d_mig.vhd.

◆ DQS_WIDTH

DQS_WIDTH integer := 2
Generic

Definition at line 106 of file migui_nexys4d_mig.vhd.

◆ DQS_CNT_WIDTH

DQS_CNT_WIDTH integer := 1
Generic

Definition at line 107 of file migui_nexys4d_mig.vhd.

◆ DRAM_WIDTH

DRAM_WIDTH integer := 8
Generic

Definition at line 109 of file migui_nexys4d_mig.vhd.

◆ ECC

ECC string := " OFF "
Generic

Definition at line 111 of file migui_nexys4d_mig.vhd.

◆ ECC_TEST

ECC_TEST string := " OFF "
Generic

Definition at line 112 of file migui_nexys4d_mig.vhd.

◆ PAYLOAD_WIDTH

PAYLOAD_WIDTH integer := 16
Generic

Definition at line 113 of file migui_nexys4d_mig.vhd.

◆ MEM_ADDR_ORDER

MEM_ADDR_ORDER string := " ROW_BANK_COLUMN "
Generic

Definition at line 114 of file migui_nexys4d_mig.vhd.

◆ nBANK_MACHS

nBANK_MACHS integer := 2
Generic

Definition at line 124 of file migui_nexys4d_mig.vhd.

◆ RANKS

RANKS integer := 1
Generic

Definition at line 125 of file migui_nexys4d_mig.vhd.

◆ ODT_WIDTH

ODT_WIDTH integer := 1
Generic

Definition at line 127 of file migui_nexys4d_mig.vhd.

◆ ROW_WIDTH

ROW_WIDTH integer := 13
Generic

Definition at line 129 of file migui_nexys4d_mig.vhd.

◆ ADDR_WIDTH

ADDR_WIDTH integer := 27
Generic

Definition at line 131 of file migui_nexys4d_mig.vhd.

◆ USE_CS_PORT

USE_CS_PORT integer := 1
Generic

Definition at line 136 of file migui_nexys4d_mig.vhd.

◆ USE_DM_PORT

USE_DM_PORT integer := 1
Generic

Definition at line 141 of file migui_nexys4d_mig.vhd.

◆ USE_ODT_PORT

USE_ODT_PORT integer := 1
Generic

Definition at line 148 of file migui_nexys4d_mig.vhd.

◆ PHY_CONTROL_MASTER_BANK

PHY_CONTROL_MASTER_BANK integer := 0
Generic

Definition at line 151 of file migui_nexys4d_mig.vhd.

◆ MEM_DENSITY

MEM_DENSITY string := " 1Gb "
Generic

Definition at line 154 of file migui_nexys4d_mig.vhd.

◆ MEM_SPEEDGRADE

MEM_SPEEDGRADE string := " 25E "
Generic

Definition at line 157 of file migui_nexys4d_mig.vhd.

◆ MEM_DEVICE_WIDTH

MEM_DEVICE_WIDTH integer := 16
Generic

Definition at line 160 of file migui_nexys4d_mig.vhd.

◆ AL

AL string := " 0 "
Generic

Definition at line 167 of file migui_nexys4d_mig.vhd.

◆ nAL

nAL integer := 0
Generic

Definition at line 173 of file migui_nexys4d_mig.vhd.

◆ BURST_MODE

BURST_MODE string := " 8 "
Generic

Definition at line 176 of file migui_nexys4d_mig.vhd.

◆ BURST_TYPE

BURST_TYPE string := " SEQ "
Generic

Definition at line 183 of file migui_nexys4d_mig.vhd.

◆ CL

CL integer := 5
Generic

Definition at line 188 of file migui_nexys4d_mig.vhd.

◆ OUTPUT_DRV

OUTPUT_DRV string := " HIGH "
Generic

Definition at line 192 of file migui_nexys4d_mig.vhd.

◆ RTT_NOM

RTT_NOM string := " 50 "
Generic

Definition at line 196 of file migui_nexys4d_mig.vhd.

◆ ADDR_CMD_MODE

ADDR_CMD_MODE string := " 1T "
Generic

Definition at line 201 of file migui_nexys4d_mig.vhd.

◆ REG_CTRL

REG_CTRL string := " OFF "
Generic

Definition at line 203 of file migui_nexys4d_mig.vhd.

◆ CLKIN_PERIOD

CLKIN_PERIOD integer := 9999
Generic

Definition at line 211 of file migui_nexys4d_mig.vhd.

◆ CLKFBOUT_MULT

CLKFBOUT_MULT integer := 12
Generic

Definition at line 213 of file migui_nexys4d_mig.vhd.

◆ DIVCLK_DIVIDE

DIVCLK_DIVIDE integer := 1
Generic

Definition at line 215 of file migui_nexys4d_mig.vhd.

◆ CLKOUT0_PHASE

CLKOUT0_PHASE real := 0 . 0
Generic

Definition at line 217 of file migui_nexys4d_mig.vhd.

◆ CLKOUT0_DIVIDE

CLKOUT0_DIVIDE integer := 2
Generic

Definition at line 219 of file migui_nexys4d_mig.vhd.

◆ CLKOUT1_DIVIDE

CLKOUT1_DIVIDE integer := 4
Generic

Definition at line 221 of file migui_nexys4d_mig.vhd.

◆ CLKOUT2_DIVIDE

CLKOUT2_DIVIDE integer := 64
Generic

Definition at line 223 of file migui_nexys4d_mig.vhd.

◆ CLKOUT3_DIVIDE

CLKOUT3_DIVIDE integer := 16
Generic

Definition at line 225 of file migui_nexys4d_mig.vhd.

◆ MMCM_VCO

MMCM_VCO integer := 1200
Generic

Definition at line 227 of file migui_nexys4d_mig.vhd.

◆ MMCM_MULT_F

MMCM_MULT_F integer := 15
Generic

Definition at line 229 of file migui_nexys4d_mig.vhd.

◆ MMCM_DIVCLK_DIVIDE

MMCM_DIVCLK_DIVIDE integer := 1
Generic

Definition at line 231 of file migui_nexys4d_mig.vhd.

◆ tCKE

tCKE integer := 7500
Generic

Definition at line 238 of file migui_nexys4d_mig.vhd.

◆ tFAW

tFAW integer := 45000
Generic

Definition at line 240 of file migui_nexys4d_mig.vhd.

◆ tPRDI

tPRDI integer := 1000000
Generic

Definition at line 242 of file migui_nexys4d_mig.vhd.

◆ tRAS

tRAS integer := 40000
Generic

Definition at line 244 of file migui_nexys4d_mig.vhd.

◆ tRCD

tRCD integer := 15000
Generic

Definition at line 246 of file migui_nexys4d_mig.vhd.

◆ tREFI

tREFI integer := 7800000
Generic

Definition at line 248 of file migui_nexys4d_mig.vhd.

◆ tRFC

tRFC integer := 127500
Generic

Definition at line 250 of file migui_nexys4d_mig.vhd.

◆ tRP

tRP integer := 12500
Generic

Definition at line 252 of file migui_nexys4d_mig.vhd.

◆ tRRD

tRRD integer := 10000
Generic

Definition at line 254 of file migui_nexys4d_mig.vhd.

◆ tRTP

tRTP integer := 7500
Generic

Definition at line 256 of file migui_nexys4d_mig.vhd.

◆ tWTR

tWTR integer := 7500
Generic

Definition at line 258 of file migui_nexys4d_mig.vhd.

◆ tZQI

tZQI integer := 128000000
Generic

Definition at line 260 of file migui_nexys4d_mig.vhd.

◆ tZQCS

tZQCS integer := 64
Generic

Definition at line 262 of file migui_nexys4d_mig.vhd.

◆ SIM_BYPASS_INIT_CAL

SIM_BYPASS_INIT_CAL string := " OFF "
Generic

Definition at line 268 of file migui_nexys4d_mig.vhd.

◆ SIMULATION

SIMULATION string := " FALSE "
Generic

Definition at line 275 of file migui_nexys4d_mig.vhd.

◆ BYTE_LANES_B0

BYTE_LANES_B0 std_logic_vector ( 3 downto 0 ) := " 1111 "
Generic

Definition at line 284 of file migui_nexys4d_mig.vhd.

◆ BYTE_LANES_B1

BYTE_LANES_B1 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 286 of file migui_nexys4d_mig.vhd.

◆ BYTE_LANES_B2

BYTE_LANES_B2 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 288 of file migui_nexys4d_mig.vhd.

◆ BYTE_LANES_B3

BYTE_LANES_B3 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 290 of file migui_nexys4d_mig.vhd.

◆ BYTE_LANES_B4

BYTE_LANES_B4 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 292 of file migui_nexys4d_mig.vhd.

◆ DATA_CTL_B0

DATA_CTL_B0 std_logic_vector ( 3 downto 0 ) := " 0101 "
Generic

Definition at line 294 of file migui_nexys4d_mig.vhd.

◆ DATA_CTL_B1

DATA_CTL_B1 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 299 of file migui_nexys4d_mig.vhd.

◆ DATA_CTL_B2

DATA_CTL_B2 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 304 of file migui_nexys4d_mig.vhd.

◆ DATA_CTL_B3

DATA_CTL_B3 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 309 of file migui_nexys4d_mig.vhd.

◆ DATA_CTL_B4

DATA_CTL_B4 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 314 of file migui_nexys4d_mig.vhd.

◆ PHY_0_BITLANES

PHY_0_BITLANES std_logic_vector ( 47 downto 0 ) := X " FFC3F7FFF3FE "
Generic

Definition at line 319 of file migui_nexys4d_mig.vhd.

◆ PHY_1_BITLANES

PHY_1_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
Generic

Definition at line 320 of file migui_nexys4d_mig.vhd.

◆ PHY_2_BITLANES

PHY_2_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
Generic

Definition at line 321 of file migui_nexys4d_mig.vhd.

◆ CK_BYTE_MAP

CK_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000003 "
Generic

Definition at line 325 of file migui_nexys4d_mig.vhd.

◆ ADDR_MAP

ADDR_MAP std_logic_vector ( 191 downto 0 ) := X " 00000000001003301A01903203A034018036012011017015 "
Generic

Definition at line 327 of file migui_nexys4d_mig.vhd.

◆ BANK_MAP

BANK_MAP std_logic_vector ( 35 downto 0 ) := X " 01301601B "
Generic

Definition at line 328 of file migui_nexys4d_mig.vhd.

◆ CAS_MAP

CAS_MAP std_logic_vector ( 11 downto 0 ) := X " 039 "
Generic

Definition at line 329 of file migui_nexys4d_mig.vhd.

◆ CKE_ODT_BYTE_MAP

CKE_ODT_BYTE_MAP std_logic_vector ( 7 downto 0 ) := X " 00 "
Generic

Definition at line 330 of file migui_nexys4d_mig.vhd.

◆ CKE_MAP

CKE_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000038 "
Generic

Definition at line 331 of file migui_nexys4d_mig.vhd.

◆ ODT_MAP

ODT_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000035 "
Generic

Definition at line 332 of file migui_nexys4d_mig.vhd.

◆ CS_MAP

CS_MAP std_logic_vector ( 119 downto 0 ) := X " 000000000000000000000000000037 "
Generic

Definition at line 333 of file migui_nexys4d_mig.vhd.

◆ PARITY_MAP

PARITY_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 334 of file migui_nexys4d_mig.vhd.

◆ RAS_MAP

RAS_MAP std_logic_vector ( 11 downto 0 ) := X " 014 "
Generic

Definition at line 335 of file migui_nexys4d_mig.vhd.

◆ WE_MAP

WE_MAP std_logic_vector ( 11 downto 0 ) := X " 03B "
Generic

Definition at line 336 of file migui_nexys4d_mig.vhd.

◆ DQS_BYTE_MAP

DQS_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000200 "
Generic

Definition at line 338 of file migui_nexys4d_mig.vhd.

◆ DATA0_MAP

DATA0_MAP std_logic_vector ( 95 downto 0 ) := X " 008004009007005001006003 "
Generic

Definition at line 339 of file migui_nexys4d_mig.vhd.

◆ DATA1_MAP

DATA1_MAP std_logic_vector ( 95 downto 0 ) := X " 022028020024027025026021 "
Generic

Definition at line 340 of file migui_nexys4d_mig.vhd.

◆ DATA2_MAP

DATA2_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 341 of file migui_nexys4d_mig.vhd.

◆ DATA3_MAP

DATA3_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 342 of file migui_nexys4d_mig.vhd.

◆ DATA4_MAP

DATA4_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 343 of file migui_nexys4d_mig.vhd.

◆ DATA5_MAP

DATA5_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 344 of file migui_nexys4d_mig.vhd.

◆ DATA6_MAP

DATA6_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 345 of file migui_nexys4d_mig.vhd.

◆ DATA7_MAP

DATA7_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 346 of file migui_nexys4d_mig.vhd.

◆ DATA8_MAP

DATA8_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 347 of file migui_nexys4d_mig.vhd.

◆ DATA9_MAP

DATA9_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 348 of file migui_nexys4d_mig.vhd.

◆ DATA10_MAP

DATA10_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 349 of file migui_nexys4d_mig.vhd.

◆ DATA11_MAP

DATA11_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 350 of file migui_nexys4d_mig.vhd.

◆ DATA12_MAP

DATA12_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 351 of file migui_nexys4d_mig.vhd.

◆ DATA13_MAP

DATA13_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 352 of file migui_nexys4d_mig.vhd.

◆ DATA14_MAP

DATA14_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 353 of file migui_nexys4d_mig.vhd.

◆ DATA15_MAP

DATA15_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 354 of file migui_nexys4d_mig.vhd.

◆ DATA16_MAP

DATA16_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 355 of file migui_nexys4d_mig.vhd.

◆ DATA17_MAP

DATA17_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 356 of file migui_nexys4d_mig.vhd.

◆ MASK0_MAP

MASK0_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000029002 "
Generic

Definition at line 357 of file migui_nexys4d_mig.vhd.

◆ MASK1_MAP

MASK1_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
Generic

Definition at line 358 of file migui_nexys4d_mig.vhd.

◆ SLOT_0_CONFIG

SLOT_0_CONFIG std_logic_vector ( 7 downto 0 ) := " 00000001 "
Generic

Definition at line 360 of file migui_nexys4d_mig.vhd.

◆ SLOT_1_CONFIG

SLOT_1_CONFIG std_logic_vector ( 7 downto 0 ) := " 00000000 "
Generic

Definition at line 362 of file migui_nexys4d_mig.vhd.

◆ IBUF_LPWR_MODE

IBUF_LPWR_MODE string := " OFF "
Generic

Definition at line 368 of file migui_nexys4d_mig.vhd.

◆ DATA_IO_IDLE_PWRDWN

DATA_IO_IDLE_PWRDWN string := " ON "
Generic

Definition at line 370 of file migui_nexys4d_mig.vhd.

◆ BANK_TYPE

BANK_TYPE string := " HR_IO "
Generic

Definition at line 372 of file migui_nexys4d_mig.vhd.

◆ DATA_IO_PRIM_TYPE

DATA_IO_PRIM_TYPE string := " HR_LP "
Generic

Definition at line 374 of file migui_nexys4d_mig.vhd.

◆ CKE_ODT_AUX

CKE_ODT_AUX string := " FALSE "
Generic

Definition at line 376 of file migui_nexys4d_mig.vhd.

◆ USER_REFRESH

USER_REFRESH string := " OFF "
Generic

Definition at line 377 of file migui_nexys4d_mig.vhd.

◆ WRLVL

WRLVL string := " OFF "
Generic

Definition at line 378 of file migui_nexys4d_mig.vhd.

◆ ORDERING

ORDERING string := " STRICT "
Generic

Definition at line 381 of file migui_nexys4d_mig.vhd.

◆ CALIB_ROW_ADD

CALIB_ROW_ADD std_logic_vector ( 15 downto 0 ) := X " 0000 "
Generic

Definition at line 383 of file migui_nexys4d_mig.vhd.

◆ CALIB_COL_ADD

CALIB_COL_ADD std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 386 of file migui_nexys4d_mig.vhd.

◆ CALIB_BA_ADD

CALIB_BA_ADD std_logic_vector ( 2 downto 0 ) := " 000 "
Generic

Definition at line 389 of file migui_nexys4d_mig.vhd.

◆ TCQ

TCQ integer := 100
Generic

Definition at line 392 of file migui_nexys4d_mig.vhd.

◆ IODELAY_GRP0

IODELAY_GRP0 string := " MIGUI_NEXYS4D_IODELAY_MIG0 "
Generic

Definition at line 394 of file migui_nexys4d_mig.vhd.

◆ IODELAY_GRP1

IODELAY_GRP1 string := " MIGUI_NEXYS4D_IODELAY_MIG1 "
Generic

Definition at line 398 of file migui_nexys4d_mig.vhd.

◆ SYSCLK_TYPE

SYSCLK_TYPE string := " NO_BUFFER "
Generic

Definition at line 402 of file migui_nexys4d_mig.vhd.

◆ REFCLK_TYPE

REFCLK_TYPE string := " NO_BUFFER "
Generic

Definition at line 405 of file migui_nexys4d_mig.vhd.

◆ SYS_RST_PORT

SYS_RST_PORT string := " FALSE "
Generic

Definition at line 408 of file migui_nexys4d_mig.vhd.

◆ FPGA_SPEED_GRADE

FPGA_SPEED_GRADE integer := 1
Generic

Definition at line 412 of file migui_nexys4d_mig.vhd.

◆ REF_CLK_MMCM_IODELAY_CTRL

REF_CLK_MMCM_IODELAY_CTRL string := " FALSE "
Generic

Definition at line 414 of file migui_nexys4d_mig.vhd.

◆ CMD_PIPE_PLUS1

CMD_PIPE_PLUS1 string := " ON "
Generic

Definition at line 416 of file migui_nexys4d_mig.vhd.

◆ DRAM_TYPE

DRAM_TYPE string := " DDR2 "
Generic

Definition at line 418 of file migui_nexys4d_mig.vhd.

◆ CAL_WIDTH

CAL_WIDTH string := " HALF "
Generic

Definition at line 419 of file migui_nexys4d_mig.vhd.

◆ STARVE_LIMIT

STARVE_LIMIT integer := 2
Generic

Definition at line 420 of file migui_nexys4d_mig.vhd.

◆ REFCLK_FREQ

REFCLK_FREQ real := 200 . 0
Generic

Definition at line 426 of file migui_nexys4d_mig.vhd.

◆ DIFF_TERM_REFCLK

DIFF_TERM_REFCLK string := " TRUE "
Generic

Definition at line 428 of file migui_nexys4d_mig.vhd.

◆ tCK

tCK integer := 3333
Generic

Definition at line 434 of file migui_nexys4d_mig.vhd.

◆ nCK_PER_CLK

nCK_PER_CLK integer := 4
Generic

Definition at line 437 of file migui_nexys4d_mig.vhd.

◆ DIFF_TERM_SYSCLK

DIFF_TERM_SYSCLK string := " TRUE "
Generic

Definition at line 439 of file migui_nexys4d_mig.vhd.

◆ DEBUG_PORT

DEBUG_PORT string := " OFF "
Generic

Definition at line 446 of file migui_nexys4d_mig.vhd.

◆ TEMP_MON_CONTROL

TEMP_MON_CONTROL string := " EXTERNAL "
Generic

Definition at line 459 of file migui_nexys4d_mig.vhd.

◆ ddr2_dq

ddr2_dq inout std_logic_vector ( DQ_WIDTH - 1 downto 0 )
Port

Definition at line 463 of file migui_nexys4d_mig.vhd.

◆ ddr2_dqs_p

ddr2_dqs_p inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Port

Definition at line 464 of file migui_nexys4d_mig.vhd.

◆ ddr2_dqs_n

ddr2_dqs_n inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Port

Definition at line 465 of file migui_nexys4d_mig.vhd.

◆ ddr2_addr

ddr2_addr out std_logic_vector ( ROW_WIDTH - 1 downto 0 )
Port

Definition at line 468 of file migui_nexys4d_mig.vhd.

◆ ddr2_ba

ddr2_ba out std_logic_vector ( BANK_WIDTH - 1 downto 0 )
Port

Definition at line 469 of file migui_nexys4d_mig.vhd.

◆ ddr2_ras_n

ddr2_ras_n out std_logic
Port

Definition at line 470 of file migui_nexys4d_mig.vhd.

◆ ddr2_cas_n

ddr2_cas_n out std_logic
Port

Definition at line 471 of file migui_nexys4d_mig.vhd.

◆ ddr2_we_n

ddr2_we_n out std_logic
Port

Definition at line 472 of file migui_nexys4d_mig.vhd.

◆ ddr2_ck_p

ddr2_ck_p out std_logic_vector ( CK_WIDTH - 1 downto 0 )
Port

Definition at line 473 of file migui_nexys4d_mig.vhd.

◆ ddr2_ck_n

ddr2_ck_n out std_logic_vector ( CK_WIDTH - 1 downto 0 )
Port

Definition at line 474 of file migui_nexys4d_mig.vhd.

◆ ddr2_cke

ddr2_cke out std_logic_vector ( CKE_WIDTH - 1 downto 0 )
Port

Definition at line 475 of file migui_nexys4d_mig.vhd.

◆ ddr2_cs_n

ddr2_cs_n out std_logic_vector ( ( CS_WIDTH * nCS_PER_RANK ) - 1 downto 0 )
Port

Definition at line 476 of file migui_nexys4d_mig.vhd.

◆ ddr2_dm

ddr2_dm out std_logic_vector ( DM_WIDTH - 1 downto 0 )
Port

Definition at line 477 of file migui_nexys4d_mig.vhd.

◆ ddr2_odt

ddr2_odt out std_logic_vector ( ODT_WIDTH - 1 downto 0 )
Port

Definition at line 478 of file migui_nexys4d_mig.vhd.

◆ sys_clk_i

sys_clk_i in std_logic
Port

Definition at line 482 of file migui_nexys4d_mig.vhd.

◆ clk_ref_i

clk_ref_i in std_logic
Port

Definition at line 484 of file migui_nexys4d_mig.vhd.

◆ app_addr

app_addr in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
Port

Definition at line 486 of file migui_nexys4d_mig.vhd.

◆ app_cmd

app_cmd in std_logic_vector ( 2 downto 0 )
Port

Definition at line 487 of file migui_nexys4d_mig.vhd.

◆ app_en

app_en in std_logic
Port

Definition at line 488 of file migui_nexys4d_mig.vhd.

◆ app_wdf_data

app_wdf_data in std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )
Port

Definition at line 489 of file migui_nexys4d_mig.vhd.

◆ app_wdf_end

app_wdf_end in std_logic
Port

Definition at line 490 of file migui_nexys4d_mig.vhd.

◆ app_wdf_mask

app_wdf_mask in std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH / 8 ) - 1 downto 0 )
Port

Definition at line 491 of file migui_nexys4d_mig.vhd.

◆ app_wdf_wren

app_wdf_wren in std_logic
Port

Definition at line 492 of file migui_nexys4d_mig.vhd.

◆ app_rd_data

app_rd_data out std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )
Port

Definition at line 493 of file migui_nexys4d_mig.vhd.

◆ app_rd_data_end

app_rd_data_end out std_logic
Port

Definition at line 494 of file migui_nexys4d_mig.vhd.

◆ app_rd_data_valid

app_rd_data_valid out std_logic
Port

Definition at line 495 of file migui_nexys4d_mig.vhd.

◆ app_rdy

app_rdy out std_logic
Port

Definition at line 496 of file migui_nexys4d_mig.vhd.

◆ app_wdf_rdy

app_wdf_rdy out std_logic
Port

Definition at line 497 of file migui_nexys4d_mig.vhd.

◆ app_sr_req

app_sr_req in std_logic
Port

Definition at line 498 of file migui_nexys4d_mig.vhd.

◆ app_ref_req

app_ref_req in std_logic
Port

Definition at line 499 of file migui_nexys4d_mig.vhd.

◆ app_zq_req

app_zq_req in std_logic
Port

Definition at line 500 of file migui_nexys4d_mig.vhd.

◆ app_sr_active

app_sr_active out std_logic
Port

Definition at line 501 of file migui_nexys4d_mig.vhd.

◆ app_ref_ack

app_ref_ack out std_logic
Port

Definition at line 502 of file migui_nexys4d_mig.vhd.

◆ app_zq_ack

app_zq_ack out std_logic
Port

Definition at line 503 of file migui_nexys4d_mig.vhd.

◆ ui_clk

ui_clk out std_logic
Port

Definition at line 504 of file migui_nexys4d_mig.vhd.

◆ ui_clk_sync_rst

ui_clk_sync_rst out std_logic
Port

Definition at line 505 of file migui_nexys4d_mig.vhd.

◆ init_calib_complete

init_calib_complete out std_logic
Port

Definition at line 508 of file migui_nexys4d_mig.vhd.

◆ device_temp_i

device_temp_i in std_logic_vector ( 11 downto 0 )
Port

Definition at line 509 of file migui_nexys4d_mig.vhd.

◆ sys_rst

sys_rst in std_logic
Port

Definition at line 519 of file migui_nexys4d_mig.vhd.

◆ ieee

ieee
Library

Definition at line 72 of file migui_nexys4d_mig.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 73 of file migui_nexys4d_mig.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 74 of file migui_nexys4d_mig.vhd.

The documentation for this design unit was generated from the following files: