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Components | Constants | Functions | Instantiations | Signals
arch_migui_nexys4d_mig Architecture Reference
Architecture >> arch_migui_nexys4d_mig

Functions

integer   clogb2 ( size: in integer )
integer   ECCWIDTH
integer   XWIDTH
string   TEMP_MON
integer   clogb2 ( size: in integer )
integer   ECCWIDTH
integer   XWIDTH
string   TEMP_MON
integer   clogb2 ( size: in integer )
integer   ECCWIDTH
integer   XWIDTH
string   TEMP_MON
integer   clogb2 ( size: in integer )
integer   ECCWIDTH
integer   XWIDTH
string   TEMP_MON

Components

mig_7series_v4_2_iodelay_ctrl 
mig_7series_v4_2_clk_ibuf 
mig_7series_v4_2_infrastructure 
mig_7series_v4_2_tempmon 
mig_7series_v4_2_memc_ui_top_std 

Constants

DATA_WIDTH  integer := 16
RANK_WIDTH  integer := clogb2 ( RANKS )
TAPSPERKCLK  integer := 56
BM_CNT_WIDTH  integer := clogb2 ( nBANK_MACHS )
ECC_WIDTH  integer := ECCWIDTH
DATA_BUF_OFFSET_WIDTH  integer := 1
MC_ERR_ADDR_WIDTH  integer := XWIDTH+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH + DATA_BUF_OFFSET_WIDTH
APP_DATA_WIDTH  integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH
APP_MASK_WIDTH  integer := APP_DATA_WIDTH / 8
TEMP_MON_EN  string := TEMP_MON
tTEMPSAMPLE  integer := 10000000
XADC_CLK_PERIOD  integer := 5000

Signals

bank_mach_next  std_logic_vector ( BM_CNT_WIDTH - 1 downto 0 )
clk  std_logic
clk_ref  std_logic_vector ( 1 downto 0 )
iodelay_ctrl_rdy  std_logic_vector ( 1 downto 0 )
clk_ref_in  std_logic
sys_rst_o  std_logic
clk_div2  std_logic
rst_div2  std_logic
freq_refclk  std_logic
mem_refclk  std_logic
pll_locked  std_logic
sync_pulse  std_logic
mmcm_ps_clk  std_logic
poc_sample_pd  std_logic
psen  std_logic
psincdec  std_logic
psdone  std_logic
iddr_rst  std_logic
ref_dll_lock  std_logic
rst_phaser_ref  std_logic
rst  std_logic
app_ecc_multiple_err  std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 )
app_ecc_single_err  std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 )
ddr2_reset_n  std_logic
ddr2_parity  std_logic
init_calib_complete_i  std_logic
sys_clk_p  std_logic
sys_clk_n  std_logic
mmcm_clk  std_logic
clk_ref_p  std_logic
clk_ref_n  std_logic
device_temp_s  std_logic_vector ( 11 downto 0 )
dbg_idel_down_all  std_logic
dbg_idel_down_cpt  std_logic
dbg_idel_up_all  std_logic
dbg_idel_up_cpt  std_logic
dbg_sel_all_idel_cpt  std_logic
dbg_sel_idel_cpt  std_logic_vector ( DQS_CNT_WIDTH - 1 downto 0 )
dbg_po_f_stg23_sel  std_logic
dbg_sel_pi_incdec  std_logic
dbg_sel_po_incdec  std_logic
dbg_byte_sel  std_logic_vector ( DQS_CNT_WIDTH downto 0 )
dbg_pi_f_inc  std_logic
dbg_po_f_inc  std_logic
dbg_pi_f_dec  std_logic
dbg_po_f_dec  std_logic
dbg_pi_counter_read_val  std_logic_vector ( 5 downto 0 )
dbg_po_counter_read_val  std_logic_vector ( 8 downto 0 )
dbg_prbs_final_dqs_tap_cnt_r  std_logic_vector ( 11 downto 0 )
dbg_prbs_first_edge_taps  std_logic_vector ( 11 downto 0 )
dbg_prbs_second_edge_taps  std_logic_vector ( 11 downto 0 )
dbg_cpt_tap_cnt  std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
dbg_dq_idelay_tap_cnt  std_logic_vector ( ( 5 * DQS_WIDTH * RANKS ) - 1 downto 0 )
dbg_calib_top  std_logic_vector ( 255 downto 0 )
dbg_cpt_first_edge_cnt  std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
dbg_cpt_second_edge_cnt  std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
dbg_rd_data_offset  std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
dbg_phy_rdlvl  std_logic_vector ( 255 downto 0 )
dbg_phy_wrcal  std_logic_vector ( 99 downto 0 )
dbg_final_po_fine_tap_cnt  std_logic_vector ( ( 6 * DQS_WIDTH ) - 1 downto 0 )
dbg_final_po_coarse_tap_cnt  std_logic_vector ( ( 3 * DQS_WIDTH ) - 1 downto 0 )
dbg_phy_wrlvl  std_logic_vector ( 255 downto 0 )
dbg_phy_init  std_logic_vector ( 255 downto 0 )
dbg_prbs_rdlvl  std_logic_vector ( 255 downto 0 )
dbg_dqs_found_cal  std_logic_vector ( 255 downto 0 )
dbg_pi_phaselock_start  std_logic
dbg_pi_phaselocked_done  std_logic
dbg_pi_phaselock_err  std_logic
dbg_pi_dqsfound_start  std_logic
dbg_pi_dqsfound_done  std_logic
dbg_pi_dqsfound_err  std_logic
dbg_wrcal_start  std_logic
dbg_wrcal_done  std_logic
dbg_wrcal_err  std_logic
dbg_pi_dqs_found_lanes_phy4lanes  std_logic_vector ( 11 downto 0 )
dbg_pi_phase_locked_phy4lanes  std_logic_vector ( 11 downto 0 )
dbg_oclkdelay_calib_start  std_logic
dbg_oclkdelay_calib_done  std_logic
dbg_phy_oclkdelay_cal  std_logic_vector ( 255 downto 0 )
dbg_oclkdelay_rd_data  std_logic_vector ( ( DRAM_WIDTH * 16 ) - 1 downto 0 )
dbg_rd_data_edge_detect  std_logic_vector ( DQS_WIDTH - 1 downto 0 )
dbg_rddata  std_logic_vector ( ( 2 * nCK_PER_CLK * DQ_WIDTH ) - 1 downto 0 )
dbg_rddata_valid  std_logic
dbg_rdlvl_done  std_logic_vector ( 1 downto 0 )
dbg_rdlvl_err  std_logic_vector ( 1 downto 0 )
dbg_rdlvl_start  std_logic_vector ( 1 downto 0 )
dbg_wrlvl_fine_tap_cnt  std_logic_vector ( ( 6 * DQS_WIDTH ) - 1 downto 0 )
dbg_wrlvl_coarse_tap_cnt  std_logic_vector ( ( 3 * DQS_WIDTH ) - 1 downto 0 )
dbg_tap_cnt_during_wrlvl  std_logic_vector ( 5 downto 0 )
dbg_wl_edge_detect_valid  std_logic
dbg_wrlvl_done  std_logic
dbg_wrlvl_err  std_logic
dbg_wrlvl_start  std_logic
dbg_rddata_r  std_logic_vector ( 63 downto 0 )
dbg_rddata_valid_r  std_logic
ocal_tap_cnt  std_logic_vector ( 53 downto 0 )
dbg_dqs  std_logic_vector ( 4 downto 0 )
dbg_bit  std_logic_vector ( 8 downto 0 )
rd_data_edge_detect_r  std_logic_vector ( 8 downto 0 )
wl_po_fine_cnt  std_logic_vector ( 53 downto 0 )
wl_po_coarse_cnt  std_logic_vector ( 26 downto 0 )
dbg_calib_rd_data_offset_1  std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
dbg_calib_rd_data_offset_2  std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
dbg_data_offset  std_logic_vector ( 5 downto 0 )
dbg_data_offset_1  std_logic_vector ( 5 downto 0 )
dbg_data_offset_2  std_logic_vector ( 5 downto 0 )
all_zeros  std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 ) := ( others = > ' 0 ' )
ddr2_ila_basic_int  std_logic_vector ( 119 downto 0 )
ddr2_ila_wrpath_int  std_logic_vector ( 390 downto 0 )
ddr2_ila_rdpath_int  std_logic_vector ( 1023 downto 0 )
dbg_prbs_final_dqs_tap_cnt_r_int  std_logic_vector ( 11 downto 0 )
dbg_prbs_first_edge_taps_int  std_logic_vector ( 11 downto 0 )
dbg_prbs_second_edge_taps_int  std_logic_vector ( 11 downto 0 )

Instantiations

u_iodelay_ctrl  mig_7series_v4_2_iodelay_ctrl
u_ddr2_clk_ibuf  mig_7series_v4_2_clk_ibuf
u_tempmon  mig_7series_v4_2_tempmon
u_ddr2_infrastructure  mig_7series_v4_2_infrastructure
u_memc_ui_top_std  mig_7series_v4_2_memc_ui_top_std
u_iodelay_ctrl  mig_7series_v4_2_iodelay_ctrl
u_ddr2_clk_ibuf  mig_7series_v4_2_clk_ibuf
u_tempmon  mig_7series_v4_2_tempmon
u_ddr2_infrastructure  mig_7series_v4_2_infrastructure
u_memc_ui_top_std  mig_7series_v4_2_memc_ui_top_std
u_iodelay_ctrl  mig_7series_v4_2_iodelay_ctrl
u_ddr2_clk_ibuf  mig_7series_v4_2_clk_ibuf
u_tempmon  mig_7series_v4_2_tempmon
u_ddr2_infrastructure  mig_7series_v4_2_infrastructure
u_memc_ui_top_std  mig_7series_v4_2_memc_ui_top_std
u_iodelay_ctrl  mig_7series_v4_2_iodelay_ctrl
u_ddr2_clk_ibuf  mig_7series_v4_2_clk_ibuf
u_tempmon  mig_7series_v4_2_tempmon
u_ddr2_infrastructure  mig_7series_v4_2_infrastructure
u_memc_ui_top_std  mig_7series_v4_2_memc_ui_top_std

Detailed Description

Definition at line 523 of file migui_nexys4d_mig.vhd.

Member Function/Procedure/Process Documentation

◆ clogb2() [1/4]

integer clogb2 (   size in integer  
)
Function

Definition at line 527 of file migui_nexys4d_mig.vhd.

◆ ECCWIDTH() [1/4]

integer ECCWIDTH ( )
Function

Definition at line 540 of file migui_nexys4d_mig.vhd.

◆ XWIDTH() [1/4]

integer XWIDTH ( )
Function

Definition at line 565 of file migui_nexys4d_mig.vhd.

◆ TEMP_MON() [1/4]

string TEMP_MON ( )
Function

Definition at line 576 of file migui_nexys4d_mig.vhd.

◆ clogb2() [2/4]

integer clogb2 (   size in integer  
)
Function

Definition at line 527 of file migui_nexys4d_mig_sim.vhd.

◆ ECCWIDTH() [2/4]

integer ECCWIDTH ( )
Function

Definition at line 540 of file migui_nexys4d_mig_sim.vhd.

◆ XWIDTH() [2/4]

integer XWIDTH ( )
Function

Definition at line 565 of file migui_nexys4d_mig_sim.vhd.

◆ TEMP_MON() [2/4]

string TEMP_MON ( )
Function

Definition at line 576 of file migui_nexys4d_mig_sim.vhd.

◆ clogb2() [3/4]

integer clogb2 (   size in integer  
)
Function

Definition at line 527 of file migui_nexys4d_mig.vhd.

◆ ECCWIDTH() [3/4]

integer ECCWIDTH ( )
Function

Definition at line 540 of file migui_nexys4d_mig.vhd.

◆ XWIDTH() [3/4]

integer XWIDTH ( )
Function

Definition at line 565 of file migui_nexys4d_mig.vhd.

◆ TEMP_MON() [3/4]

string TEMP_MON ( )
Function

Definition at line 576 of file migui_nexys4d_mig.vhd.

◆ clogb2() [4/4]

integer clogb2 (   size in integer  
)
Function

Definition at line 527 of file migui_nexys4d_mig_sim.vhd.

◆ ECCWIDTH() [4/4]

integer ECCWIDTH ( )
Function

Definition at line 540 of file migui_nexys4d_mig_sim.vhd.

◆ XWIDTH() [4/4]

integer XWIDTH ( )
Function

Definition at line 565 of file migui_nexys4d_mig_sim.vhd.

◆ TEMP_MON() [4/4]

string TEMP_MON ( )
Function

Definition at line 576 of file migui_nexys4d_mig_sim.vhd.

Member Data Documentation

◆ DATA_WIDTH

DATA_WIDTH integer := 16
Constant

Definition at line 538 of file migui_nexys4d_mig.vhd.

◆ RANK_WIDTH

RANK_WIDTH integer := clogb2 ( RANKS )
Constant

Definition at line 563 of file migui_nexys4d_mig.vhd.

◆ TAPSPERKCLK

TAPSPERKCLK integer := 56
Constant

Definition at line 574 of file migui_nexys4d_mig.vhd.

◆ BM_CNT_WIDTH

BM_CNT_WIDTH integer := clogb2 ( nBANK_MACHS )
Constant

Definition at line 587 of file migui_nexys4d_mig.vhd.

◆ ECC_WIDTH

ECC_WIDTH integer := ECCWIDTH
Constant

Definition at line 588 of file migui_nexys4d_mig.vhd.

◆ DATA_BUF_OFFSET_WIDTH

DATA_BUF_OFFSET_WIDTH integer := 1
Constant

Definition at line 589 of file migui_nexys4d_mig.vhd.

◆ MC_ERR_ADDR_WIDTH

MC_ERR_ADDR_WIDTH integer := XWIDTH+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH + DATA_BUF_OFFSET_WIDTH
Constant

Definition at line 590 of file migui_nexys4d_mig.vhd.

◆ APP_DATA_WIDTH

APP_DATA_WIDTH integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH
Constant

Definition at line 592 of file migui_nexys4d_mig.vhd.

◆ APP_MASK_WIDTH

APP_MASK_WIDTH integer := APP_DATA_WIDTH / 8
Constant

Definition at line 593 of file migui_nexys4d_mig.vhd.

◆ TEMP_MON_EN

TEMP_MON_EN string := TEMP_MON
Constant

Definition at line 594 of file migui_nexys4d_mig.vhd.

◆ tTEMPSAMPLE

tTEMPSAMPLE integer := 10000000
Constant

Definition at line 596 of file migui_nexys4d_mig.vhd.

◆ XADC_CLK_PERIOD

XADC_CLK_PERIOD integer := 5000
Constant

Definition at line 597 of file migui_nexys4d_mig.vhd.

◆ mig_7series_v4_2_iodelay_ctrl

mig_7series_v4_2_iodelay_ctrl
Component

Definition at line 604 of file migui_nexys4d_mig.vhd.

◆ mig_7series_v4_2_clk_ibuf

mig_7series_v4_2_clk_ibuf
Component

Definition at line 628 of file migui_nexys4d_mig.vhd.

◆ mig_7series_v4_2_infrastructure

mig_7series_v4_2_infrastructure
Component

Definition at line 641 of file migui_nexys4d_mig.vhd.

◆ mig_7series_v4_2_tempmon

mig_7series_v4_2_tempmon
Component

Definition at line 703 of file migui_nexys4d_mig.vhd.

◆ mig_7series_v4_2_memc_ui_top_std

mig_7series_v4_2_memc_ui_top_std
Component

Definition at line 719 of file migui_nexys4d_mig.vhd.

◆ bank_mach_next

bank_mach_next std_logic_vector ( BM_CNT_WIDTH - 1 downto 0 )
Signal

Definition at line 1007 of file migui_nexys4d_mig.vhd.

◆ clk

clk std_logic
Signal

Definition at line 1008 of file migui_nexys4d_mig.vhd.

◆ clk_ref

clk_ref std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1009 of file migui_nexys4d_mig.vhd.

◆ iodelay_ctrl_rdy

iodelay_ctrl_rdy std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1010 of file migui_nexys4d_mig.vhd.

◆ clk_ref_in

clk_ref_in std_logic
Signal

Definition at line 1011 of file migui_nexys4d_mig.vhd.

◆ sys_rst_o

sys_rst_o std_logic
Signal

Definition at line 1012 of file migui_nexys4d_mig.vhd.

◆ clk_div2

clk_div2 std_logic
Signal

Definition at line 1013 of file migui_nexys4d_mig.vhd.

◆ rst_div2

rst_div2 std_logic
Signal

Definition at line 1014 of file migui_nexys4d_mig.vhd.

◆ freq_refclk

freq_refclk std_logic
Signal

Definition at line 1015 of file migui_nexys4d_mig.vhd.

◆ mem_refclk

mem_refclk std_logic
Signal

Definition at line 1016 of file migui_nexys4d_mig.vhd.

◆ pll_locked

pll_locked std_logic
Signal

Definition at line 1017 of file migui_nexys4d_mig.vhd.

◆ sync_pulse

sync_pulse std_logic
Signal

Definition at line 1018 of file migui_nexys4d_mig.vhd.

◆ mmcm_ps_clk

mmcm_ps_clk std_logic
Signal

Definition at line 1019 of file migui_nexys4d_mig.vhd.

◆ poc_sample_pd

poc_sample_pd std_logic
Signal

Definition at line 1020 of file migui_nexys4d_mig.vhd.

◆ psen

psen std_logic
Signal

Definition at line 1021 of file migui_nexys4d_mig.vhd.

◆ psincdec

psincdec std_logic
Signal

Definition at line 1022 of file migui_nexys4d_mig.vhd.

◆ psdone

psdone std_logic
Signal

Definition at line 1023 of file migui_nexys4d_mig.vhd.

◆ iddr_rst

iddr_rst std_logic
Signal

Definition at line 1024 of file migui_nexys4d_mig.vhd.

◆ ref_dll_lock

ref_dll_lock std_logic
Signal

Definition at line 1025 of file migui_nexys4d_mig.vhd.

◆ rst_phaser_ref

rst_phaser_ref std_logic
Signal

Definition at line 1026 of file migui_nexys4d_mig.vhd.

◆ rst

rst std_logic
Signal

Definition at line 1028 of file migui_nexys4d_mig.vhd.

◆ app_ecc_multiple_err

app_ecc_multiple_err std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 )
Signal

Definition at line 1030 of file migui_nexys4d_mig.vhd.

◆ app_ecc_single_err

app_ecc_single_err std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 )
Signal

Definition at line 1031 of file migui_nexys4d_mig.vhd.

◆ ddr2_reset_n

ddr2_reset_n std_logic
Signal

Definition at line 1032 of file migui_nexys4d_mig.vhd.

◆ ddr2_parity

ddr2_parity std_logic
Signal

Definition at line 1034 of file migui_nexys4d_mig.vhd.

◆ init_calib_complete_i

init_calib_complete_i std_logic
Signal

Definition at line 1036 of file migui_nexys4d_mig.vhd.

◆ sys_clk_p

sys_clk_p std_logic
Signal

Definition at line 1038 of file migui_nexys4d_mig.vhd.

◆ sys_clk_n

sys_clk_n std_logic
Signal

Definition at line 1039 of file migui_nexys4d_mig.vhd.

◆ mmcm_clk

mmcm_clk std_logic
Signal

Definition at line 1040 of file migui_nexys4d_mig.vhd.

◆ clk_ref_p

clk_ref_p std_logic
Signal

Definition at line 1041 of file migui_nexys4d_mig.vhd.

◆ clk_ref_n

clk_ref_n std_logic
Signal

Definition at line 1042 of file migui_nexys4d_mig.vhd.

◆ device_temp_s

device_temp_s std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1043 of file migui_nexys4d_mig.vhd.

◆ dbg_idel_down_all

dbg_idel_down_all std_logic
Signal

Definition at line 1046 of file migui_nexys4d_mig.vhd.

◆ dbg_idel_down_cpt

dbg_idel_down_cpt std_logic
Signal

Definition at line 1047 of file migui_nexys4d_mig.vhd.

◆ dbg_idel_up_all

dbg_idel_up_all std_logic
Signal

Definition at line 1048 of file migui_nexys4d_mig.vhd.

◆ dbg_idel_up_cpt

dbg_idel_up_cpt std_logic
Signal

Definition at line 1049 of file migui_nexys4d_mig.vhd.

◆ dbg_sel_all_idel_cpt

dbg_sel_all_idel_cpt std_logic
Signal

Definition at line 1050 of file migui_nexys4d_mig.vhd.

◆ dbg_sel_idel_cpt

dbg_sel_idel_cpt std_logic_vector ( DQS_CNT_WIDTH - 1 downto 0 )
Signal

Definition at line 1051 of file migui_nexys4d_mig.vhd.

◆ dbg_po_f_stg23_sel

dbg_po_f_stg23_sel std_logic
Signal

Definition at line 1052 of file migui_nexys4d_mig.vhd.

◆ dbg_sel_pi_incdec

dbg_sel_pi_incdec std_logic
Signal

Definition at line 1053 of file migui_nexys4d_mig.vhd.

◆ dbg_sel_po_incdec

dbg_sel_po_incdec std_logic
Signal

Definition at line 1054 of file migui_nexys4d_mig.vhd.

◆ dbg_byte_sel

dbg_byte_sel std_logic_vector ( DQS_CNT_WIDTH downto 0 )
Signal

Definition at line 1055 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_f_inc

dbg_pi_f_inc std_logic
Signal

Definition at line 1056 of file migui_nexys4d_mig.vhd.

◆ dbg_po_f_inc

dbg_po_f_inc std_logic
Signal

Definition at line 1057 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_f_dec

dbg_pi_f_dec std_logic
Signal

Definition at line 1058 of file migui_nexys4d_mig.vhd.

◆ dbg_po_f_dec

dbg_po_f_dec std_logic
Signal

Definition at line 1059 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_counter_read_val

dbg_pi_counter_read_val std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1060 of file migui_nexys4d_mig.vhd.

◆ dbg_po_counter_read_val

dbg_po_counter_read_val std_logic_vector ( 8 downto 0 )
Signal

Definition at line 1061 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_final_dqs_tap_cnt_r

dbg_prbs_final_dqs_tap_cnt_r std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1062 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_first_edge_taps

dbg_prbs_first_edge_taps std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1063 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_second_edge_taps

dbg_prbs_second_edge_taps std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1064 of file migui_nexys4d_mig.vhd.

◆ dbg_cpt_tap_cnt

dbg_cpt_tap_cnt std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
Signal

Definition at line 1065 of file migui_nexys4d_mig.vhd.

◆ dbg_dq_idelay_tap_cnt

dbg_dq_idelay_tap_cnt std_logic_vector ( ( 5 * DQS_WIDTH * RANKS ) - 1 downto 0 )
Signal

Definition at line 1066 of file migui_nexys4d_mig.vhd.

◆ dbg_calib_top

dbg_calib_top std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1067 of file migui_nexys4d_mig.vhd.

◆ dbg_cpt_first_edge_cnt

dbg_cpt_first_edge_cnt std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
Signal

Definition at line 1068 of file migui_nexys4d_mig.vhd.

◆ dbg_cpt_second_edge_cnt

dbg_cpt_second_edge_cnt std_logic_vector ( ( 6 * DQS_WIDTH * RANKS ) - 1 downto 0 )
Signal

Definition at line 1069 of file migui_nexys4d_mig.vhd.

◆ dbg_rd_data_offset

dbg_rd_data_offset std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
Signal

Definition at line 1070 of file migui_nexys4d_mig.vhd.

◆ dbg_phy_rdlvl

dbg_phy_rdlvl std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1071 of file migui_nexys4d_mig.vhd.

◆ dbg_phy_wrcal

dbg_phy_wrcal std_logic_vector ( 99 downto 0 )
Signal

Definition at line 1072 of file migui_nexys4d_mig.vhd.

◆ dbg_final_po_fine_tap_cnt

dbg_final_po_fine_tap_cnt std_logic_vector ( ( 6 * DQS_WIDTH ) - 1 downto 0 )
Signal

Definition at line 1073 of file migui_nexys4d_mig.vhd.

◆ dbg_final_po_coarse_tap_cnt

dbg_final_po_coarse_tap_cnt std_logic_vector ( ( 3 * DQS_WIDTH ) - 1 downto 0 )
Signal

Definition at line 1074 of file migui_nexys4d_mig.vhd.

◆ dbg_phy_wrlvl

dbg_phy_wrlvl std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1075 of file migui_nexys4d_mig.vhd.

◆ dbg_phy_init

dbg_phy_init std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1076 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_rdlvl

dbg_prbs_rdlvl std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1077 of file migui_nexys4d_mig.vhd.

◆ dbg_dqs_found_cal

dbg_dqs_found_cal std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1078 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_phaselock_start

dbg_pi_phaselock_start std_logic
Signal

Definition at line 1079 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_phaselocked_done

dbg_pi_phaselocked_done std_logic
Signal

Definition at line 1080 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_phaselock_err

dbg_pi_phaselock_err std_logic
Signal

Definition at line 1081 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_dqsfound_start

dbg_pi_dqsfound_start std_logic
Signal

Definition at line 1082 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_dqsfound_done

dbg_pi_dqsfound_done std_logic
Signal

Definition at line 1083 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_dqsfound_err

dbg_pi_dqsfound_err std_logic
Signal

Definition at line 1084 of file migui_nexys4d_mig.vhd.

◆ dbg_wrcal_start

dbg_wrcal_start std_logic
Signal

Definition at line 1085 of file migui_nexys4d_mig.vhd.

◆ dbg_wrcal_done

dbg_wrcal_done std_logic
Signal

Definition at line 1086 of file migui_nexys4d_mig.vhd.

◆ dbg_wrcal_err

dbg_wrcal_err std_logic
Signal

Definition at line 1087 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_dqs_found_lanes_phy4lanes

dbg_pi_dqs_found_lanes_phy4lanes std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1088 of file migui_nexys4d_mig.vhd.

◆ dbg_pi_phase_locked_phy4lanes

dbg_pi_phase_locked_phy4lanes std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1089 of file migui_nexys4d_mig.vhd.

◆ dbg_oclkdelay_calib_start

dbg_oclkdelay_calib_start std_logic
Signal

Definition at line 1090 of file migui_nexys4d_mig.vhd.

◆ dbg_oclkdelay_calib_done

dbg_oclkdelay_calib_done std_logic
Signal

Definition at line 1091 of file migui_nexys4d_mig.vhd.

◆ dbg_phy_oclkdelay_cal

dbg_phy_oclkdelay_cal std_logic_vector ( 255 downto 0 )
Signal

Definition at line 1092 of file migui_nexys4d_mig.vhd.

◆ dbg_oclkdelay_rd_data

dbg_oclkdelay_rd_data std_logic_vector ( ( DRAM_WIDTH * 16 ) - 1 downto 0 )
Signal

Definition at line 1093 of file migui_nexys4d_mig.vhd.

◆ dbg_rd_data_edge_detect

dbg_rd_data_edge_detect std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Signal

Definition at line 1094 of file migui_nexys4d_mig.vhd.

◆ dbg_rddata

dbg_rddata std_logic_vector ( ( 2 * nCK_PER_CLK * DQ_WIDTH ) - 1 downto 0 )
Signal

Definition at line 1095 of file migui_nexys4d_mig.vhd.

◆ dbg_rddata_valid

dbg_rddata_valid std_logic
Signal

Definition at line 1096 of file migui_nexys4d_mig.vhd.

◆ dbg_rdlvl_done

dbg_rdlvl_done std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1097 of file migui_nexys4d_mig.vhd.

◆ dbg_rdlvl_err

dbg_rdlvl_err std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1098 of file migui_nexys4d_mig.vhd.

◆ dbg_rdlvl_start

dbg_rdlvl_start std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1099 of file migui_nexys4d_mig.vhd.

◆ dbg_wrlvl_fine_tap_cnt

dbg_wrlvl_fine_tap_cnt std_logic_vector ( ( 6 * DQS_WIDTH ) - 1 downto 0 )
Signal

Definition at line 1100 of file migui_nexys4d_mig.vhd.

◆ dbg_wrlvl_coarse_tap_cnt

dbg_wrlvl_coarse_tap_cnt std_logic_vector ( ( 3 * DQS_WIDTH ) - 1 downto 0 )
Signal

Definition at line 1101 of file migui_nexys4d_mig.vhd.

◆ dbg_tap_cnt_during_wrlvl

dbg_tap_cnt_during_wrlvl std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1102 of file migui_nexys4d_mig.vhd.

◆ dbg_wl_edge_detect_valid

dbg_wl_edge_detect_valid std_logic
Signal

Definition at line 1103 of file migui_nexys4d_mig.vhd.

◆ dbg_wrlvl_done

dbg_wrlvl_done std_logic
Signal

Definition at line 1104 of file migui_nexys4d_mig.vhd.

◆ dbg_wrlvl_err

dbg_wrlvl_err std_logic
Signal

Definition at line 1105 of file migui_nexys4d_mig.vhd.

◆ dbg_wrlvl_start

dbg_wrlvl_start std_logic
Signal

Definition at line 1106 of file migui_nexys4d_mig.vhd.

◆ dbg_rddata_r

dbg_rddata_r std_logic_vector ( 63 downto 0 )
Signal

Definition at line 1107 of file migui_nexys4d_mig.vhd.

◆ dbg_rddata_valid_r

dbg_rddata_valid_r std_logic
Signal

Definition at line 1108 of file migui_nexys4d_mig.vhd.

◆ ocal_tap_cnt

ocal_tap_cnt std_logic_vector ( 53 downto 0 )
Signal

Definition at line 1109 of file migui_nexys4d_mig.vhd.

◆ dbg_dqs

dbg_dqs std_logic_vector ( 4 downto 0 )
Signal

Definition at line 1110 of file migui_nexys4d_mig.vhd.

◆ dbg_bit

dbg_bit std_logic_vector ( 8 downto 0 )
Signal

Definition at line 1111 of file migui_nexys4d_mig.vhd.

◆ rd_data_edge_detect_r

rd_data_edge_detect_r std_logic_vector ( 8 downto 0 )
Signal

Definition at line 1112 of file migui_nexys4d_mig.vhd.

◆ wl_po_fine_cnt

wl_po_fine_cnt std_logic_vector ( 53 downto 0 )
Signal

Definition at line 1113 of file migui_nexys4d_mig.vhd.

◆ wl_po_coarse_cnt

wl_po_coarse_cnt std_logic_vector ( 26 downto 0 )
Signal

Definition at line 1114 of file migui_nexys4d_mig.vhd.

◆ dbg_calib_rd_data_offset_1

dbg_calib_rd_data_offset_1 std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
Signal

Definition at line 1115 of file migui_nexys4d_mig.vhd.

◆ dbg_calib_rd_data_offset_2

dbg_calib_rd_data_offset_2 std_logic_vector ( ( 6 * RANKS ) - 1 downto 0 )
Signal

Definition at line 1116 of file migui_nexys4d_mig.vhd.

◆ dbg_data_offset

dbg_data_offset std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1117 of file migui_nexys4d_mig.vhd.

◆ dbg_data_offset_1

dbg_data_offset_1 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1118 of file migui_nexys4d_mig.vhd.

◆ dbg_data_offset_2

dbg_data_offset_2 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1119 of file migui_nexys4d_mig.vhd.

◆ all_zeros

all_zeros std_logic_vector ( ( 2 * nCK_PER_CLK ) - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 1120 of file migui_nexys4d_mig.vhd.

◆ ddr2_ila_basic_int

ddr2_ila_basic_int std_logic_vector ( 119 downto 0 )
Signal

Definition at line 1122 of file migui_nexys4d_mig.vhd.

◆ ddr2_ila_wrpath_int

ddr2_ila_wrpath_int std_logic_vector ( 390 downto 0 )
Signal

Definition at line 1123 of file migui_nexys4d_mig.vhd.

◆ ddr2_ila_rdpath_int

ddr2_ila_rdpath_int std_logic_vector ( 1023 downto 0 )
Signal

Definition at line 1124 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_final_dqs_tap_cnt_r_int

dbg_prbs_final_dqs_tap_cnt_r_int std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1125 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_first_edge_taps_int

dbg_prbs_first_edge_taps_int std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1126 of file migui_nexys4d_mig.vhd.

◆ dbg_prbs_second_edge_taps_int

dbg_prbs_second_edge_taps_int std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1127 of file migui_nexys4d_mig.vhd.

◆ u_iodelay_ctrl [1/4]

u_iodelay_ctrl mig_7series_v4_2_iodelay_ctrl
Instantiation

Definition at line 1182 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_clk_ibuf [1/4]

u_ddr2_clk_ibuf mig_7series_v4_2_clk_ibuf
Instantiation

Definition at line 1195 of file migui_nexys4d_mig_sim.vhd.

◆ u_tempmon [1/4]

u_tempmon mig_7series_v4_2_tempmon
Instantiation

Definition at line 1214 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_infrastructure [1/4]

u_ddr2_infrastructure mig_7series_v4_2_infrastructure
Instantiation

Definition at line 1273 of file migui_nexys4d_mig_sim.vhd.

◆ u_memc_ui_top_std [1/4]

u_memc_ui_top_std mig_7series_v4_2_memc_ui_top_std
Instantiation

Definition at line 1554 of file migui_nexys4d_mig_sim.vhd.

◆ u_iodelay_ctrl [2/4]

u_iodelay_ctrl mig_7series_v4_2_iodelay_ctrl
Instantiation

Definition at line 1182 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_clk_ibuf [2/4]

u_ddr2_clk_ibuf mig_7series_v4_2_clk_ibuf
Instantiation

Definition at line 1195 of file migui_nexys4d_mig_sim.vhd.

◆ u_tempmon [2/4]

u_tempmon mig_7series_v4_2_tempmon
Instantiation

Definition at line 1214 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_infrastructure [2/4]

u_ddr2_infrastructure mig_7series_v4_2_infrastructure
Instantiation

Definition at line 1273 of file migui_nexys4d_mig_sim.vhd.

◆ u_memc_ui_top_std [2/4]

u_memc_ui_top_std mig_7series_v4_2_memc_ui_top_std
Instantiation

Definition at line 1554 of file migui_nexys4d_mig_sim.vhd.

◆ u_iodelay_ctrl [3/4]

u_iodelay_ctrl mig_7series_v4_2_iodelay_ctrl
Instantiation

Definition at line 1182 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_clk_ibuf [3/4]

u_ddr2_clk_ibuf mig_7series_v4_2_clk_ibuf
Instantiation

Definition at line 1195 of file migui_nexys4d_mig_sim.vhd.

◆ u_tempmon [3/4]

u_tempmon mig_7series_v4_2_tempmon
Instantiation

Definition at line 1214 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_infrastructure [3/4]

u_ddr2_infrastructure mig_7series_v4_2_infrastructure
Instantiation

Definition at line 1273 of file migui_nexys4d_mig_sim.vhd.

◆ u_memc_ui_top_std [3/4]

u_memc_ui_top_std mig_7series_v4_2_memc_ui_top_std
Instantiation

Definition at line 1554 of file migui_nexys4d_mig_sim.vhd.

◆ u_iodelay_ctrl [4/4]

u_iodelay_ctrl mig_7series_v4_2_iodelay_ctrl
Instantiation

Definition at line 1182 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_clk_ibuf [4/4]

u_ddr2_clk_ibuf mig_7series_v4_2_clk_ibuf
Instantiation

Definition at line 1195 of file migui_nexys4d_mig_sim.vhd.

◆ u_tempmon [4/4]

u_tempmon mig_7series_v4_2_tempmon
Instantiation

Definition at line 1214 of file migui_nexys4d_mig_sim.vhd.

◆ u_ddr2_infrastructure [4/4]

u_ddr2_infrastructure mig_7series_v4_2_infrastructure
Instantiation

Definition at line 1273 of file migui_nexys4d_mig_sim.vhd.

◆ u_memc_ui_top_std [4/4]

u_memc_ui_top_std mig_7series_v4_2_memc_ui_top_std
Instantiation

Definition at line 1554 of file migui_nexys4d_mig_sim.vhd.

The documentation for this design unit was generated from the following files: