syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )

Signals
R_LED	slv4 := ( others = > ' 0 ' )
R_RGB_R	slv2 := ( others = > ' 0 ' )
R_RGB_G	slv2 := ( others = > ' 0 ' )
R_RGB_B	slv2 := ( others = > ' 0 ' )

Detailed Description

Definition at line 77 of file pdp11_hio70_artys7.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 86 of file pdp11_hio70_artys7.vhd.

Member Data Documentation

R_LED

R_LED slv4 := ( others = > ' 0 ' )

Signal

Definition at line 79 of file pdp11_hio70_artys7.vhd.

R_RGB_R

R_RGB_R slv2 := ( others = > ' 0 ' )

Signal

Definition at line 80 of file pdp11_hio70_artys7.vhd.

R_RGB_G

R_RGB_G slv2 := ( others = > ' 0 ' )

Signal

Definition at line 81 of file pdp11_hio70_artys7.vhd.

R_RGB_B

R_RGB_B slv2 := ( others = > ' 0 ' )

Signal

Definition at line 82 of file pdp11_hio70_artys7.vhd.

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The documentation for this design unit was generated from the following file:

• sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vhd